2 * Author: MontaVista Software, Inc.
5 * Based on the OMAP devices.c
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/init.h>
32 #include <linux/platform_device.h>
33 #include <linux/gpio.h>
34 #include <linux/dma-mapping.h>
36 #include <mach/irqs.h>
37 #include <mach/hardware.h>
38 #include <mach/common.h>
44 * SPI master controller
46 * - i.MX1: 2 channel (slighly different register setting)
50 static struct resource mxc_spi_resources0
[] = {
52 .start
= CSPI1_BASE_ADDR
,
53 .end
= CSPI1_BASE_ADDR
+ SZ_4K
- 1,
54 .flags
= IORESOURCE_MEM
,
56 .start
= MXC_INT_CSPI1
,
58 .flags
= IORESOURCE_IRQ
,
62 static struct resource mxc_spi_resources1
[] = {
64 .start
= CSPI2_BASE_ADDR
,
65 .end
= CSPI2_BASE_ADDR
+ SZ_4K
- 1,
66 .flags
= IORESOURCE_MEM
,
68 .start
= MXC_INT_CSPI2
,
70 .flags
= IORESOURCE_IRQ
,
74 #ifdef CONFIG_MACH_MX27
75 static struct resource mxc_spi_resources2
[] = {
77 .start
= CSPI3_BASE_ADDR
,
78 .end
= CSPI3_BASE_ADDR
+ SZ_4K
- 1,
79 .flags
= IORESOURCE_MEM
,
81 .start
= MXC_INT_CSPI3
,
83 .flags
= IORESOURCE_IRQ
,
88 struct platform_device mxc_spi_device0
= {
91 .num_resources
= ARRAY_SIZE(mxc_spi_resources0
),
92 .resource
= mxc_spi_resources0
,
95 struct platform_device mxc_spi_device1
= {
98 .num_resources
= ARRAY_SIZE(mxc_spi_resources1
),
99 .resource
= mxc_spi_resources1
,
102 #ifdef CONFIG_MACH_MX27
103 struct platform_device mxc_spi_device2
= {
106 .num_resources
= ARRAY_SIZE(mxc_spi_resources2
),
107 .resource
= mxc_spi_resources2
,
112 * General Purpose Timer
117 /* We use gpt0 as system timer, so do not add a device for this one */
119 static struct resource timer1_resources
[] = {
121 .start
= GPT2_BASE_ADDR
,
122 .end
= GPT2_BASE_ADDR
+ 0x17,
123 .flags
= IORESOURCE_MEM
,
125 .start
= MXC_INT_GPT2
,
127 .flags
= IORESOURCE_IRQ
,
131 struct platform_device mxc_gpt1
= {
134 .num_resources
= ARRAY_SIZE(timer1_resources
),
135 .resource
= timer1_resources
,
138 static struct resource timer2_resources
[] = {
140 .start
= GPT3_BASE_ADDR
,
141 .end
= GPT3_BASE_ADDR
+ 0x17,
142 .flags
= IORESOURCE_MEM
,
144 .start
= MXC_INT_GPT3
,
146 .flags
= IORESOURCE_IRQ
,
150 struct platform_device mxc_gpt2
= {
153 .num_resources
= ARRAY_SIZE(timer2_resources
),
154 .resource
= timer2_resources
,
157 #ifdef CONFIG_MACH_MX27
158 static struct resource timer3_resources
[] = {
160 .start
= GPT4_BASE_ADDR
,
161 .end
= GPT4_BASE_ADDR
+ 0x17,
162 .flags
= IORESOURCE_MEM
,
164 .start
= MXC_INT_GPT4
,
166 .flags
= IORESOURCE_IRQ
,
170 struct platform_device mxc_gpt3
= {
173 .num_resources
= ARRAY_SIZE(timer3_resources
),
174 .resource
= timer3_resources
,
177 static struct resource timer4_resources
[] = {
179 .start
= GPT5_BASE_ADDR
,
180 .end
= GPT5_BASE_ADDR
+ 0x17,
181 .flags
= IORESOURCE_MEM
,
183 .start
= MXC_INT_GPT5
,
185 .flags
= IORESOURCE_IRQ
,
189 struct platform_device mxc_gpt4
= {
192 .num_resources
= ARRAY_SIZE(timer4_resources
),
193 .resource
= timer4_resources
,
196 static struct resource timer5_resources
[] = {
198 .start
= GPT6_BASE_ADDR
,
199 .end
= GPT6_BASE_ADDR
+ 0x17,
200 .flags
= IORESOURCE_MEM
,
202 .start
= MXC_INT_GPT6
,
204 .flags
= IORESOURCE_IRQ
,
208 struct platform_device mxc_gpt5
= {
211 .num_resources
= ARRAY_SIZE(timer5_resources
),
212 .resource
= timer5_resources
,
222 static struct resource mxc_wdt_resources
[] = {
224 .start
= WDOG_BASE_ADDR
,
225 .end
= WDOG_BASE_ADDR
+ 0x30,
226 .flags
= IORESOURCE_MEM
,
230 struct platform_device mxc_wdt
= {
233 .num_resources
= ARRAY_SIZE(mxc_wdt_resources
),
234 .resource
= mxc_wdt_resources
,
237 static struct resource mxc_w1_master_resources
[] = {
239 .start
= OWIRE_BASE_ADDR
,
240 .end
= OWIRE_BASE_ADDR
+ SZ_4K
- 1,
241 .flags
= IORESOURCE_MEM
,
245 struct platform_device mxc_w1_master_device
= {
248 .num_resources
= ARRAY_SIZE(mxc_w1_master_resources
),
249 .resource
= mxc_w1_master_resources
,
252 static struct resource mxc_nand_resources
[] = {
254 .start
= NFC_BASE_ADDR
,
255 .end
= NFC_BASE_ADDR
+ 0xfff,
256 .flags
= IORESOURCE_MEM
,
258 .start
= MXC_INT_NANDFC
,
259 .end
= MXC_INT_NANDFC
,
260 .flags
= IORESOURCE_IRQ
,
264 struct platform_device mxc_nand_device
= {
267 .num_resources
= ARRAY_SIZE(mxc_nand_resources
),
268 .resource
= mxc_nand_resources
,
273 * - i.MX1: the basic controller
274 * - i.MX21: to be checked
275 * - i.MX27: like i.MX1, with slightly variations
277 static struct resource mxc_fb
[] = {
279 .start
= LCDC_BASE_ADDR
,
280 .end
= LCDC_BASE_ADDR
+ 0xFFF,
281 .flags
= IORESOURCE_MEM
,
283 .start
= MXC_INT_LCDC
,
285 .flags
= IORESOURCE_IRQ
,
290 struct platform_device mxc_fb_device
= {
293 .num_resources
= ARRAY_SIZE(mxc_fb
),
296 .coherent_dma_mask
= DMA_BIT_MASK(32),
300 #ifdef CONFIG_MACH_MX27
301 static struct resource mxc_fec_resources
[] = {
303 .start
= FEC_BASE_ADDR
,
304 .end
= FEC_BASE_ADDR
+ 0xfff,
305 .flags
= IORESOURCE_MEM
,
307 .start
= MXC_INT_FEC
,
309 .flags
= IORESOURCE_IRQ
,
313 struct platform_device mxc_fec_device
= {
316 .num_resources
= ARRAY_SIZE(mxc_fec_resources
),
317 .resource
= mxc_fec_resources
,
321 static struct resource mxc_i2c_1_resources
[] = {
323 .start
= I2C_BASE_ADDR
,
324 .end
= I2C_BASE_ADDR
+ 0x0fff,
325 .flags
= IORESOURCE_MEM
,
327 .start
= MXC_INT_I2C
,
329 .flags
= IORESOURCE_IRQ
,
333 struct platform_device mxc_i2c_device0
= {
336 .num_resources
= ARRAY_SIZE(mxc_i2c_1_resources
),
337 .resource
= mxc_i2c_1_resources
,
340 #ifdef CONFIG_MACH_MX27
341 static struct resource mxc_i2c_2_resources
[] = {
343 .start
= I2C2_BASE_ADDR
,
344 .end
= I2C2_BASE_ADDR
+ 0x0fff,
345 .flags
= IORESOURCE_MEM
,
347 .start
= MXC_INT_I2C2
,
349 .flags
= IORESOURCE_IRQ
,
353 struct platform_device mxc_i2c_device1
= {
356 .num_resources
= ARRAY_SIZE(mxc_i2c_2_resources
),
357 .resource
= mxc_i2c_2_resources
,
361 static struct resource mxc_pwm_resources
[] = {
363 .start
= PWM_BASE_ADDR
,
364 .end
= PWM_BASE_ADDR
+ 0x0fff,
365 .flags
= IORESOURCE_MEM
,
367 .start
= MXC_INT_PWM
,
369 .flags
= IORESOURCE_IRQ
,
373 struct platform_device mxc_pwm_device
= {
376 .num_resources
= ARRAY_SIZE(mxc_pwm_resources
),
377 .resource
= mxc_pwm_resources
,
381 * Resource definition for the MXC SDHC
383 static struct resource mxc_sdhc1_resources
[] = {
385 .start
= SDHC1_BASE_ADDR
,
386 .end
= SDHC1_BASE_ADDR
+ SZ_4K
- 1,
387 .flags
= IORESOURCE_MEM
,
389 .start
= MXC_INT_SDHC1
,
390 .end
= MXC_INT_SDHC1
,
391 .flags
= IORESOURCE_IRQ
,
393 .start
= DMA_REQ_SDHC1
,
394 .end
= DMA_REQ_SDHC1
,
395 .flags
= IORESOURCE_DMA
,
399 static u64 mxc_sdhc1_dmamask
= DMA_BIT_MASK(32);
401 struct platform_device mxc_sdhc_device0
= {
405 .dma_mask
= &mxc_sdhc1_dmamask
,
406 .coherent_dma_mask
= DMA_BIT_MASK(32),
408 .num_resources
= ARRAY_SIZE(mxc_sdhc1_resources
),
409 .resource
= mxc_sdhc1_resources
,
412 static struct resource mxc_sdhc2_resources
[] = {
414 .start
= SDHC2_BASE_ADDR
,
415 .end
= SDHC2_BASE_ADDR
+ SZ_4K
- 1,
416 .flags
= IORESOURCE_MEM
,
418 .start
= MXC_INT_SDHC2
,
419 .end
= MXC_INT_SDHC2
,
420 .flags
= IORESOURCE_IRQ
,
422 .start
= DMA_REQ_SDHC2
,
423 .end
= DMA_REQ_SDHC2
,
424 .flags
= IORESOURCE_DMA
,
428 static u64 mxc_sdhc2_dmamask
= DMA_BIT_MASK(32);
430 struct platform_device mxc_sdhc_device1
= {
434 .dma_mask
= &mxc_sdhc2_dmamask
,
435 .coherent_dma_mask
= DMA_BIT_MASK(32),
437 .num_resources
= ARRAY_SIZE(mxc_sdhc2_resources
),
438 .resource
= mxc_sdhc2_resources
,
441 #ifdef CONFIG_MACH_MX27
442 static struct resource otg_resources
[] = {
444 .start
= OTG_BASE_ADDR
,
445 .end
= OTG_BASE_ADDR
+ 0x1ff,
446 .flags
= IORESOURCE_MEM
,
448 .start
= MXC_INT_USB3
,
450 .flags
= IORESOURCE_IRQ
,
454 static u64 otg_dmamask
= DMA_BIT_MASK(32);
456 /* OTG gadget device */
457 struct platform_device mxc_otg_udc_device
= {
458 .name
= "fsl-usb2-udc",
461 .dma_mask
= &otg_dmamask
,
462 .coherent_dma_mask
= DMA_BIT_MASK(32),
464 .resource
= otg_resources
,
465 .num_resources
= ARRAY_SIZE(otg_resources
),
469 struct platform_device mxc_otg_host
= {
473 .coherent_dma_mask
= DMA_BIT_MASK(32),
474 .dma_mask
= &otg_dmamask
,
476 .resource
= otg_resources
,
477 .num_resources
= ARRAY_SIZE(otg_resources
),
482 static u64 usbh1_dmamask
= DMA_BIT_MASK(32);
484 static struct resource mxc_usbh1_resources
[] = {
486 .start
= OTG_BASE_ADDR
+ 0x200,
487 .end
= OTG_BASE_ADDR
+ 0x3ff,
488 .flags
= IORESOURCE_MEM
,
490 .start
= MXC_INT_USB1
,
492 .flags
= IORESOURCE_IRQ
,
496 struct platform_device mxc_usbh1
= {
500 .coherent_dma_mask
= DMA_BIT_MASK(32),
501 .dma_mask
= &usbh1_dmamask
,
503 .resource
= mxc_usbh1_resources
,
504 .num_resources
= ARRAY_SIZE(mxc_usbh1_resources
),
508 static u64 usbh2_dmamask
= DMA_BIT_MASK(32);
510 static struct resource mxc_usbh2_resources
[] = {
512 .start
= OTG_BASE_ADDR
+ 0x400,
513 .end
= OTG_BASE_ADDR
+ 0x5ff,
514 .flags
= IORESOURCE_MEM
,
516 .start
= MXC_INT_USB2
,
518 .flags
= IORESOURCE_IRQ
,
522 struct platform_device mxc_usbh2
= {
526 .coherent_dma_mask
= DMA_BIT_MASK(32),
527 .dma_mask
= &usbh2_dmamask
,
529 .resource
= mxc_usbh2_resources
,
530 .num_resources
= ARRAY_SIZE(mxc_usbh2_resources
),
534 static struct resource imx_ssi_resources0
[] = {
536 .start
= SSI1_BASE_ADDR
,
537 .end
= SSI1_BASE_ADDR
+ 0x6F,
538 .flags
= IORESOURCE_MEM
,
540 .start
= MXC_INT_SSI1
,
542 .flags
= IORESOURCE_IRQ
,
545 .start
= DMA_REQ_SSI1_TX0
,
546 .end
= DMA_REQ_SSI1_TX0
,
547 .flags
= IORESOURCE_DMA
,
550 .start
= DMA_REQ_SSI1_RX0
,
551 .end
= DMA_REQ_SSI1_RX0
,
552 .flags
= IORESOURCE_DMA
,
555 .start
= DMA_REQ_SSI1_TX1
,
556 .end
= DMA_REQ_SSI1_TX1
,
557 .flags
= IORESOURCE_DMA
,
560 .start
= DMA_REQ_SSI1_RX1
,
561 .end
= DMA_REQ_SSI1_RX1
,
562 .flags
= IORESOURCE_DMA
,
566 static struct resource imx_ssi_resources1
[] = {
568 .start
= SSI2_BASE_ADDR
,
569 .end
= SSI2_BASE_ADDR
+ 0x6F,
570 .flags
= IORESOURCE_MEM
,
572 .start
= MXC_INT_SSI2
,
574 .flags
= IORESOURCE_IRQ
,
577 .start
= DMA_REQ_SSI2_TX0
,
578 .end
= DMA_REQ_SSI2_TX0
,
579 .flags
= IORESOURCE_DMA
,
582 .start
= DMA_REQ_SSI2_RX0
,
583 .end
= DMA_REQ_SSI2_RX0
,
584 .flags
= IORESOURCE_DMA
,
587 .start
= DMA_REQ_SSI2_TX1
,
588 .end
= DMA_REQ_SSI2_TX1
,
589 .flags
= IORESOURCE_DMA
,
592 .start
= DMA_REQ_SSI2_RX1
,
593 .end
= DMA_REQ_SSI2_RX1
,
594 .flags
= IORESOURCE_DMA
,
598 struct platform_device imx_ssi_device0
= {
601 .num_resources
= ARRAY_SIZE(imx_ssi_resources0
),
602 .resource
= imx_ssi_resources0
,
605 struct platform_device imx_ssi_device1
= {
608 .num_resources
= ARRAY_SIZE(imx_ssi_resources1
),
609 .resource
= imx_ssi_resources1
,
612 /* GPIO port description */
613 static struct mxc_gpio_port imx_gpio_ports
[] = {
615 .chip
.label
= "gpio-0",
617 .base
= IO_ADDRESS(GPIO_BASE_ADDR
),
618 .virtual_irq_start
= MXC_GPIO_IRQ_START
,
620 .chip
.label
= "gpio-1",
621 .base
= IO_ADDRESS(GPIO_BASE_ADDR
+ 0x100),
622 .virtual_irq_start
= MXC_GPIO_IRQ_START
+ 32,
624 .chip
.label
= "gpio-2",
625 .base
= IO_ADDRESS(GPIO_BASE_ADDR
+ 0x200),
626 .virtual_irq_start
= MXC_GPIO_IRQ_START
+ 64,
628 .chip
.label
= "gpio-3",
629 .base
= IO_ADDRESS(GPIO_BASE_ADDR
+ 0x300),
630 .virtual_irq_start
= MXC_GPIO_IRQ_START
+ 96,
632 .chip
.label
= "gpio-4",
633 .base
= IO_ADDRESS(GPIO_BASE_ADDR
+ 0x400),
634 .virtual_irq_start
= MXC_GPIO_IRQ_START
+ 128,
636 .chip
.label
= "gpio-5",
637 .base
= IO_ADDRESS(GPIO_BASE_ADDR
+ 0x500),
638 .virtual_irq_start
= MXC_GPIO_IRQ_START
+ 160,
642 int __init
mxc_register_gpios(void)
644 return mxc_gpio_init(imx_gpio_ports
, ARRAY_SIZE(imx_gpio_ports
));
647 #ifdef CONFIG_MACH_MX21
648 static struct resource mx21_usbhc_resources
[] = {
650 .start
= USBOTG_BASE_ADDR
,
651 .end
= USBOTG_BASE_ADDR
+ 0x1FFF,
652 .flags
= IORESOURCE_MEM
,
655 .start
= MXC_INT_USBHOST
,
656 .end
= MXC_INT_USBHOST
,
657 .flags
= IORESOURCE_IRQ
,
661 struct platform_device mx21_usbhc_device
= {
665 .dma_mask
= &mx21_usbhc_device
.dev
.coherent_dma_mask
,
666 .coherent_dma_mask
= DMA_BIT_MASK(32),
668 .num_resources
= ARRAY_SIZE(mx21_usbhc_resources
),
669 .resource
= mx21_usbhc_resources
,