ARM: mx3: use .init_early to initialize cpu type, reset address and iomuxer
[deliverable/linux.git] / arch / arm / mach-mx3 / mach-mx31lite.c
1 /*
2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/types.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/memory.h>
22 #include <linux/platform_device.h>
23 #include <linux/gpio.h>
24 #include <linux/smsc911x.h>
25 #include <linux/mfd/mc13783.h>
26 #include <linux/spi/spi.h>
27 #include <linux/usb/otg.h>
28 #include <linux/usb/ulpi.h>
29 #include <linux/mtd/physmap.h>
30
31 #include <asm/mach-types.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/time.h>
34 #include <asm/mach/map.h>
35 #include <asm/page.h>
36 #include <asm/setup.h>
37
38 #include <mach/hardware.h>
39 #include <mach/common.h>
40 #include <mach/board-mx31lite.h>
41 #include <mach/iomux-mx3.h>
42 #include <mach/irqs.h>
43 #include <mach/ulpi.h>
44
45 #include "devices-imx31.h"
46 #include "devices.h"
47
48 /*
49 * This file contains the module-specific initialization routines.
50 */
51
52 static unsigned int mx31lite_pins[] = {
53 /* LAN9117 IRQ pin */
54 IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
55 /* SPI 1 */
56 MX31_PIN_CSPI2_SCLK__SCLK,
57 MX31_PIN_CSPI2_MOSI__MOSI,
58 MX31_PIN_CSPI2_MISO__MISO,
59 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
60 MX31_PIN_CSPI2_SS0__SS0,
61 MX31_PIN_CSPI2_SS1__SS1,
62 MX31_PIN_CSPI2_SS2__SS2,
63 };
64
65 static const struct mxc_nand_platform_data
66 mx31lite_nand_board_info __initconst = {
67 .width = 1,
68 .hw_ecc = 1,
69 };
70
71 static struct smsc911x_platform_config smsc911x_config = {
72 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
73 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
74 .flags = SMSC911X_USE_16BIT,
75 };
76
77 static struct resource smsc911x_resources[] = {
78 {
79 .start = MX31_CS4_BASE_ADDR,
80 .end = MX31_CS4_BASE_ADDR + 0x100,
81 .flags = IORESOURCE_MEM,
82 }, {
83 .start = IOMUX_TO_IRQ(MX31_PIN_SFS6),
84 .end = IOMUX_TO_IRQ(MX31_PIN_SFS6),
85 .flags = IORESOURCE_IRQ,
86 },
87 };
88
89 static struct platform_device smsc911x_device = {
90 .name = "smsc911x",
91 .id = -1,
92 .num_resources = ARRAY_SIZE(smsc911x_resources),
93 .resource = smsc911x_resources,
94 .dev = {
95 .platform_data = &smsc911x_config,
96 },
97 };
98
99 /*
100 * SPI
101 *
102 * The MC13783 is the only hard-wired SPI device on the module.
103 */
104
105 static int spi_internal_chipselect[] = {
106 MXC_SPI_CS(0),
107 };
108
109 static const struct spi_imx_master spi1_pdata __initconst = {
110 .chipselect = spi_internal_chipselect,
111 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
112 };
113
114 static struct mc13xxx_platform_data mc13783_pdata __initdata = {
115 .flags = MC13XXX_USE_RTC |
116 MC13XXX_USE_REGULATOR,
117 };
118
119 static struct spi_board_info mc13783_spi_dev __initdata = {
120 .modalias = "mc13783",
121 .max_speed_hz = 1000000,
122 .bus_num = 1,
123 .chip_select = 0,
124 .platform_data = &mc13783_pdata,
125 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
126 };
127
128 /*
129 * USB
130 */
131
132 #if defined(CONFIG_USB_ULPI)
133 #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
134 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
135
136 static int usbh2_init(struct platform_device *pdev)
137 {
138 int pins[] = {
139 MX31_PIN_USBH2_DATA0__USBH2_DATA0,
140 MX31_PIN_USBH2_DATA1__USBH2_DATA1,
141 MX31_PIN_USBH2_CLK__USBH2_CLK,
142 MX31_PIN_USBH2_DIR__USBH2_DIR,
143 MX31_PIN_USBH2_NXT__USBH2_NXT,
144 MX31_PIN_USBH2_STP__USBH2_STP,
145 };
146
147 mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
148
149 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
150 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
151 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
152 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
153 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
154 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
155 mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
156 mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
157 mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
158 mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
159 mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
160 mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
161
162 mxc_iomux_set_gpr(MUX_PGP_UH2, true);
163
164 /* chip select */
165 mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
166 "USBH2_CS");
167 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
168 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
169
170 return 0;
171 }
172
173 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
174 .init = usbh2_init,
175 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
176 .flags = MXC_EHCI_POWER_PINS_ENABLED,
177 };
178 #endif
179
180 /*
181 * NOR flash
182 */
183
184 static struct physmap_flash_data nor_flash_data = {
185 .width = 2,
186 };
187
188 static struct resource nor_flash_resource = {
189 .start = 0xa0000000,
190 .end = 0xa1ffffff,
191 .flags = IORESOURCE_MEM,
192 };
193
194 static struct platform_device physmap_flash_device = {
195 .name = "physmap-flash",
196 .id = 0,
197 .dev = {
198 .platform_data = &nor_flash_data,
199 },
200 .resource = &nor_flash_resource,
201 .num_resources = 1,
202 };
203
204
205
206 /*
207 * This structure defines the MX31 memory map.
208 */
209 static struct map_desc mx31lite_io_desc[] __initdata = {
210 {
211 .virtual = MX31_CS4_BASE_ADDR_VIRT,
212 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
213 .length = MX31_CS4_SIZE,
214 .type = MT_DEVICE
215 }
216 };
217
218 /*
219 * Set up static virtual mappings.
220 */
221 void __init mx31lite_map_io(void)
222 {
223 mx31_map_io();
224 iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
225 }
226
227 static int mx31lite_baseboard;
228 core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
229
230 static void __init mxc_board_init(void)
231 {
232 int ret;
233
234 switch (mx31lite_baseboard) {
235 case MX31LITE_NOBOARD:
236 break;
237 case MX31LITE_DB:
238 mx31lite_db_init();
239 break;
240 default:
241 printk(KERN_ERR "Illegal mx31lite_baseboard type %d\n",
242 mx31lite_baseboard);
243 }
244
245 mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
246 "mx31lite");
247
248 /* NOR and NAND flash */
249 platform_device_register(&physmap_flash_device);
250 imx31_add_mxc_nand(&mx31lite_nand_board_info);
251
252 imx31_add_spi_imx1(&spi1_pdata);
253 spi_register_board_info(&mc13783_spi_dev, 1);
254
255 #if defined(CONFIG_USB_ULPI)
256 /* USB */
257 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
258 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
259
260 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
261 #endif
262
263 /* SMSC9117 IRQ pin */
264 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
265 if (ret)
266 pr_warning("could not get LAN irq gpio\n");
267 else {
268 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
269 platform_device_register(&smsc911x_device);
270 }
271 }
272
273 static void __init mx31lite_timer_init(void)
274 {
275 mx31_clocks_init(26000000);
276 }
277
278 struct sys_timer mx31lite_timer = {
279 .init = mx31lite_timer_init,
280 };
281
282 MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
283 /* Maintainer: Freescale Semiconductor, Inc. */
284 .boot_params = MX3x_PHYS_OFFSET + 0x100,
285 .map_io = mx31lite_map_io,
286 .init_early = imx31_init_early,
287 .init_irq = mx31_init_irq,
288 .timer = &mx31lite_timer,
289 .init_machine = mxc_board_init,
290 MACHINE_END
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