arch/arm/mach-mx5/board-cpuimx51sd.c

   1 /*
   2  *
   3  * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
   4  *
   5  * based on board-mx51_babbage.c which is
   6  * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
   7  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
   8  *
   9  * The code contained herein is licensed under the GNU General Public
  10  * License. You may obtain a copy of the GNU General Public License
  11  * Version 2 or later at the following locations:
  12  *
  13  * http://www.opensource.org/licenses/gpl-license.html
  14  * http://www.gnu.org/copyleft/gpl.html
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/i2c.h>
  20 #include <linux/i2c/tsc2007.h>
  21 #include <linux/gpio.h>
  22 #include <linux/delay.h>
  23 #include <linux/io.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irq.h>
  26 #include <linux/fsl_devices.h>
  27 #include <linux/i2c-gpio.h>
  28 #include <linux/spi/spi.h>
  29 #include <linux/can/platform/mcp251x.h>
  30
  31 #include <mach/eukrea-baseboards.h>
  32 #include <mach/common.h>
  33 #include <mach/hardware.h>
  34 #include <mach/iomux-mx51.h>
  35 #include <mach/mxc_ehci.h>
  36
  37 #include <asm/irq.h>
  38 #include <asm/setup.h>
  39 #include <asm/mach-types.h>
  40 #include <asm/mach/arch.h>
  41 #include <asm/mach/time.h>
  42
  43 #include "devices-imx51.h"
  44 #include "devices.h"
  45
  46 #define USBH1_RST               IMX_GPIO_NR(2, 28)
  47 #define ETH_RST                 IMX_GPIO_NR(2, 31)
  48 #define TSC2007_IRQGPIO         IMX_GPIO_NR(3, 12)
  49 #define CAN_IRQGPIO             IMX_GPIO_NR(1, 1)
  50 #define CAN_RST                 IMX_GPIO_NR(4, 15)
  51 #define CAN_NCS                 IMX_GPIO_NR(4, 24)
  52 #define CAN_RXOBF               IMX_GPIO_NR(1, 4)
  53 #define CAN_RX1BF               IMX_GPIO_NR(1, 6)
  54 #define CAN_TXORTS              IMX_GPIO_NR(1, 7)
  55 #define CAN_TX1RTS              IMX_GPIO_NR(1, 8)
  56 #define CAN_TX2RTS              IMX_GPIO_NR(1, 9)
  57 #define I2C_SCL                 IMX_GPIO_NR(4, 16)
  58 #define I2C_SDA                 IMX_GPIO_NR(4, 17)
  59
  60 /* USB_CTRL_1 */
  61 #define MX51_USB_CTRL_1_OFFSET          0x10
  62 #define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
  63
  64 #define MX51_USB_PLLDIV_12_MHZ          0x00
  65 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
  66 #define MX51_USB_PLL_DIV_24_MHZ         0x02
  67
  68 static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
  69         /* UART1 */
  70         MX51_PAD_UART1_RXD__UART1_RXD,
  71         MX51_PAD_UART1_TXD__UART1_TXD,
  72         MX51_PAD_UART1_RTS__UART1_RTS,
  73         MX51_PAD_UART1_CTS__UART1_CTS,
  74
  75         /* USB HOST1 */
  76         MX51_PAD_USBH1_CLK__USBH1_CLK,
  77         MX51_PAD_USBH1_DIR__USBH1_DIR,
  78         MX51_PAD_USBH1_NXT__USBH1_NXT,
  79         MX51_PAD_USBH1_DATA0__USBH1_DATA0,
  80         MX51_PAD_USBH1_DATA1__USBH1_DATA1,
  81         MX51_PAD_USBH1_DATA2__USBH1_DATA2,
  82         MX51_PAD_USBH1_DATA3__USBH1_DATA3,
  83         MX51_PAD_USBH1_DATA4__USBH1_DATA4,
  84         MX51_PAD_USBH1_DATA5__USBH1_DATA5,
  85         MX51_PAD_USBH1_DATA6__USBH1_DATA6,
  86         MX51_PAD_USBH1_DATA7__USBH1_DATA7,
  87         MX51_PAD_USBH1_STP__USBH1_STP,
  88         MX51_PAD_EIM_CS3__GPIO2_28,             /* PHY nRESET */
  89
  90         /* FEC */
  91         MX51_PAD_EIM_DTACK__GPIO2_31,           /* PHY nRESET */
  92
  93         /* HSI2C */
  94         MX51_PAD_I2C1_CLK__GPIO4_16,
  95         MX51_PAD_I2C1_DAT__GPIO4_17,
  96
  97         /* CAN */
  98         MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
  99         MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
 100         MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
 101         MX51_PAD_CSPI1_SS0__GPIO4_24,           /* nCS */
 102         MX51_PAD_CSI2_PIXCLK__GPIO4_15,         /* nReset */
 103         MX51_PAD_GPIO1_1__GPIO1_1,              /* IRQ */
 104         MX51_PAD_GPIO1_4__GPIO1_4,              /* Control signals */
 105         MX51_PAD_GPIO1_6__GPIO1_6,
 106         MX51_PAD_GPIO1_7__GPIO1_7,
 107         MX51_PAD_GPIO1_8__GPIO1_8,
 108         MX51_PAD_GPIO1_9__GPIO1_9,
 109
 110         /* Touchscreen */
 111         /* IRQ */
 112         _MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
 113                         PAD_CTL_PKE | PAD_CTL_SRE_FAST |
 114                         PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
 115 };
 116
 117 static const struct imxuart_platform_data uart_pdata __initconst = {
 118         .flags = IMXUART_HAVE_RTSCTS,
 119 };
 120
 121 static int ts_get_pendown_state(void)
 122 {
 123         return gpio_get_value(TSC2007_IRQGPIO) ? 0 : 1;
 124 }
 125
 126 static struct tsc2007_platform_data tsc2007_info = {
 127         .model                  = 2007,
 128         .x_plate_ohms           = 180,
 129         .get_pendown_state      = ts_get_pendown_state,
 130 };
 131
 132 static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
 133         {
 134                 I2C_BOARD_INFO("pcf8563", 0x51),
 135         }, {
 136                 I2C_BOARD_INFO("tsc2007", 0x49),
 137                 .type           = "tsc2007",
 138                 .platform_data  = &tsc2007_info,
 139                 .irq            = gpio_to_irq(TSC2007_IRQGPIO),
 140         },
 141 };
 142
 143 static const struct mxc_nand_platform_data
 144                 eukrea_cpuimx51sd_nand_board_info __initconst = {
 145         .width          = 1,
 146         .hw_ecc         = 1,
 147         .flash_bbt      = 1,
 148 };
 149
 150 /* This function is board specific as the bit mask for the plldiv will also
 151 be different for other Freescale SoCs, thus a common bitmask is not
 152 possible and cannot get place in /plat-mxc/ehci.c.*/
 153 static int initialize_otg_port(struct platform_device *pdev)
 154 {
 155         u32 v;
 156         void __iomem *usb_base;
 157         void __iomem *usbother_base;
 158
 159         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
 160         if (!usb_base)
 161                 return -ENOMEM;
 162         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 163
 164         /* Set the PHY clock to 19.2MHz */
 165         v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 166         v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
 167         v |= MX51_USB_PLL_DIV_19_2_MHZ;
 168         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 169         iounmap(usb_base);
 170
 171         mdelay(10);
 172
 173         return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
 174 }
 175
 176 static int initialize_usbh1_port(struct platform_device *pdev)
 177 {
 178         u32 v;
 179         void __iomem *usb_base;
 180         void __iomem *usbother_base;
 181
 182         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
 183         if (!usb_base)
 184                 return -ENOMEM;
 185         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 186
 187         /* The clock for the USBH1 ULPI port will come from the PHY. */
 188         v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
 189         __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
 190                         usbother_base + MX51_USB_CTRL_1_OFFSET);
 191         iounmap(usb_base);
 192
 193         mdelay(10);
 194
 195         return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
 196                         MXC_EHCI_ITC_NO_THRESHOLD);
 197 }
 198
 199 static struct mxc_usbh_platform_data dr_utmi_config = {
 200         .init           = initialize_otg_port,
 201         .portsc = MXC_EHCI_UTMI_16BIT,
 202 };
 203
 204 static struct fsl_usb2_platform_data usb_pdata = {
 205         .operating_mode = FSL_USB2_DR_DEVICE,
 206         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 207 };
 208
 209 static struct mxc_usbh_platform_data usbh1_config = {
 210         .init           = initialize_usbh1_port,
 211         .portsc = MXC_EHCI_MODE_ULPI,
 212 };
 213
 214 static int otg_mode_host;
 215
 216 static int __init eukrea_cpuimx51sd_otg_mode(char *options)
 217 {
 218         if (!strcmp(options, "host"))
 219                 otg_mode_host = 1;
 220         else if (!strcmp(options, "device"))
 221                 otg_mode_host = 0;
 222         else
 223                 pr_info("otg_mode neither \"host\" nor \"device\". "
 224                         "Defaulting to device\n");
 225         return 0;
 226 }
 227 __setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
 228
 229 static struct i2c_gpio_platform_data pdata = {
 230         .sda_pin                = I2C_SDA,
 231         .sda_is_open_drain      = 0,
 232         .scl_pin                = I2C_SCL,
 233         .scl_is_open_drain      = 0,
 234         .udelay                 = 2,
 235 };
 236
 237 static struct platform_device hsi2c_gpio_device = {
 238         .name                   = "i2c-gpio",
 239         .id                     = 0,
 240         .dev.platform_data      = &pdata,
 241 };
 242
 243 static struct mcp251x_platform_data mcp251x_info = {
 244         .oscillator_frequency = 24E6,
 245 };
 246
 247 static struct spi_board_info cpuimx51sd_spi_device[] = {
 248         {
 249                 .modalias        = "mcp2515",
 250                 .max_speed_hz    = 6500000,
 251                 .bus_num         = 0,
 252                 .mode           = SPI_MODE_0,
 253                 .chip_select     = 0,
 254                 .platform_data   = &mcp251x_info,
 255                 .irq             = gpio_to_irq(CAN_IRQGPIO)
 256         },
 257 };
 258
 259 static int cpuimx51sd_spi1_cs[] = {
 260         CAN_NCS,
 261 };
 262
 263 static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
 264         .chipselect     = cpuimx51sd_spi1_cs,
 265         .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
 266 };
 267
 268 static struct platform_device *platform_devices[] __initdata = {
 269         &hsi2c_gpio_device,
 270 };
 271
 272 static void __init eukrea_cpuimx51sd_init(void)
 273 {
 274         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
 275                                         ARRAY_SIZE(eukrea_cpuimx51sd_pads));
 276
 277         imx51_add_imx_uart(0, &uart_pdata);
 278         imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
 279
 280         gpio_request(ETH_RST, "eth_rst");
 281         gpio_set_value(ETH_RST, 1);
 282         imx51_add_fec(NULL);
 283
 284         gpio_request(CAN_IRQGPIO, "can_irq");
 285         gpio_direction_input(CAN_IRQGPIO);
 286         gpio_free(CAN_IRQGPIO);
 287         gpio_request(CAN_NCS, "can_ncs");
 288         gpio_direction_output(CAN_NCS, 1);
 289         gpio_free(CAN_NCS);
 290         gpio_request(CAN_RST, "can_rst");
 291         gpio_direction_output(CAN_RST, 0);
 292         msleep(20);
 293         gpio_set_value(CAN_RST, 1);
 294         imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
 295         spi_register_board_info(cpuimx51sd_spi_device,
 296                                 ARRAY_SIZE(cpuimx51sd_spi_device));
 297
 298         gpio_request(TSC2007_IRQGPIO, "tsc2007_irq");
 299         gpio_direction_input(TSC2007_IRQGPIO);
 300         gpio_free(TSC2007_IRQGPIO);
 301
 302         i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
 303                         ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
 304         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 305
 306         if (otg_mode_host)
 307                 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
 308         else {
 309                 initialize_otg_port(NULL);
 310                 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
 311         }
 312
 313         gpio_request(USBH1_RST, "usb_rst");
 314         gpio_direction_output(USBH1_RST, 0);
 315         msleep(20);
 316         gpio_set_value(USBH1_RST, 1);
 317         mxc_register_device(&mxc_usbh1_device, &usbh1_config);
 318
 319 #ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
 320         eukrea_mbimxsd51_baseboard_init();
 321 #endif
 322 }
 323
 324 static void __init eukrea_cpuimx51sd_timer_init(void)
 325 {
 326         mx51_clocks_init(32768, 24000000, 22579200, 0);
 327 }
 328
 329 static struct sys_timer mxc_timer = {
 330         .init   = eukrea_cpuimx51sd_timer_init,
 331 };
 332
 333 MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
 334         /* Maintainer: Eric Bénard <eric@eukrea.com> */
 335         .boot_params = MX51_PHYS_OFFSET + 0x100,
 336         .map_io = mx51_map_io,
 337         .init_early = imx51_init_early,
 338         .init_irq = mx51_init_irq,
 339         .timer = &mxc_timer,
 340         .init_machine = eukrea_cpuimx51sd_init,
 341 MACHINE_END