mx5: Register i2c on Freescale MX51 Babbage HW
[deliverable/linux.git] / arch / arm / mach-mx5 / board-mx51_babbage.c
1 /*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/i2c.h>
16 #include <linux/gpio.h>
17 #include <linux/delay.h>
18 #include <linux/io.h>
19 #include <linux/fsl_devices.h>
20
21 #include <mach/common.h>
22 #include <mach/hardware.h>
23 #include <mach/imx-uart.h>
24 #include <mach/iomux-mx51.h>
25 #include <mach/i2c.h>
26 #include <mach/mxc_ehci.h>
27
28 #include <asm/irq.h>
29 #include <asm/setup.h>
30 #include <asm/mach-types.h>
31 #include <asm/mach/arch.h>
32 #include <asm/mach/time.h>
33
34 #include "devices.h"
35
36 #define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */
37 #define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */
38 #define BABBAGE_PHY_RESET (1*32 +5) /* GPIO_2_5 */
39
40 /* USB_CTRL_1 */
41 #define MX51_USB_CTRL_1_OFFSET 0x10
42 #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
43
44 #define MX51_USB_PLLDIV_12_MHZ 0x00
45 #define MX51_USB_PLL_DIV_19_2_MHZ 0x01
46 #define MX51_USB_PLL_DIV_24_MHZ 0x02
47
48 static struct platform_device *devices[] __initdata = {
49 &mxc_fec_device,
50 };
51
52 static struct pad_desc mx51babbage_pads[] = {
53 /* UART1 */
54 MX51_PAD_UART1_RXD__UART1_RXD,
55 MX51_PAD_UART1_TXD__UART1_TXD,
56 MX51_PAD_UART1_RTS__UART1_RTS,
57 MX51_PAD_UART1_CTS__UART1_CTS,
58
59 /* UART2 */
60 MX51_PAD_UART2_RXD__UART2_RXD,
61 MX51_PAD_UART2_TXD__UART2_TXD,
62
63 /* UART3 */
64 MX51_PAD_EIM_D25__UART3_RXD,
65 MX51_PAD_EIM_D26__UART3_TXD,
66 MX51_PAD_EIM_D27__UART3_RTS,
67 MX51_PAD_EIM_D24__UART3_CTS,
68
69 /* I2C1 */
70 MX51_PAD_EIM_D16__I2C1_SDA,
71 MX51_PAD_EIM_D19__I2C1_SCL,
72
73 /* I2C2 */
74 MX51_PAD_KEY_COL4__I2C2_SCL,
75 MX51_PAD_KEY_COL5__I2C2_SDA,
76
77 /* HSI2C */
78 MX51_PAD_I2C1_CLK__HSI2C_CLK,
79 MX51_PAD_I2C1_DAT__HSI2C_DAT,
80
81 /* USB HOST1 */
82 MX51_PAD_USBH1_CLK__USBH1_CLK,
83 MX51_PAD_USBH1_DIR__USBH1_DIR,
84 MX51_PAD_USBH1_NXT__USBH1_NXT,
85 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
86 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
87 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
88 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
89 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
90 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
91 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
92 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
93
94 /* USB HUB reset line*/
95 MX51_PAD_GPIO_1_7__GPIO1_7,
96 };
97
98 /* Serial ports */
99 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
100 static struct imxuart_platform_data uart_pdata = {
101 .flags = IMXUART_HAVE_RTSCTS,
102 };
103
104 static inline void mxc_init_imx_uart(void)
105 {
106 mxc_register_device(&mxc_uart_device0, &uart_pdata);
107 mxc_register_device(&mxc_uart_device1, &uart_pdata);
108 mxc_register_device(&mxc_uart_device2, &uart_pdata);
109 }
110 #else /* !SERIAL_IMX */
111 static inline void mxc_init_imx_uart(void)
112 {
113 }
114 #endif /* SERIAL_IMX */
115
116 static struct imxi2c_platform_data babbage_i2c_data = {
117 .bitrate = 100000,
118 };
119
120 static struct imxi2c_platform_data babbage_hsi2c_data = {
121 .bitrate = 400000,
122 };
123
124 static int gpio_usbh1_active(void)
125 {
126 struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27;
127 struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5;
128 int ret;
129
130 /* Set USBH1_STP to GPIO and toggle it */
131 mxc_iomux_v3_setup_pad(&usbh1stp_gpio);
132 ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp");
133
134 if (ret) {
135 pr_debug("failed to get MX51_PAD_USBH1_STP__GPIO_1_27: %d\n", ret);
136 return ret;
137 }
138 gpio_direction_output(BABBAGE_USBH1_STP, 0);
139 gpio_set_value(BABBAGE_USBH1_STP, 1);
140 msleep(100);
141 gpio_free(BABBAGE_USBH1_STP);
142
143 /* De-assert USB PHY RESETB */
144 mxc_iomux_v3_setup_pad(&phyreset_gpio);
145 ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset");
146
147 if (ret) {
148 pr_debug("failed to get MX51_PAD_EIM_D21__GPIO_2_5: %d\n", ret);
149 return ret;
150 }
151 gpio_direction_output(BABBAGE_PHY_RESET, 1);
152 return 0;
153 }
154
155 static inline void babbage_usbhub_reset(void)
156 {
157 int ret;
158
159 /* Bring USB hub out of reset */
160 ret = gpio_request(BABBAGE_USB_HUB_RESET, "GPIO1_7");
161 if (ret) {
162 printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
163 return;
164 }
165 gpio_direction_output(BABBAGE_USB_HUB_RESET, 0);
166
167 /* USB HUB RESET - De-assert USB HUB RESET_N */
168 msleep(1);
169 gpio_set_value(BABBAGE_USB_HUB_RESET, 0);
170 msleep(1);
171 gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
172 }
173
174 /* This function is board specific as the bit mask for the plldiv will also
175 be different for other Freescale SoCs, thus a common bitmask is not
176 possible and cannot get place in /plat-mxc/ehci.c.*/
177 static int initialize_otg_port(struct platform_device *pdev)
178 {
179 u32 v;
180 void __iomem *usb_base;
181 u32 usbother_base;
182
183 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
184 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
185
186 /* Set the PHY clock to 19.2MHz */
187 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
188 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
189 v |= MX51_USB_PLL_DIV_19_2_MHZ;
190 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
191 iounmap(usb_base);
192 return 0;
193 }
194
195 static int initialize_usbh1_port(struct platform_device *pdev)
196 {
197 u32 v;
198 void __iomem *usb_base;
199 u32 usbother_base;
200
201 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
202 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
203
204 /* The clock for the USBH1 ULPI port will come externally from the PHY. */
205 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
206 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
207 iounmap(usb_base);
208 return 0;
209 }
210
211 static struct mxc_usbh_platform_data dr_utmi_config = {
212 .init = initialize_otg_port,
213 .portsc = MXC_EHCI_UTMI_16BIT,
214 .flags = MXC_EHCI_INTERNAL_PHY,
215 };
216
217 static struct fsl_usb2_platform_data usb_pdata = {
218 .operating_mode = FSL_USB2_DR_DEVICE,
219 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
220 };
221
222 static struct mxc_usbh_platform_data usbh1_config = {
223 .init = initialize_usbh1_port,
224 .portsc = MXC_EHCI_MODE_ULPI,
225 .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
226 };
227
228 static int otg_mode_host;
229
230 static int __init babbage_otg_mode(char *options)
231 {
232 if (!strcmp(options, "host"))
233 otg_mode_host = 1;
234 else if (!strcmp(options, "device"))
235 otg_mode_host = 0;
236 else
237 pr_info("otg_mode neither \"host\" nor \"device\". "
238 "Defaulting to device\n");
239 return 0;
240 }
241 __setup("otg_mode=", babbage_otg_mode);
242
243 /*
244 * Board specific initialization.
245 */
246 static void __init mxc_board_init(void)
247 {
248 struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
249
250 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
251 ARRAY_SIZE(mx51babbage_pads));
252 mxc_init_imx_uart();
253 platform_add_devices(devices, ARRAY_SIZE(devices));
254
255 mxc_register_device(&mxc_i2c_device0, &babbage_i2c_data);
256 mxc_register_device(&mxc_i2c_device1, &babbage_i2c_data);
257 mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
258
259 if (otg_mode_host)
260 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
261 else {
262 initialize_otg_port(NULL);
263 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
264 }
265
266 gpio_usbh1_active();
267 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
268 /* setback USBH1_STP to be function */
269 mxc_iomux_v3_setup_pad(&usbh1stp);
270 babbage_usbhub_reset();
271 }
272
273 static void __init mx51_babbage_timer_init(void)
274 {
275 mx51_clocks_init(32768, 24000000, 22579200, 0);
276 }
277
278 static struct sys_timer mxc_timer = {
279 .init = mx51_babbage_timer_init,
280 };
281
282 MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
283 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
284 .phys_io = MX51_AIPS1_BASE_ADDR,
285 .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
286 .boot_params = PHYS_OFFSET + 0x100,
287 .map_io = mx51_map_io,
288 .init_irq = mx51_init_irq,
289 .init_machine = mxc_board_init,
290 .timer = &mxc_timer,
291 MACHINE_END
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