arch/arm/mach-mxs/timer.c

   1 /*
   2  *  Copyright (C) 2000-2001 Deep Blue Solutions
   3  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   4  *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
   5  *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
   6  *  Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  20  * MA 02110-1301, USA.
  21  */
  22
  23 #include <linux/err.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irq.h>
  26 #include <linux/clockchips.h>
  27 #include <linux/clk.h>
  28 #include <linux/of.h>
  29 #include <linux/of_irq.h>
  30
  31 #include <asm/mach/time.h>
  32 #include <mach/mxs.h>
  33 #include <mach/common.h>
  34
  35 /*
  36  * There are 2 versions of the timrot on Freescale MXS-based SoCs.
  37  * The v1 on MX23 only gets 16 bits counter, while v2 on MX28
  38  * extends the counter to 32 bits.
  39  *
  40  * The implementation uses two timers, one for clock_event and
  41  * another for clocksource. MX28 uses timrot 0 and 1, while MX23
  42  * uses 0 and 2.
  43  */
  44
  45 #define MX23_TIMROT_VERSION_OFFSET      0x0a0
  46 #define MX28_TIMROT_VERSION_OFFSET      0x120
  47 #define BP_TIMROT_MAJOR_VERSION         24
  48 #define BV_TIMROT_VERSION_1             0x01
  49 #define BV_TIMROT_VERSION_2             0x02
  50 #define timrot_is_v1()  (timrot_major_version == BV_TIMROT_VERSION_1)
  51
  52 /*
  53  * There are 4 registers for each timrotv2 instance, and 2 registers
  54  * for each timrotv1. So address step 0x40 in macros below strides
  55  * one instance of timrotv2 while two instances of timrotv1.
  56  *
  57  * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
  58  * on MX28 while timrot2 on MX23.
  59  */
  60 /* common between v1 and v2 */
  61 #define HW_TIMROT_ROTCTRL               0x00
  62 #define HW_TIMROT_TIMCTRLn(n)           (0x20 + (n) * 0x40)
  63 /* v1 only */
  64 #define HW_TIMROT_TIMCOUNTn(n)          (0x30 + (n) * 0x40)
  65 /* v2 only */
  66 #define HW_TIMROT_RUNNING_COUNTn(n)     (0x30 + (n) * 0x40)
  67 #define HW_TIMROT_FIXED_COUNTn(n)       (0x40 + (n) * 0x40)
  68
  69 #define BM_TIMROT_TIMCTRLn_RELOAD       (1 << 6)
  70 #define BM_TIMROT_TIMCTRLn_UPDATE       (1 << 7)
  71 #define BM_TIMROT_TIMCTRLn_IRQ_EN       (1 << 14)
  72 #define BM_TIMROT_TIMCTRLn_IRQ          (1 << 15)
  73 #define BP_TIMROT_TIMCTRLn_SELECT       0
  74 #define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
  75 #define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
  76
  77 static struct clock_event_device mxs_clockevent_device;
  78 static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;
  79
  80 static void __iomem *mxs_timrot_base = MXS_IO_ADDRESS(MXS_TIMROT_BASE_ADDR);
  81 static u32 timrot_major_version;
  82
  83 static inline void timrot_irq_disable(void)
  84 {
  85         __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN,
  86                         mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
  87 }
  88
  89 static inline void timrot_irq_enable(void)
  90 {
  91         __mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN,
  92                         mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
  93 }
  94
  95 static void timrot_irq_acknowledge(void)
  96 {
  97         __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ,
  98                         mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
  99 }
 100
 101 static cycle_t timrotv1_get_cycles(struct clocksource *cs)
 102 {
 103         return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
 104                         & 0xffff0000) >> 16);
 105 }
 106
 107 static int timrotv1_set_next_event(unsigned long evt,
 108                                         struct clock_event_device *dev)
 109 {
 110         /* timrot decrements the count */
 111         __raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));
 112
 113         return 0;
 114 }
 115
 116 static int timrotv2_set_next_event(unsigned long evt,
 117                                         struct clock_event_device *dev)
 118 {
 119         /* timrot decrements the count */
 120         __raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));
 121
 122         return 0;
 123 }
 124
 125 static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
 126 {
 127         struct clock_event_device *evt = dev_id;
 128
 129         timrot_irq_acknowledge();
 130         evt->event_handler(evt);
 131
 132         return IRQ_HANDLED;
 133 }
 134
 135 static struct irqaction mxs_timer_irq = {
 136         .name           = "MXS Timer Tick",
 137         .dev_id         = &mxs_clockevent_device,
 138         .flags          = IRQF_TIMER | IRQF_IRQPOLL,
 139         .handler        = mxs_timer_interrupt,
 140 };
 141
 142 #ifdef DEBUG
 143 static const char *clock_event_mode_label[] const = {
 144         [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
 145         [CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
 146         [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
 147         [CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED"
 148 };
 149 #endif /* DEBUG */
 150
 151 static void mxs_set_mode(enum clock_event_mode mode,
 152                                 struct clock_event_device *evt)
 153 {
 154         /* Disable interrupt in timer module */
 155         timrot_irq_disable();
 156
 157         if (mode != mxs_clockevent_mode) {
 158                 /* Set event time into the furthest future */
 159                 if (timrot_is_v1())
 160                         __raw_writel(0xffff,
 161                                 mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
 162                 else
 163                         __raw_writel(0xffffffff,
 164                                 mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
 165
 166                 /* Clear pending interrupt */
 167                 timrot_irq_acknowledge();
 168         }
 169
 170 #ifdef DEBUG
 171         pr_info("%s: changing mode from %s to %s\n", __func__,
 172                 clock_event_mode_label[mxs_clockevent_mode],
 173                 clock_event_mode_label[mode]);
 174 #endif /* DEBUG */
 175
 176         /* Remember timer mode */
 177         mxs_clockevent_mode = mode;
 178
 179         switch (mode) {
 180         case CLOCK_EVT_MODE_PERIODIC:
 181                 pr_err("%s: Periodic mode is not implemented\n", __func__);
 182                 break;
 183         case CLOCK_EVT_MODE_ONESHOT:
 184                 timrot_irq_enable();
 185                 break;
 186         case CLOCK_EVT_MODE_SHUTDOWN:
 187         case CLOCK_EVT_MODE_UNUSED:
 188         case CLOCK_EVT_MODE_RESUME:
 189                 /* Left event sources disabled, no more interrupts appear */
 190                 break;
 191         }
 192 }
 193
 194 static struct clock_event_device mxs_clockevent_device = {
 195         .name           = "mxs_timrot",
 196         .features       = CLOCK_EVT_FEAT_ONESHOT,
 197         .shift          = 32,
 198         .set_mode       = mxs_set_mode,
 199         .set_next_event = timrotv2_set_next_event,
 200         .rating         = 200,
 201 };
 202
 203 static int __init mxs_clockevent_init(struct clk *timer_clk)
 204 {
 205         unsigned int c = clk_get_rate(timer_clk);
 206
 207         mxs_clockevent_device.mult =
 208                 div_sc(c, NSEC_PER_SEC, mxs_clockevent_device.shift);
 209         mxs_clockevent_device.cpumask = cpumask_of(0);
 210         if (timrot_is_v1()) {
 211                 mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
 212                 mxs_clockevent_device.max_delta_ns =
 213                         clockevent_delta2ns(0xfffe, &mxs_clockevent_device);
 214                 mxs_clockevent_device.min_delta_ns =
 215                         clockevent_delta2ns(0xf, &mxs_clockevent_device);
 216         } else {
 217                 mxs_clockevent_device.max_delta_ns =
 218                         clockevent_delta2ns(0xfffffffe, &mxs_clockevent_device);
 219                 mxs_clockevent_device.min_delta_ns =
 220                         clockevent_delta2ns(0xf, &mxs_clockevent_device);
 221         }
 222
 223         clockevents_register_device(&mxs_clockevent_device);
 224
 225         return 0;
 226 }
 227
 228 static struct clocksource clocksource_mxs = {
 229         .name           = "mxs_timer",
 230         .rating         = 200,
 231         .read           = timrotv1_get_cycles,
 232         .mask           = CLOCKSOURCE_MASK(16),
 233         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 234 };
 235
 236 static int __init mxs_clocksource_init(struct clk *timer_clk)
 237 {
 238         unsigned int c = clk_get_rate(timer_clk);
 239
 240         if (timrot_is_v1())
 241                 clocksource_register_hz(&clocksource_mxs, c);
 242         else
 243                 clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
 244                         "mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
 245
 246         return 0;
 247 }
 248
 249 void __init mxs_timer_init(void)
 250 {
 251         struct device_node *np;
 252         struct clk *timer_clk;
 253         int irq;
 254
 255         np = of_find_compatible_node(NULL, NULL, "fsl,timrot");
 256         if (!np) {
 257                 pr_err("%s: failed find timrot node\n", __func__);
 258                 return;
 259         }
 260
 261         timer_clk = clk_get_sys("timrot", NULL);
 262         if (IS_ERR(timer_clk)) {
 263                 pr_err("%s: failed to get clk\n", __func__);
 264                 return;
 265         }
 266
 267         clk_prepare_enable(timer_clk);
 268
 269         /*
 270          * Initialize timers to a known state
 271          */
 272         mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
 273
 274         /* get timrot version */
 275         timrot_major_version = __raw_readl(mxs_timrot_base +
 276                                 (cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET :
 277                                                 MX28_TIMROT_VERSION_OFFSET));
 278         timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
 279
 280         /* one for clock_event */
 281         __raw_writel((timrot_is_v1() ?
 282                         BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
 283                         BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
 284                         BM_TIMROT_TIMCTRLn_UPDATE |
 285                         BM_TIMROT_TIMCTRLn_IRQ_EN,
 286                         mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
 287
 288         /* another for clocksource */
 289         __raw_writel((timrot_is_v1() ?
 290                         BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
 291                         BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
 292                         BM_TIMROT_TIMCTRLn_RELOAD,
 293                         mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
 294
 295         /* set clocksource timer fixed count to the maximum */
 296         if (timrot_is_v1())
 297                 __raw_writel(0xffff,
 298                         mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
 299         else
 300                 __raw_writel(0xffffffff,
 301                         mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
 302
 303         /* init and register the timer to the framework */
 304         mxs_clocksource_init(timer_clk);
 305         mxs_clockevent_init(timer_clk);
 306
 307         /* Make irqs happen */
 308         irq = irq_of_parse_and_map(np, 0);
 309         setup_irq(irq, &mxs_timer_irq);
 310 }