2 * linux/arch/arm/mach-omap1/clock_data.c
4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * - Clocks that are only available on some chips should be marked with the
14 * chips that they are present on.
17 #include <linux/kernel.h>
19 #include <linux/clk.h>
20 #include <linux/cpufreq.h>
21 #include <linux/delay.h>
23 #include <asm/mach-types.h> /* for machine_is_* */
27 #include <mach/hardware.h>
28 #include <mach/usb.h> /* for OTG_BASE */
30 #include "../plat-omap/sram.h"
35 /* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
36 #define IDL_CLKOUT_ARM_SHIFT 12
37 #define IDLTIM_ARM_SHIFT 9
38 #define IDLAPI_ARM_SHIFT 8
39 #define IDLIF_ARM_SHIFT 6
40 #define IDLLB_ARM_SHIFT 4 /* undocumented? */
41 #define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */
42 #define IDLPER_ARM_SHIFT 2
43 #define IDLXORP_ARM_SHIFT 1
44 #define IDLWDT_ARM_SHIFT 0
46 /* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
47 #define CONF_MOD_UART3_CLK_MODE_R 31
48 #define CONF_MOD_UART2_CLK_MODE_R 30
49 #define CONF_MOD_UART1_CLK_MODE_R 29
50 #define CONF_MOD_MMC_SD_CLK_REQ_R 23
51 #define CONF_MOD_MCBSP3_AUXON 20
53 /* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
54 #define CONF_MOD_SOSSI_CLK_EN_R 16
56 /* Some OTG_SYSCON_2-specific bit fields */
57 #define OTG_SYSCON_2_UHOST_EN_SHIFT 8
59 /* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
60 #define SOFT_MMC2_DPLL_REQ_SHIFT 13
61 #define SOFT_MMC_DPLL_REQ_SHIFT 12
62 #define SOFT_UART3_DPLL_REQ_SHIFT 11
63 #define SOFT_UART2_DPLL_REQ_SHIFT 10
64 #define SOFT_UART1_DPLL_REQ_SHIFT 9
65 #define SOFT_USB_OTG_DPLL_REQ_SHIFT 8
66 #define SOFT_CAM_DPLL_REQ_SHIFT 7
67 #define SOFT_COM_MCKO_REQ_SHIFT 6
68 #define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */
69 #define USB_REQ_EN_SHIFT 4
70 #define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */
71 #define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */
72 #define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */
73 #define SOFT_DPLL_REQ_SHIFT 0
79 static struct clk ck_ref
= {
85 static struct clk ck_dpll1
= {
92 * FIXME: This clock seems to be necessary but no-one has asked for its
93 * activation. [ FIX: SoSSI, SSR ]
95 static struct arm_idlect1_clk ck_dpll1out
= {
97 .name
= "ck_dpll1out",
98 .ops
= &clkops_generic
,
100 .flags
= CLOCK_IDLE_CONTROL
| ENABLE_REG_32BIT
|
102 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
103 .enable_bit
= EN_CKOUT_ARM
,
104 .recalc
= &followparent_recalc
,
106 .idlect_shift
= IDL_CLKOUT_ARM_SHIFT
,
109 static struct clk sossi_ck
= {
111 .ops
= &clkops_generic
,
112 .parent
= &ck_dpll1out
.clk
,
113 .flags
= CLOCK_NO_IDLE_PARENT
| ENABLE_REG_32BIT
,
114 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1
),
115 .enable_bit
= CONF_MOD_SOSSI_CLK_EN_R
,
116 .recalc
= &omap1_sossi_recalc
,
117 .set_rate
= &omap1_set_sossi_rate
,
120 static struct clk arm_ck
= {
124 .rate_offset
= CKCTL_ARMDIV_OFFSET
,
125 .recalc
= &omap1_ckctl_recalc
,
126 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
127 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
130 static struct arm_idlect1_clk armper_ck
= {
133 .ops
= &clkops_generic
,
135 .flags
= CLOCK_IDLE_CONTROL
,
136 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
137 .enable_bit
= EN_PERCK
,
138 .rate_offset
= CKCTL_PERDIV_OFFSET
,
139 .recalc
= &omap1_ckctl_recalc
,
140 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
141 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
143 .idlect_shift
= IDLPER_ARM_SHIFT
,
147 * FIXME: This clock seems to be necessary but no-one has asked for its
148 * activation. [ GPIO code for 1510 ]
150 static struct clk arm_gpio_ck
= {
152 .ops
= &clkops_generic
,
154 .flags
= ENABLE_ON_INIT
,
155 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
156 .enable_bit
= EN_GPIOCK
,
157 .recalc
= &followparent_recalc
,
160 static struct arm_idlect1_clk armxor_ck
= {
163 .ops
= &clkops_generic
,
165 .flags
= CLOCK_IDLE_CONTROL
,
166 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
167 .enable_bit
= EN_XORPCK
,
168 .recalc
= &followparent_recalc
,
170 .idlect_shift
= IDLXORP_ARM_SHIFT
,
173 static struct arm_idlect1_clk armtim_ck
= {
176 .ops
= &clkops_generic
,
178 .flags
= CLOCK_IDLE_CONTROL
,
179 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
180 .enable_bit
= EN_TIMCK
,
181 .recalc
= &followparent_recalc
,
183 .idlect_shift
= IDLTIM_ARM_SHIFT
,
186 static struct arm_idlect1_clk armwdt_ck
= {
189 .ops
= &clkops_generic
,
191 .flags
= CLOCK_IDLE_CONTROL
,
192 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
193 .enable_bit
= EN_WDTCK
,
195 .recalc
= &omap_fixed_divisor_recalc
,
197 .idlect_shift
= IDLWDT_ARM_SHIFT
,
200 static struct clk arminth_ck16xx
= {
201 .name
= "arminth_ck",
204 .recalc
= &followparent_recalc
,
205 /* Note: On 16xx the frequency can be divided by 2 by programming
206 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
208 * 1510 version is in TC clocks.
212 static struct clk dsp_ck
= {
214 .ops
= &clkops_generic
,
216 .enable_reg
= OMAP1_IO_ADDRESS(ARM_CKCTL
),
217 .enable_bit
= EN_DSPCK
,
218 .rate_offset
= CKCTL_DSPDIV_OFFSET
,
219 .recalc
= &omap1_ckctl_recalc
,
220 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
221 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
224 static struct clk dspmmu_ck
= {
228 .rate_offset
= CKCTL_DSPMMUDIV_OFFSET
,
229 .recalc
= &omap1_ckctl_recalc
,
230 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
231 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
234 static struct clk dspper_ck
= {
236 .ops
= &clkops_dspck
,
238 .enable_reg
= DSP_IDLECT2
,
239 .enable_bit
= EN_PERCK
,
240 .rate_offset
= CKCTL_PERDIV_OFFSET
,
241 .recalc
= &omap1_ckctl_recalc_dsp_domain
,
242 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
243 .set_rate
= &omap1_clk_set_rate_dsp_domain
,
246 static struct clk dspxor_ck
= {
248 .ops
= &clkops_dspck
,
250 .enable_reg
= DSP_IDLECT2
,
251 .enable_bit
= EN_XORPCK
,
252 .recalc
= &followparent_recalc
,
255 static struct clk dsptim_ck
= {
257 .ops
= &clkops_dspck
,
259 .enable_reg
= DSP_IDLECT2
,
260 .enable_bit
= EN_DSPTIMCK
,
261 .recalc
= &followparent_recalc
,
264 static struct arm_idlect1_clk tc_ck
= {
269 .flags
= CLOCK_IDLE_CONTROL
,
270 .rate_offset
= CKCTL_TCDIV_OFFSET
,
271 .recalc
= &omap1_ckctl_recalc
,
272 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
273 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
275 .idlect_shift
= IDLIF_ARM_SHIFT
,
278 static struct clk arminth_ck1510
= {
279 .name
= "arminth_ck",
281 .parent
= &tc_ck
.clk
,
282 .recalc
= &followparent_recalc
,
283 /* Note: On 1510 the frequency follows TC_CK
285 * 16xx version is in MPU clocks.
289 static struct clk tipb_ck
= {
290 /* No-idle controlled by "tc_ck" */
293 .parent
= &tc_ck
.clk
,
294 .recalc
= &followparent_recalc
,
297 static struct clk l3_ocpi_ck
= {
298 /* No-idle controlled by "tc_ck" */
299 .name
= "l3_ocpi_ck",
300 .ops
= &clkops_generic
,
301 .parent
= &tc_ck
.clk
,
302 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT3
),
303 .enable_bit
= EN_OCPI_CK
,
304 .recalc
= &followparent_recalc
,
307 static struct clk tc1_ck
= {
309 .ops
= &clkops_generic
,
310 .parent
= &tc_ck
.clk
,
311 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT3
),
312 .enable_bit
= EN_TC1_CK
,
313 .recalc
= &followparent_recalc
,
317 * FIXME: This clock seems to be necessary but no-one has asked for its
318 * activation. [ pm.c (SRAM), CCP, Camera ]
320 static struct clk tc2_ck
= {
322 .ops
= &clkops_generic
,
323 .parent
= &tc_ck
.clk
,
324 .flags
= ENABLE_ON_INIT
,
325 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT3
),
326 .enable_bit
= EN_TC2_CK
,
327 .recalc
= &followparent_recalc
,
330 static struct clk dma_ck
= {
331 /* No-idle controlled by "tc_ck" */
334 .parent
= &tc_ck
.clk
,
335 .recalc
= &followparent_recalc
,
338 static struct clk dma_lcdfree_ck
= {
339 .name
= "dma_lcdfree_ck",
341 .parent
= &tc_ck
.clk
,
342 .recalc
= &followparent_recalc
,
345 static struct arm_idlect1_clk api_ck
= {
348 .ops
= &clkops_generic
,
349 .parent
= &tc_ck
.clk
,
350 .flags
= CLOCK_IDLE_CONTROL
,
351 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
352 .enable_bit
= EN_APICK
,
353 .recalc
= &followparent_recalc
,
355 .idlect_shift
= IDLAPI_ARM_SHIFT
,
358 static struct arm_idlect1_clk lb_ck
= {
361 .ops
= &clkops_generic
,
362 .parent
= &tc_ck
.clk
,
363 .flags
= CLOCK_IDLE_CONTROL
,
364 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
365 .enable_bit
= EN_LBCK
,
366 .recalc
= &followparent_recalc
,
368 .idlect_shift
= IDLLB_ARM_SHIFT
,
371 static struct clk rhea1_ck
= {
374 .parent
= &tc_ck
.clk
,
375 .recalc
= &followparent_recalc
,
378 static struct clk rhea2_ck
= {
381 .parent
= &tc_ck
.clk
,
382 .recalc
= &followparent_recalc
,
385 static struct clk lcd_ck_16xx
= {
387 .ops
= &clkops_generic
,
389 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
390 .enable_bit
= EN_LCDCK
,
391 .rate_offset
= CKCTL_LCDDIV_OFFSET
,
392 .recalc
= &omap1_ckctl_recalc
,
393 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
394 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
397 static struct arm_idlect1_clk lcd_ck_1510
= {
400 .ops
= &clkops_generic
,
402 .flags
= CLOCK_IDLE_CONTROL
,
403 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
404 .enable_bit
= EN_LCDCK
,
405 .rate_offset
= CKCTL_LCDDIV_OFFSET
,
406 .recalc
= &omap1_ckctl_recalc
,
407 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
408 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
410 .idlect_shift
= OMAP1510_IDLLCD_ARM_SHIFT
,
414 * XXX The enable_bit here is misused - it simply switches between 12MHz
415 * and 48MHz. Reimplement with clksel.
417 * XXX does this need SYSC register handling?
419 static struct clk uart1_1510
= {
422 /* Direct from ULPD, no real parent */
423 .parent
= &armper_ck
.clk
,
425 .flags
= ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
426 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
427 .enable_bit
= CONF_MOD_UART1_CLK_MODE_R
,
428 .set_rate
= &omap1_set_uart_rate
,
429 .recalc
= &omap1_uart_recalc
,
433 * XXX The enable_bit here is misused - it simply switches between 12MHz
434 * and 48MHz. Reimplement with clksel.
436 * XXX SYSC register handling does not belong in the clock framework
438 static struct uart_clk uart1_16xx
= {
441 .ops
= &clkops_uart_16xx
,
442 /* Direct from ULPD, no real parent */
443 .parent
= &armper_ck
.clk
,
445 .flags
= ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
446 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
447 .enable_bit
= CONF_MOD_UART1_CLK_MODE_R
,
449 .sysc_addr
= 0xfffb0054,
453 * XXX The enable_bit here is misused - it simply switches between 12MHz
454 * and 48MHz. Reimplement with clksel.
456 * XXX does this need SYSC register handling?
458 static struct clk uart2_ck
= {
461 /* Direct from ULPD, no real parent */
462 .parent
= &armper_ck
.clk
,
464 .flags
= ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
465 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
466 .enable_bit
= CONF_MOD_UART2_CLK_MODE_R
,
467 .set_rate
= &omap1_set_uart_rate
,
468 .recalc
= &omap1_uart_recalc
,
472 * XXX The enable_bit here is misused - it simply switches between 12MHz
473 * and 48MHz. Reimplement with clksel.
475 * XXX does this need SYSC register handling?
477 static struct clk uart3_1510
= {
480 /* Direct from ULPD, no real parent */
481 .parent
= &armper_ck
.clk
,
483 .flags
= ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
484 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
485 .enable_bit
= CONF_MOD_UART3_CLK_MODE_R
,
486 .set_rate
= &omap1_set_uart_rate
,
487 .recalc
= &omap1_uart_recalc
,
491 * XXX The enable_bit here is misused - it simply switches between 12MHz
492 * and 48MHz. Reimplement with clksel.
494 * XXX SYSC register handling does not belong in the clock framework
496 static struct uart_clk uart3_16xx
= {
499 .ops
= &clkops_uart_16xx
,
500 /* Direct from ULPD, no real parent */
501 .parent
= &armper_ck
.clk
,
503 .flags
= ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
504 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
505 .enable_bit
= CONF_MOD_UART3_CLK_MODE_R
,
507 .sysc_addr
= 0xfffb9854,
510 static struct clk usb_clko
= { /* 6 MHz output on W4_USB_CLKO */
512 .ops
= &clkops_generic
,
513 /* Direct from ULPD, no parent */
515 .flags
= ENABLE_REG_32BIT
,
516 .enable_reg
= OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL
),
517 .enable_bit
= USB_MCLK_EN_BIT
,
520 static struct clk usb_hhc_ck1510
= {
521 .name
= "usb_hhc_ck",
522 .ops
= &clkops_generic
,
523 /* Direct from ULPD, no parent */
524 .rate
= 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
525 .flags
= ENABLE_REG_32BIT
,
526 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
527 .enable_bit
= USB_HOST_HHC_UHOST_EN
,
530 static struct clk usb_hhc_ck16xx
= {
531 .name
= "usb_hhc_ck",
532 .ops
= &clkops_generic
,
533 /* Direct from ULPD, no parent */
535 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
536 .flags
= ENABLE_REG_32BIT
,
537 .enable_reg
= OMAP1_IO_ADDRESS(OTG_BASE
+ 0x08), /* OTG_SYSCON_2 */
538 .enable_bit
= OTG_SYSCON_2_UHOST_EN_SHIFT
541 static struct clk usb_dc_ck
= {
543 .ops
= &clkops_generic
,
544 /* Direct from ULPD, no parent */
546 .enable_reg
= OMAP1_IO_ADDRESS(SOFT_REQ_REG
),
547 .enable_bit
= USB_REQ_EN_SHIFT
,
550 static struct clk usb_dc_ck7xx
= {
552 .ops
= &clkops_generic
,
553 /* Direct from ULPD, no parent */
555 .enable_reg
= OMAP1_IO_ADDRESS(SOFT_REQ_REG
),
556 .enable_bit
= SOFT_USB_OTG_DPLL_REQ_SHIFT
,
559 static struct clk uart1_7xx
= {
561 .ops
= &clkops_generic
,
562 /* Direct from ULPD, no parent */
564 .enable_reg
= OMAP1_IO_ADDRESS(SOFT_REQ_REG
),
568 static struct clk uart2_7xx
= {
570 .ops
= &clkops_generic
,
571 /* Direct from ULPD, no parent */
573 .enable_reg
= OMAP1_IO_ADDRESS(SOFT_REQ_REG
),
577 static struct clk mclk_1510
= {
579 .ops
= &clkops_generic
,
580 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
582 .enable_reg
= OMAP1_IO_ADDRESS(SOFT_REQ_REG
),
583 .enable_bit
= SOFT_COM_MCKO_REQ_SHIFT
,
586 static struct clk mclk_16xx
= {
588 .ops
= &clkops_generic
,
589 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
590 .enable_reg
= OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL
),
591 .enable_bit
= COM_ULPD_PLL_CLK_REQ
,
592 .set_rate
= &omap1_set_ext_clk_rate
,
593 .round_rate
= &omap1_round_ext_clk_rate
,
594 .init
= &omap1_init_ext_clk
,
597 static struct clk bclk_1510
= {
599 .ops
= &clkops_generic
,
600 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
604 static struct clk bclk_16xx
= {
606 .ops
= &clkops_generic
,
607 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
608 .enable_reg
= OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL
),
609 .enable_bit
= SWD_ULPD_PLL_CLK_REQ
,
610 .set_rate
= &omap1_set_ext_clk_rate
,
611 .round_rate
= &omap1_round_ext_clk_rate
,
612 .init
= &omap1_init_ext_clk
,
615 static struct clk mmc1_ck
= {
617 .ops
= &clkops_generic
,
618 /* Functional clock is direct from ULPD, interface clock is ARMPER */
619 .parent
= &armper_ck
.clk
,
621 .flags
= ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
622 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
623 .enable_bit
= CONF_MOD_MMC_SD_CLK_REQ_R
,
627 * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
628 * CONF_MOD_MCBSP3_AUXON ??
630 static struct clk mmc2_ck
= {
632 .ops
= &clkops_generic
,
633 /* Functional clock is direct from ULPD, interface clock is ARMPER */
634 .parent
= &armper_ck
.clk
,
636 .flags
= ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
637 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
641 static struct clk mmc3_ck
= {
643 .ops
= &clkops_generic
,
644 /* Functional clock is direct from ULPD, interface clock is ARMPER */
645 .parent
= &armper_ck
.clk
,
647 .flags
= ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
648 .enable_reg
= OMAP1_IO_ADDRESS(SOFT_REQ_REG
),
649 .enable_bit
= SOFT_MMC_DPLL_REQ_SHIFT
,
652 static struct clk virtual_ck_mpu
= {
655 .parent
= &arm_ck
, /* Is smarter alias for */
656 .recalc
= &followparent_recalc
,
657 .set_rate
= &omap1_select_table_rate
,
658 .round_rate
= &omap1_round_to_table_rate
,
661 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
662 remains active during MPU idle whenever this is enabled */
663 static struct clk i2c_fck
= {
666 .flags
= CLOCK_NO_IDLE_PARENT
,
667 .parent
= &armxor_ck
.clk
,
668 .recalc
= &followparent_recalc
,
671 static struct clk i2c_ick
= {
674 .flags
= CLOCK_NO_IDLE_PARENT
,
675 .parent
= &armper_ck
.clk
,
676 .recalc
= &followparent_recalc
,
683 static struct omap_clk omap_clks
[] = {
684 /* non-ULPD clocks */
685 CLK(NULL
, "ck_ref", &ck_ref
, CK_16XX
| CK_1510
| CK_310
| CK_7XX
),
686 CLK(NULL
, "ck_dpll1", &ck_dpll1
, CK_16XX
| CK_1510
| CK_310
| CK_7XX
),
688 CLK(NULL
, "ck_dpll1out", &ck_dpll1out
.clk
, CK_16XX
),
689 CLK(NULL
, "ck_sossi", &sossi_ck
, CK_16XX
),
690 CLK(NULL
, "arm_ck", &arm_ck
, CK_16XX
| CK_1510
| CK_310
),
691 CLK(NULL
, "armper_ck", &armper_ck
.clk
, CK_16XX
| CK_1510
| CK_310
),
692 CLK("omap_gpio.0", "ick", &arm_gpio_ck
, CK_1510
| CK_310
),
693 CLK(NULL
, "armxor_ck", &armxor_ck
.clk
, CK_16XX
| CK_1510
| CK_310
| CK_7XX
),
694 CLK(NULL
, "armtim_ck", &armtim_ck
.clk
, CK_16XX
| CK_1510
| CK_310
),
695 CLK("omap_wdt", "fck", &armwdt_ck
.clk
, CK_16XX
| CK_1510
| CK_310
),
696 CLK("omap_wdt", "ick", &armper_ck
.clk
, CK_16XX
),
697 CLK("omap_wdt", "ick", &dummy_ck
, CK_1510
| CK_310
),
698 CLK(NULL
, "arminth_ck", &arminth_ck1510
, CK_1510
| CK_310
),
699 CLK(NULL
, "arminth_ck", &arminth_ck16xx
, CK_16XX
),
701 CLK(NULL
, "dsp_ck", &dsp_ck
, CK_16XX
| CK_1510
| CK_310
),
702 CLK(NULL
, "dspmmu_ck", &dspmmu_ck
, CK_16XX
| CK_1510
| CK_310
),
703 CLK(NULL
, "dspper_ck", &dspper_ck
, CK_16XX
| CK_1510
| CK_310
),
704 CLK(NULL
, "dspxor_ck", &dspxor_ck
, CK_16XX
| CK_1510
| CK_310
),
705 CLK(NULL
, "dsptim_ck", &dsptim_ck
, CK_16XX
| CK_1510
| CK_310
),
707 CLK(NULL
, "tc_ck", &tc_ck
.clk
, CK_16XX
| CK_1510
| CK_310
| CK_7XX
),
708 CLK(NULL
, "tipb_ck", &tipb_ck
, CK_1510
| CK_310
),
709 CLK(NULL
, "l3_ocpi_ck", &l3_ocpi_ck
, CK_16XX
| CK_7XX
),
710 CLK(NULL
, "tc1_ck", &tc1_ck
, CK_16XX
),
711 CLK(NULL
, "tc2_ck", &tc2_ck
, CK_16XX
),
712 CLK(NULL
, "dma_ck", &dma_ck
, CK_16XX
| CK_1510
| CK_310
),
713 CLK(NULL
, "dma_lcdfree_ck", &dma_lcdfree_ck
, CK_16XX
),
714 CLK(NULL
, "api_ck", &api_ck
.clk
, CK_16XX
| CK_1510
| CK_310
| CK_7XX
),
715 CLK(NULL
, "lb_ck", &lb_ck
.clk
, CK_1510
| CK_310
),
716 CLK(NULL
, "rhea1_ck", &rhea1_ck
, CK_16XX
),
717 CLK(NULL
, "rhea2_ck", &rhea2_ck
, CK_16XX
),
718 CLK(NULL
, "lcd_ck", &lcd_ck_16xx
, CK_16XX
| CK_7XX
),
719 CLK(NULL
, "lcd_ck", &lcd_ck_1510
.clk
, CK_1510
| CK_310
),
721 CLK(NULL
, "uart1_ck", &uart1_1510
, CK_1510
| CK_310
),
722 CLK(NULL
, "uart1_ck", &uart1_16xx
.clk
, CK_16XX
),
723 CLK(NULL
, "uart1_ck", &uart1_7xx
, CK_7XX
),
724 CLK(NULL
, "uart2_ck", &uart2_ck
, CK_16XX
| CK_1510
| CK_310
),
725 CLK(NULL
, "uart2_ck", &uart2_7xx
, CK_7XX
),
726 CLK(NULL
, "uart3_ck", &uart3_1510
, CK_1510
| CK_310
),
727 CLK(NULL
, "uart3_ck", &uart3_16xx
.clk
, CK_16XX
),
728 CLK(NULL
, "usb_clko", &usb_clko
, CK_16XX
| CK_1510
| CK_310
),
729 CLK(NULL
, "usb_hhc_ck", &usb_hhc_ck1510
, CK_1510
| CK_310
),
730 CLK(NULL
, "usb_hhc_ck", &usb_hhc_ck16xx
, CK_16XX
),
731 CLK(NULL
, "usb_dc_ck", &usb_dc_ck
, CK_16XX
),
732 CLK(NULL
, "usb_dc_ck", &usb_dc_ck7xx
, CK_7XX
),
733 CLK(NULL
, "mclk", &mclk_1510
, CK_1510
| CK_310
),
734 CLK(NULL
, "mclk", &mclk_16xx
, CK_16XX
),
735 CLK(NULL
, "bclk", &bclk_1510
, CK_1510
| CK_310
),
736 CLK(NULL
, "bclk", &bclk_16xx
, CK_16XX
),
737 CLK("mmci-omap.0", "fck", &mmc1_ck
, CK_16XX
| CK_1510
| CK_310
),
738 CLK("mmci-omap.0", "fck", &mmc3_ck
, CK_7XX
),
739 CLK("mmci-omap.0", "ick", &armper_ck
.clk
, CK_16XX
| CK_1510
| CK_310
| CK_7XX
),
740 CLK("mmci-omap.1", "fck", &mmc2_ck
, CK_16XX
),
741 CLK("mmci-omap.1", "ick", &armper_ck
.clk
, CK_16XX
),
743 CLK(NULL
, "mpu", &virtual_ck_mpu
, CK_16XX
| CK_1510
| CK_310
),
744 CLK("omap_i2c.1", "fck", &i2c_fck
, CK_16XX
| CK_1510
| CK_310
| CK_7XX
),
745 CLK("omap_i2c.1", "ick", &i2c_ick
, CK_16XX
),
746 CLK("omap_i2c.1", "ick", &dummy_ck
, CK_1510
| CK_310
| CK_7XX
),
747 CLK("omap1_spi100k.1", "fck", &dummy_ck
, CK_7XX
),
748 CLK("omap1_spi100k.1", "ick", &dummy_ck
, CK_7XX
),
749 CLK("omap1_spi100k.2", "fck", &dummy_ck
, CK_7XX
),
750 CLK("omap1_spi100k.2", "ick", &dummy_ck
, CK_7XX
),
751 CLK("omap_uwire", "fck", &armxor_ck
.clk
, CK_16XX
| CK_1510
| CK_310
),
752 CLK("omap-mcbsp.1", "ick", &dspper_ck
, CK_16XX
),
753 CLK("omap-mcbsp.1", "ick", &dummy_ck
, CK_1510
| CK_310
),
754 CLK("omap-mcbsp.2", "ick", &armper_ck
.clk
, CK_16XX
),
755 CLK("omap-mcbsp.2", "ick", &dummy_ck
, CK_1510
| CK_310
),
756 CLK("omap-mcbsp.3", "ick", &dspper_ck
, CK_16XX
),
757 CLK("omap-mcbsp.3", "ick", &dummy_ck
, CK_1510
| CK_310
),
758 CLK("omap-mcbsp.1", "fck", &dspxor_ck
, CK_16XX
| CK_1510
| CK_310
),
759 CLK("omap-mcbsp.2", "fck", &armper_ck
.clk
, CK_16XX
| CK_1510
| CK_310
),
760 CLK("omap-mcbsp.3", "fck", &dspxor_ck
, CK_16XX
| CK_1510
| CK_310
),
767 static void __init
omap1_show_rates(void)
769 pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
770 ck_ref
.rate
/ 1000000, (ck_ref
.rate
/ 100000) % 10,
771 ck_dpll1
.rate
/ 1000000, (ck_dpll1
.rate
/ 100000) % 10,
772 arm_ck
.rate
/ 1000000, (arm_ck
.rate
/ 100000) % 10);
777 int __init
omap1_clk_init(void)
780 int crystal_type
= 0; /* Default 12 MHz */
783 #ifdef CONFIG_DEBUG_LL
785 * Resets some clocks that may be left on from bootloader,
786 * but leaves serial clocks on.
788 omap_writel(0x3 << 29, MOD_CONF_CTRL_0
);
791 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
792 reg
= omap_readw(SOFT_REQ_REG
) & (1 << 4);
793 omap_writew(reg
, SOFT_REQ_REG
);
794 if (!cpu_is_omap15xx())
795 omap_writew(0, SOFT_REQ_REG2
);
797 /* By default all idlect1 clocks are allowed to idle */
798 arm_idlect1_mask
= ~0;
800 for (c
= omap_clks
; c
< omap_clks
+ ARRAY_SIZE(omap_clks
); c
++)
801 clk_preinit(c
->lk
.clk
);
804 if (cpu_is_omap1710())
806 if (cpu_is_omap16xx())
808 if (cpu_is_omap1510())
810 if (cpu_is_omap7xx())
812 if (cpu_is_omap310())
815 for (c
= omap_clks
; c
< omap_clks
+ ARRAY_SIZE(omap_clks
); c
++)
816 if (c
->cpu
& cpu_mask
) {
818 clk_register(c
->lk
.clk
);
821 /* Pointers to these clocks are needed by code in clock.c */
822 api_ck_p
= clk_get(NULL
, "api_ck");
823 ck_dpll1_p
= clk_get(NULL
, "ck_dpll1");
824 ck_ref_p
= clk_get(NULL
, "ck_ref");
826 if (cpu_is_omap7xx())
827 ck_ref
.rate
= 13000000;
828 if (cpu_is_omap16xx() && crystal_type
== 2)
829 ck_ref
.rate
= 19200000;
831 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
832 omap_readw(ARM_SYSST
), omap_readw(DPLL_CTL
),
833 omap_readw(ARM_CKCTL
));
835 /* We want to be in syncronous scalable mode */
836 omap_writew(0x1000, ARM_SYSST
);
840 * Initially use the values set by bootloader. Determine PLL rate and
841 * recalculate dependent clocks as if kernel had changed PLL or
842 * divisors. See also omap1_clk_late_init() that can reprogram dpll1
843 * after the SRAM is initialized.
846 unsigned pll_ctl_val
= omap_readw(DPLL_CTL
);
848 ck_dpll1
.rate
= ck_ref
.rate
; /* Base xtal rate */
849 if (pll_ctl_val
& 0x10) {
850 /* PLL enabled, apply multiplier and divisor */
851 if (pll_ctl_val
& 0xf80)
852 ck_dpll1
.rate
*= (pll_ctl_val
& 0xf80) >> 7;
853 ck_dpll1
.rate
/= ((pll_ctl_val
& 0x60) >> 5) + 1;
855 /* PLL disabled, apply bypass divisor */
856 switch (pll_ctl_val
& 0xc) {
868 propagate_rate(&ck_dpll1
);
869 /* Cache rates for clocks connected to ck_ref (not dpll1) */
870 propagate_rate(&ck_ref
);
872 if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
873 /* Select slicer output as OMAP input clock */
874 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL
) & ~0x1,
875 OMAP7XX_PCC_UPLD_CTRL
);
878 /* Amstrad Delta wants BCLK high when inactive */
879 if (machine_is_ams_delta())
880 omap_writel(omap_readl(ULPD_CLOCK_CTRL
) |
881 (1 << SDW_MCLK_INV_BIT
),
884 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
885 /* (on 730, bit 13 must not be cleared) */
886 if (cpu_is_omap7xx())
887 omap_writew(omap_readw(ARM_CKCTL
) & 0x2fff, ARM_CKCTL
);
889 omap_writew(omap_readw(ARM_CKCTL
) & 0x0fff, ARM_CKCTL
);
891 /* Put DSP/MPUI into reset until needed */
892 omap_writew(0, ARM_RSTCT1
);
893 omap_writew(1, ARM_RSTCT2
);
894 omap_writew(0x400, ARM_IDLECT1
);
897 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
898 * of the ARM_IDLECT2 register must be set to zero. The power-on
899 * default value of this bit is one.
901 omap_writew(0x0000, ARM_IDLECT2
); /* Turn LCD clock off also */
904 * Only enable those clocks we will need, let the drivers
905 * enable other clocks as necessary
907 clk_enable(&armper_ck
.clk
);
908 clk_enable(&armxor_ck
.clk
);
909 clk_enable(&armtim_ck
.clk
); /* This should be done by timer code */
911 if (cpu_is_omap15xx())
912 clk_enable(&arm_gpio_ck
);
917 #define OMAP1_DPLL1_SANE_VALUE 60000000
919 void __init
omap1_clk_late_init(void)
921 unsigned long rate
= ck_dpll1
.rate
;
923 /* Find the highest supported frequency and enable it */
924 if (omap1_select_table_rate(&virtual_ck_mpu
, ~0)) {
925 pr_err("System frequencies not set, using default. Check your config.\n");
927 * Reprogramming the DPLL is tricky, it must be done from SRAM.
929 omap_sram_reprogram_clock(0x2290, 0x0005);
930 ck_dpll1
.rate
= OMAP1_DPLL1_SANE_VALUE
;
932 propagate_rate(&ck_dpll1
);
934 loops_per_jiffy
= cpufreq_scale(loops_per_jiffy
, rate
, ck_dpll1
.rate
);