2 * linux/arch/arm/mach-omap1/clock_data.c
4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * - Clocks that are only available on some chips should be marked with the
14 * chips that they are present on.
17 #include <linux/kernel.h>
19 #include <linux/clk.h>
20 #include <linux/cpufreq.h>
21 #include <linux/delay.h>
23 #include <asm/mach-types.h> /* for machine_is_* */
25 #include <plat/clock.h>
27 #include <plat/clkdev_omap.h>
28 #include <plat/sram.h> /* for omap_sram_reprogram_clock() */
30 #include <mach/hardware.h>
31 #include <mach/usb.h> /* for OTG_BASE */
36 /* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
37 #define IDL_CLKOUT_ARM_SHIFT 12
38 #define IDLTIM_ARM_SHIFT 9
39 #define IDLAPI_ARM_SHIFT 8
40 #define IDLIF_ARM_SHIFT 6
41 #define IDLLB_ARM_SHIFT 4 /* undocumented? */
42 #define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */
43 #define IDLPER_ARM_SHIFT 2
44 #define IDLXORP_ARM_SHIFT 1
45 #define IDLWDT_ARM_SHIFT 0
47 /* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
48 #define CONF_MOD_UART3_CLK_MODE_R 31
49 #define CONF_MOD_UART2_CLK_MODE_R 30
50 #define CONF_MOD_UART1_CLK_MODE_R 29
51 #define CONF_MOD_MMC_SD_CLK_REQ_R 23
52 #define CONF_MOD_MCBSP3_AUXON 20
54 /* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
55 #define CONF_MOD_SOSSI_CLK_EN_R 16
57 /* Some OTG_SYSCON_2-specific bit fields */
58 #define OTG_SYSCON_2_UHOST_EN_SHIFT 8
60 /* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
61 #define SOFT_MMC2_DPLL_REQ_SHIFT 13
62 #define SOFT_MMC_DPLL_REQ_SHIFT 12
63 #define SOFT_UART3_DPLL_REQ_SHIFT 11
64 #define SOFT_UART2_DPLL_REQ_SHIFT 10
65 #define SOFT_UART1_DPLL_REQ_SHIFT 9
66 #define SOFT_USB_OTG_DPLL_REQ_SHIFT 8
67 #define SOFT_CAM_DPLL_REQ_SHIFT 7
68 #define SOFT_COM_MCKO_REQ_SHIFT 6
69 #define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */
70 #define USB_REQ_EN_SHIFT 4
71 #define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */
72 #define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */
73 #define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */
74 #define SOFT_DPLL_REQ_SHIFT 0
80 static struct clk ck_ref
= {
86 static struct clk ck_dpll1
= {
93 * FIXME: This clock seems to be necessary but no-one has asked for its
94 * activation. [ FIX: SoSSI, SSR ]
96 static struct arm_idlect1_clk ck_dpll1out
= {
98 .name
= "ck_dpll1out",
99 .ops
= &clkops_generic
,
101 .flags
= CLOCK_IDLE_CONTROL
| ENABLE_REG_32BIT
|
103 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
104 .enable_bit
= EN_CKOUT_ARM
,
105 .recalc
= &followparent_recalc
,
107 .idlect_shift
= IDL_CLKOUT_ARM_SHIFT
,
110 static struct clk sossi_ck
= {
112 .ops
= &clkops_generic
,
113 .parent
= &ck_dpll1out
.clk
,
114 .flags
= CLOCK_NO_IDLE_PARENT
| ENABLE_REG_32BIT
,
115 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1
),
116 .enable_bit
= CONF_MOD_SOSSI_CLK_EN_R
,
117 .recalc
= &omap1_sossi_recalc
,
118 .set_rate
= &omap1_set_sossi_rate
,
121 static struct clk arm_ck
= {
125 .rate_offset
= CKCTL_ARMDIV_OFFSET
,
126 .recalc
= &omap1_ckctl_recalc
,
127 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
128 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
131 static struct arm_idlect1_clk armper_ck
= {
134 .ops
= &clkops_generic
,
136 .flags
= CLOCK_IDLE_CONTROL
,
137 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
138 .enable_bit
= EN_PERCK
,
139 .rate_offset
= CKCTL_PERDIV_OFFSET
,
140 .recalc
= &omap1_ckctl_recalc
,
141 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
142 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
144 .idlect_shift
= IDLPER_ARM_SHIFT
,
148 * FIXME: This clock seems to be necessary but no-one has asked for its
149 * activation. [ GPIO code for 1510 ]
151 static struct clk arm_gpio_ck
= {
153 .ops
= &clkops_generic
,
155 .flags
= ENABLE_ON_INIT
,
156 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
157 .enable_bit
= EN_GPIOCK
,
158 .recalc
= &followparent_recalc
,
161 static struct arm_idlect1_clk armxor_ck
= {
164 .ops
= &clkops_generic
,
166 .flags
= CLOCK_IDLE_CONTROL
,
167 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
168 .enable_bit
= EN_XORPCK
,
169 .recalc
= &followparent_recalc
,
171 .idlect_shift
= IDLXORP_ARM_SHIFT
,
174 static struct arm_idlect1_clk armtim_ck
= {
177 .ops
= &clkops_generic
,
179 .flags
= CLOCK_IDLE_CONTROL
,
180 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
181 .enable_bit
= EN_TIMCK
,
182 .recalc
= &followparent_recalc
,
184 .idlect_shift
= IDLTIM_ARM_SHIFT
,
187 static struct arm_idlect1_clk armwdt_ck
= {
190 .ops
= &clkops_generic
,
192 .flags
= CLOCK_IDLE_CONTROL
,
193 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
194 .enable_bit
= EN_WDTCK
,
196 .recalc
= &omap_fixed_divisor_recalc
,
198 .idlect_shift
= IDLWDT_ARM_SHIFT
,
201 static struct clk arminth_ck16xx
= {
202 .name
= "arminth_ck",
205 .recalc
= &followparent_recalc
,
206 /* Note: On 16xx the frequency can be divided by 2 by programming
207 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
209 * 1510 version is in TC clocks.
213 static struct clk dsp_ck
= {
215 .ops
= &clkops_generic
,
217 .enable_reg
= OMAP1_IO_ADDRESS(ARM_CKCTL
),
218 .enable_bit
= EN_DSPCK
,
219 .rate_offset
= CKCTL_DSPDIV_OFFSET
,
220 .recalc
= &omap1_ckctl_recalc
,
221 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
222 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
225 static struct clk dspmmu_ck
= {
229 .rate_offset
= CKCTL_DSPMMUDIV_OFFSET
,
230 .recalc
= &omap1_ckctl_recalc
,
231 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
232 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
235 static struct clk dspper_ck
= {
237 .ops
= &clkops_dspck
,
239 .enable_reg
= DSP_IDLECT2
,
240 .enable_bit
= EN_PERCK
,
241 .rate_offset
= CKCTL_PERDIV_OFFSET
,
242 .recalc
= &omap1_ckctl_recalc_dsp_domain
,
243 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
244 .set_rate
= &omap1_clk_set_rate_dsp_domain
,
247 static struct clk dspxor_ck
= {
249 .ops
= &clkops_dspck
,
251 .enable_reg
= DSP_IDLECT2
,
252 .enable_bit
= EN_XORPCK
,
253 .recalc
= &followparent_recalc
,
256 static struct clk dsptim_ck
= {
258 .ops
= &clkops_dspck
,
260 .enable_reg
= DSP_IDLECT2
,
261 .enable_bit
= EN_DSPTIMCK
,
262 .recalc
= &followparent_recalc
,
265 static struct arm_idlect1_clk tc_ck
= {
270 .flags
= CLOCK_IDLE_CONTROL
,
271 .rate_offset
= CKCTL_TCDIV_OFFSET
,
272 .recalc
= &omap1_ckctl_recalc
,
273 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
274 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
276 .idlect_shift
= IDLIF_ARM_SHIFT
,
279 static struct clk arminth_ck1510
= {
280 .name
= "arminth_ck",
282 .parent
= &tc_ck
.clk
,
283 .recalc
= &followparent_recalc
,
284 /* Note: On 1510 the frequency follows TC_CK
286 * 16xx version is in MPU clocks.
290 static struct clk tipb_ck
= {
291 /* No-idle controlled by "tc_ck" */
294 .parent
= &tc_ck
.clk
,
295 .recalc
= &followparent_recalc
,
298 static struct clk l3_ocpi_ck
= {
299 /* No-idle controlled by "tc_ck" */
300 .name
= "l3_ocpi_ck",
301 .ops
= &clkops_generic
,
302 .parent
= &tc_ck
.clk
,
303 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT3
),
304 .enable_bit
= EN_OCPI_CK
,
305 .recalc
= &followparent_recalc
,
308 static struct clk tc1_ck
= {
310 .ops
= &clkops_generic
,
311 .parent
= &tc_ck
.clk
,
312 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT3
),
313 .enable_bit
= EN_TC1_CK
,
314 .recalc
= &followparent_recalc
,
318 * FIXME: This clock seems to be necessary but no-one has asked for its
319 * activation. [ pm.c (SRAM), CCP, Camera ]
321 static struct clk tc2_ck
= {
323 .ops
= &clkops_generic
,
324 .parent
= &tc_ck
.clk
,
325 .flags
= ENABLE_ON_INIT
,
326 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT3
),
327 .enable_bit
= EN_TC2_CK
,
328 .recalc
= &followparent_recalc
,
331 static struct clk dma_ck
= {
332 /* No-idle controlled by "tc_ck" */
335 .parent
= &tc_ck
.clk
,
336 .recalc
= &followparent_recalc
,
339 static struct clk dma_lcdfree_ck
= {
340 .name
= "dma_lcdfree_ck",
342 .parent
= &tc_ck
.clk
,
343 .recalc
= &followparent_recalc
,
346 static struct arm_idlect1_clk api_ck
= {
349 .ops
= &clkops_generic
,
350 .parent
= &tc_ck
.clk
,
351 .flags
= CLOCK_IDLE_CONTROL
,
352 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
353 .enable_bit
= EN_APICK
,
354 .recalc
= &followparent_recalc
,
356 .idlect_shift
= IDLAPI_ARM_SHIFT
,
359 static struct arm_idlect1_clk lb_ck
= {
362 .ops
= &clkops_generic
,
363 .parent
= &tc_ck
.clk
,
364 .flags
= CLOCK_IDLE_CONTROL
,
365 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
366 .enable_bit
= EN_LBCK
,
367 .recalc
= &followparent_recalc
,
369 .idlect_shift
= IDLLB_ARM_SHIFT
,
372 static struct clk rhea1_ck
= {
375 .parent
= &tc_ck
.clk
,
376 .recalc
= &followparent_recalc
,
379 static struct clk rhea2_ck
= {
382 .parent
= &tc_ck
.clk
,
383 .recalc
= &followparent_recalc
,
386 static struct clk lcd_ck_16xx
= {
388 .ops
= &clkops_generic
,
390 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
391 .enable_bit
= EN_LCDCK
,
392 .rate_offset
= CKCTL_LCDDIV_OFFSET
,
393 .recalc
= &omap1_ckctl_recalc
,
394 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
395 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
398 static struct arm_idlect1_clk lcd_ck_1510
= {
401 .ops
= &clkops_generic
,
403 .flags
= CLOCK_IDLE_CONTROL
,
404 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
405 .enable_bit
= EN_LCDCK
,
406 .rate_offset
= CKCTL_LCDDIV_OFFSET
,
407 .recalc
= &omap1_ckctl_recalc
,
408 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
409 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
411 .idlect_shift
= OMAP1510_IDLLCD_ARM_SHIFT
,
415 * XXX The enable_bit here is misused - it simply switches between 12MHz
416 * and 48MHz. Reimplement with clksel.
418 * XXX does this need SYSC register handling?
420 static struct clk uart1_1510
= {
423 /* Direct from ULPD, no real parent */
424 .parent
= &armper_ck
.clk
,
426 .flags
= ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
427 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
428 .enable_bit
= CONF_MOD_UART1_CLK_MODE_R
,
429 .set_rate
= &omap1_set_uart_rate
,
430 .recalc
= &omap1_uart_recalc
,
434 * XXX The enable_bit here is misused - it simply switches between 12MHz
435 * and 48MHz. Reimplement with clksel.
437 * XXX SYSC register handling does not belong in the clock framework
439 static struct uart_clk uart1_16xx
= {
442 .ops
= &clkops_uart_16xx
,
443 /* Direct from ULPD, no real parent */
444 .parent
= &armper_ck
.clk
,
446 .flags
= ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
447 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
448 .enable_bit
= CONF_MOD_UART1_CLK_MODE_R
,
450 .sysc_addr
= 0xfffb0054,
454 * XXX The enable_bit here is misused - it simply switches between 12MHz
455 * and 48MHz. Reimplement with clksel.
457 * XXX does this need SYSC register handling?
459 static struct clk uart2_ck
= {
462 /* Direct from ULPD, no real parent */
463 .parent
= &armper_ck
.clk
,
465 .flags
= ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
466 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
467 .enable_bit
= CONF_MOD_UART2_CLK_MODE_R
,
468 .set_rate
= &omap1_set_uart_rate
,
469 .recalc
= &omap1_uart_recalc
,
473 * XXX The enable_bit here is misused - it simply switches between 12MHz
474 * and 48MHz. Reimplement with clksel.
476 * XXX does this need SYSC register handling?
478 static struct clk uart3_1510
= {
481 /* Direct from ULPD, no real parent */
482 .parent
= &armper_ck
.clk
,
484 .flags
= ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
485 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
486 .enable_bit
= CONF_MOD_UART3_CLK_MODE_R
,
487 .set_rate
= &omap1_set_uart_rate
,
488 .recalc
= &omap1_uart_recalc
,
492 * XXX The enable_bit here is misused - it simply switches between 12MHz
493 * and 48MHz. Reimplement with clksel.
495 * XXX SYSC register handling does not belong in the clock framework
497 static struct uart_clk uart3_16xx
= {
500 .ops
= &clkops_uart_16xx
,
501 /* Direct from ULPD, no real parent */
502 .parent
= &armper_ck
.clk
,
504 .flags
= ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
505 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
506 .enable_bit
= CONF_MOD_UART3_CLK_MODE_R
,
508 .sysc_addr
= 0xfffb9854,
511 static struct clk usb_clko
= { /* 6 MHz output on W4_USB_CLKO */
513 .ops
= &clkops_generic
,
514 /* Direct from ULPD, no parent */
516 .flags
= ENABLE_REG_32BIT
,
517 .enable_reg
= OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL
),
518 .enable_bit
= USB_MCLK_EN_BIT
,
521 static struct clk usb_hhc_ck1510
= {
522 .name
= "usb_hhc_ck",
523 .ops
= &clkops_generic
,
524 /* Direct from ULPD, no parent */
525 .rate
= 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
526 .flags
= ENABLE_REG_32BIT
,
527 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
528 .enable_bit
= USB_HOST_HHC_UHOST_EN
,
531 static struct clk usb_hhc_ck16xx
= {
532 .name
= "usb_hhc_ck",
533 .ops
= &clkops_generic
,
534 /* Direct from ULPD, no parent */
536 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
537 .flags
= ENABLE_REG_32BIT
,
538 .enable_reg
= OMAP1_IO_ADDRESS(OTG_BASE
+ 0x08), /* OTG_SYSCON_2 */
539 .enable_bit
= OTG_SYSCON_2_UHOST_EN_SHIFT
542 static struct clk usb_dc_ck
= {
544 .ops
= &clkops_generic
,
545 /* Direct from ULPD, no parent */
547 .enable_reg
= OMAP1_IO_ADDRESS(SOFT_REQ_REG
),
548 .enable_bit
= USB_REQ_EN_SHIFT
,
551 static struct clk usb_dc_ck7xx
= {
553 .ops
= &clkops_generic
,
554 /* Direct from ULPD, no parent */
556 .enable_reg
= OMAP1_IO_ADDRESS(SOFT_REQ_REG
),
557 .enable_bit
= SOFT_USB_OTG_DPLL_REQ_SHIFT
,
560 static struct clk uart1_7xx
= {
562 .ops
= &clkops_generic
,
563 /* Direct from ULPD, no parent */
565 .enable_reg
= OMAP1_IO_ADDRESS(SOFT_REQ_REG
),
569 static struct clk uart2_7xx
= {
571 .ops
= &clkops_generic
,
572 /* Direct from ULPD, no parent */
574 .enable_reg
= OMAP1_IO_ADDRESS(SOFT_REQ_REG
),
578 static struct clk mclk_1510
= {
580 .ops
= &clkops_generic
,
581 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
583 .enable_reg
= OMAP1_IO_ADDRESS(SOFT_REQ_REG
),
584 .enable_bit
= SOFT_COM_MCKO_REQ_SHIFT
,
587 static struct clk mclk_16xx
= {
589 .ops
= &clkops_generic
,
590 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
591 .enable_reg
= OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL
),
592 .enable_bit
= COM_ULPD_PLL_CLK_REQ
,
593 .set_rate
= &omap1_set_ext_clk_rate
,
594 .round_rate
= &omap1_round_ext_clk_rate
,
595 .init
= &omap1_init_ext_clk
,
598 static struct clk bclk_1510
= {
600 .ops
= &clkops_generic
,
601 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
605 static struct clk bclk_16xx
= {
607 .ops
= &clkops_generic
,
608 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
609 .enable_reg
= OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL
),
610 .enable_bit
= SWD_ULPD_PLL_CLK_REQ
,
611 .set_rate
= &omap1_set_ext_clk_rate
,
612 .round_rate
= &omap1_round_ext_clk_rate
,
613 .init
= &omap1_init_ext_clk
,
616 static struct clk mmc1_ck
= {
618 .ops
= &clkops_generic
,
619 /* Functional clock is direct from ULPD, interface clock is ARMPER */
620 .parent
= &armper_ck
.clk
,
622 .flags
= ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
623 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
624 .enable_bit
= CONF_MOD_MMC_SD_CLK_REQ_R
,
628 * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
629 * CONF_MOD_MCBSP3_AUXON ??
631 static struct clk mmc2_ck
= {
633 .ops
= &clkops_generic
,
634 /* Functional clock is direct from ULPD, interface clock is ARMPER */
635 .parent
= &armper_ck
.clk
,
637 .flags
= ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
638 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
642 static struct clk mmc3_ck
= {
644 .ops
= &clkops_generic
,
645 /* Functional clock is direct from ULPD, interface clock is ARMPER */
646 .parent
= &armper_ck
.clk
,
648 .flags
= ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
649 .enable_reg
= OMAP1_IO_ADDRESS(SOFT_REQ_REG
),
650 .enable_bit
= SOFT_MMC_DPLL_REQ_SHIFT
,
653 static struct clk virtual_ck_mpu
= {
656 .parent
= &arm_ck
, /* Is smarter alias for */
657 .recalc
= &followparent_recalc
,
658 .set_rate
= &omap1_select_table_rate
,
659 .round_rate
= &omap1_round_to_table_rate
,
662 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
663 remains active during MPU idle whenever this is enabled */
664 static struct clk i2c_fck
= {
667 .flags
= CLOCK_NO_IDLE_PARENT
,
668 .parent
= &armxor_ck
.clk
,
669 .recalc
= &followparent_recalc
,
672 static struct clk i2c_ick
= {
675 .flags
= CLOCK_NO_IDLE_PARENT
,
676 .parent
= &armper_ck
.clk
,
677 .recalc
= &followparent_recalc
,
684 static struct omap_clk omap_clks
[] = {
685 /* non-ULPD clocks */
686 CLK(NULL
, "ck_ref", &ck_ref
, CK_16XX
| CK_1510
| CK_310
| CK_7XX
),
687 CLK(NULL
, "ck_dpll1", &ck_dpll1
, CK_16XX
| CK_1510
| CK_310
| CK_7XX
),
689 CLK(NULL
, "ck_dpll1out", &ck_dpll1out
.clk
, CK_16XX
),
690 CLK(NULL
, "ck_sossi", &sossi_ck
, CK_16XX
),
691 CLK(NULL
, "arm_ck", &arm_ck
, CK_16XX
| CK_1510
| CK_310
),
692 CLK(NULL
, "armper_ck", &armper_ck
.clk
, CK_16XX
| CK_1510
| CK_310
),
693 CLK("omap_gpio.0", "ick", &arm_gpio_ck
, CK_1510
| CK_310
),
694 CLK(NULL
, "armxor_ck", &armxor_ck
.clk
, CK_16XX
| CK_1510
| CK_310
| CK_7XX
),
695 CLK(NULL
, "armtim_ck", &armtim_ck
.clk
, CK_16XX
| CK_1510
| CK_310
),
696 CLK("omap_wdt", "fck", &armwdt_ck
.clk
, CK_16XX
| CK_1510
| CK_310
),
697 CLK("omap_wdt", "ick", &armper_ck
.clk
, CK_16XX
),
698 CLK("omap_wdt", "ick", &dummy_ck
, CK_1510
| CK_310
),
699 CLK(NULL
, "arminth_ck", &arminth_ck1510
, CK_1510
| CK_310
),
700 CLK(NULL
, "arminth_ck", &arminth_ck16xx
, CK_16XX
),
702 CLK(NULL
, "dsp_ck", &dsp_ck
, CK_16XX
| CK_1510
| CK_310
),
703 CLK(NULL
, "dspmmu_ck", &dspmmu_ck
, CK_16XX
| CK_1510
| CK_310
),
704 CLK(NULL
, "dspper_ck", &dspper_ck
, CK_16XX
| CK_1510
| CK_310
),
705 CLK(NULL
, "dspxor_ck", &dspxor_ck
, CK_16XX
| CK_1510
| CK_310
),
706 CLK(NULL
, "dsptim_ck", &dsptim_ck
, CK_16XX
| CK_1510
| CK_310
),
708 CLK(NULL
, "tc_ck", &tc_ck
.clk
, CK_16XX
| CK_1510
| CK_310
| CK_7XX
),
709 CLK(NULL
, "tipb_ck", &tipb_ck
, CK_1510
| CK_310
),
710 CLK(NULL
, "l3_ocpi_ck", &l3_ocpi_ck
, CK_16XX
| CK_7XX
),
711 CLK(NULL
, "tc1_ck", &tc1_ck
, CK_16XX
),
712 CLK(NULL
, "tc2_ck", &tc2_ck
, CK_16XX
),
713 CLK(NULL
, "dma_ck", &dma_ck
, CK_16XX
| CK_1510
| CK_310
),
714 CLK(NULL
, "dma_lcdfree_ck", &dma_lcdfree_ck
, CK_16XX
),
715 CLK(NULL
, "api_ck", &api_ck
.clk
, CK_16XX
| CK_1510
| CK_310
| CK_7XX
),
716 CLK(NULL
, "lb_ck", &lb_ck
.clk
, CK_1510
| CK_310
),
717 CLK(NULL
, "rhea1_ck", &rhea1_ck
, CK_16XX
),
718 CLK(NULL
, "rhea2_ck", &rhea2_ck
, CK_16XX
),
719 CLK(NULL
, "lcd_ck", &lcd_ck_16xx
, CK_16XX
| CK_7XX
),
720 CLK(NULL
, "lcd_ck", &lcd_ck_1510
.clk
, CK_1510
| CK_310
),
722 CLK(NULL
, "uart1_ck", &uart1_1510
, CK_1510
| CK_310
),
723 CLK(NULL
, "uart1_ck", &uart1_16xx
.clk
, CK_16XX
),
724 CLK(NULL
, "uart1_ck", &uart1_7xx
, CK_7XX
),
725 CLK(NULL
, "uart2_ck", &uart2_ck
, CK_16XX
| CK_1510
| CK_310
),
726 CLK(NULL
, "uart2_ck", &uart2_7xx
, CK_7XX
),
727 CLK(NULL
, "uart3_ck", &uart3_1510
, CK_1510
| CK_310
),
728 CLK(NULL
, "uart3_ck", &uart3_16xx
.clk
, CK_16XX
),
729 CLK(NULL
, "usb_clko", &usb_clko
, CK_16XX
| CK_1510
| CK_310
),
730 CLK(NULL
, "usb_hhc_ck", &usb_hhc_ck1510
, CK_1510
| CK_310
),
731 CLK(NULL
, "usb_hhc_ck", &usb_hhc_ck16xx
, CK_16XX
),
732 CLK(NULL
, "usb_dc_ck", &usb_dc_ck
, CK_16XX
),
733 CLK(NULL
, "usb_dc_ck", &usb_dc_ck7xx
, CK_7XX
),
734 CLK(NULL
, "mclk", &mclk_1510
, CK_1510
| CK_310
),
735 CLK(NULL
, "mclk", &mclk_16xx
, CK_16XX
),
736 CLK(NULL
, "bclk", &bclk_1510
, CK_1510
| CK_310
),
737 CLK(NULL
, "bclk", &bclk_16xx
, CK_16XX
),
738 CLK("mmci-omap.0", "fck", &mmc1_ck
, CK_16XX
| CK_1510
| CK_310
),
739 CLK("mmci-omap.0", "fck", &mmc3_ck
, CK_7XX
),
740 CLK("mmci-omap.0", "ick", &armper_ck
.clk
, CK_16XX
| CK_1510
| CK_310
| CK_7XX
),
741 CLK("mmci-omap.1", "fck", &mmc2_ck
, CK_16XX
),
742 CLK("mmci-omap.1", "ick", &armper_ck
.clk
, CK_16XX
),
744 CLK(NULL
, "mpu", &virtual_ck_mpu
, CK_16XX
| CK_1510
| CK_310
),
745 CLK("omap_i2c.1", "fck", &i2c_fck
, CK_16XX
| CK_1510
| CK_310
| CK_7XX
),
746 CLK("omap_i2c.1", "ick", &i2c_ick
, CK_16XX
),
747 CLK("omap_i2c.1", "ick", &dummy_ck
, CK_1510
| CK_310
| CK_7XX
),
748 CLK("omap1_spi100k.1", "fck", &dummy_ck
, CK_7XX
),
749 CLK("omap1_spi100k.1", "ick", &dummy_ck
, CK_7XX
),
750 CLK("omap1_spi100k.2", "fck", &dummy_ck
, CK_7XX
),
751 CLK("omap1_spi100k.2", "ick", &dummy_ck
, CK_7XX
),
752 CLK("omap_uwire", "fck", &armxor_ck
.clk
, CK_16XX
| CK_1510
| CK_310
),
753 CLK("omap-mcbsp.1", "ick", &dspper_ck
, CK_16XX
),
754 CLK("omap-mcbsp.1", "ick", &dummy_ck
, CK_1510
| CK_310
),
755 CLK("omap-mcbsp.2", "ick", &armper_ck
.clk
, CK_16XX
),
756 CLK("omap-mcbsp.2", "ick", &dummy_ck
, CK_1510
| CK_310
),
757 CLK("omap-mcbsp.3", "ick", &dspper_ck
, CK_16XX
),
758 CLK("omap-mcbsp.3", "ick", &dummy_ck
, CK_1510
| CK_310
),
759 CLK("omap-mcbsp.1", "fck", &dspxor_ck
, CK_16XX
| CK_1510
| CK_310
),
760 CLK("omap-mcbsp.2", "fck", &armper_ck
.clk
, CK_16XX
| CK_1510
| CK_310
),
761 CLK("omap-mcbsp.3", "fck", &dspxor_ck
, CK_16XX
| CK_1510
| CK_310
),
768 static struct clk_functions omap1_clk_functions
= {
769 .clk_enable
= omap1_clk_enable
,
770 .clk_disable
= omap1_clk_disable
,
771 .clk_round_rate
= omap1_clk_round_rate
,
772 .clk_set_rate
= omap1_clk_set_rate
,
773 .clk_disable_unused
= omap1_clk_disable_unused
,
776 static void __init
omap1_show_rates(void)
778 pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
779 ck_ref
.rate
/ 1000000, (ck_ref
.rate
/ 100000) % 10,
780 ck_dpll1
.rate
/ 1000000, (ck_dpll1
.rate
/ 100000) % 10,
781 arm_ck
.rate
/ 1000000, (arm_ck
.rate
/ 100000) % 10);
786 int __init
omap1_clk_init(void)
789 int crystal_type
= 0; /* Default 12 MHz */
792 #ifdef CONFIG_DEBUG_LL
794 * Resets some clocks that may be left on from bootloader,
795 * but leaves serial clocks on.
797 omap_writel(0x3 << 29, MOD_CONF_CTRL_0
);
800 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
801 reg
= omap_readw(SOFT_REQ_REG
) & (1 << 4);
802 omap_writew(reg
, SOFT_REQ_REG
);
803 if (!cpu_is_omap15xx())
804 omap_writew(0, SOFT_REQ_REG2
);
806 clk_init(&omap1_clk_functions
);
808 /* By default all idlect1 clocks are allowed to idle */
809 arm_idlect1_mask
= ~0;
811 for (c
= omap_clks
; c
< omap_clks
+ ARRAY_SIZE(omap_clks
); c
++)
812 clk_preinit(c
->lk
.clk
);
815 if (cpu_is_omap1710())
817 if (cpu_is_omap16xx())
819 if (cpu_is_omap1510())
821 if (cpu_is_omap7xx())
823 if (cpu_is_omap310())
826 for (c
= omap_clks
; c
< omap_clks
+ ARRAY_SIZE(omap_clks
); c
++)
827 if (c
->cpu
& cpu_mask
) {
829 clk_register(c
->lk
.clk
);
832 /* Pointers to these clocks are needed by code in clock.c */
833 api_ck_p
= clk_get(NULL
, "api_ck");
834 ck_dpll1_p
= clk_get(NULL
, "ck_dpll1");
835 ck_ref_p
= clk_get(NULL
, "ck_ref");
837 if (cpu_is_omap7xx())
838 ck_ref
.rate
= 13000000;
839 if (cpu_is_omap16xx() && crystal_type
== 2)
840 ck_ref
.rate
= 19200000;
842 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
843 omap_readw(ARM_SYSST
), omap_readw(DPLL_CTL
),
844 omap_readw(ARM_CKCTL
));
846 /* We want to be in syncronous scalable mode */
847 omap_writew(0x1000, ARM_SYSST
);
851 * Initially use the values set by bootloader. Determine PLL rate and
852 * recalculate dependent clocks as if kernel had changed PLL or
853 * divisors. See also omap1_clk_late_init() that can reprogram dpll1
854 * after the SRAM is initialized.
857 unsigned pll_ctl_val
= omap_readw(DPLL_CTL
);
859 ck_dpll1
.rate
= ck_ref
.rate
; /* Base xtal rate */
860 if (pll_ctl_val
& 0x10) {
861 /* PLL enabled, apply multiplier and divisor */
862 if (pll_ctl_val
& 0xf80)
863 ck_dpll1
.rate
*= (pll_ctl_val
& 0xf80) >> 7;
864 ck_dpll1
.rate
/= ((pll_ctl_val
& 0x60) >> 5) + 1;
866 /* PLL disabled, apply bypass divisor */
867 switch (pll_ctl_val
& 0xc) {
879 propagate_rate(&ck_dpll1
);
880 /* Cache rates for clocks connected to ck_ref (not dpll1) */
881 propagate_rate(&ck_ref
);
883 if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
884 /* Select slicer output as OMAP input clock */
885 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL
) & ~0x1,
886 OMAP7XX_PCC_UPLD_CTRL
);
889 /* Amstrad Delta wants BCLK high when inactive */
890 if (machine_is_ams_delta())
891 omap_writel(omap_readl(ULPD_CLOCK_CTRL
) |
892 (1 << SDW_MCLK_INV_BIT
),
895 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
896 /* (on 730, bit 13 must not be cleared) */
897 if (cpu_is_omap7xx())
898 omap_writew(omap_readw(ARM_CKCTL
) & 0x2fff, ARM_CKCTL
);
900 omap_writew(omap_readw(ARM_CKCTL
) & 0x0fff, ARM_CKCTL
);
902 /* Put DSP/MPUI into reset until needed */
903 omap_writew(0, ARM_RSTCT1
);
904 omap_writew(1, ARM_RSTCT2
);
905 omap_writew(0x400, ARM_IDLECT1
);
908 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
909 * of the ARM_IDLECT2 register must be set to zero. The power-on
910 * default value of this bit is one.
912 omap_writew(0x0000, ARM_IDLECT2
); /* Turn LCD clock off also */
915 * Only enable those clocks we will need, let the drivers
916 * enable other clocks as necessary
918 clk_enable(&armper_ck
.clk
);
919 clk_enable(&armxor_ck
.clk
);
920 clk_enable(&armtim_ck
.clk
); /* This should be done by timer code */
922 if (cpu_is_omap15xx())
923 clk_enable(&arm_gpio_ck
);
928 #define OMAP1_DPLL1_SANE_VALUE 60000000
930 void __init
omap1_clk_late_init(void)
932 unsigned long rate
= ck_dpll1
.rate
;
934 /* Find the highest supported frequency and enable it */
935 if (omap1_select_table_rate(&virtual_ck_mpu
, ~0)) {
936 pr_err("System frequencies not set, using default. Check your config.\n");
938 * Reprogramming the DPLL is tricky, it must be done from SRAM.
940 omap_sram_reprogram_clock(0x2290, 0x0005);
941 ck_dpll1
.rate
= OMAP1_DPLL1_SANE_VALUE
;
943 propagate_rate(&ck_dpll1
);
945 loops_per_jiffy
= cpufreq_scale(loops_per_jiffy
, rate
, ck_dpll1
.rate
);