2 * linux/arch/arm/mach-omap1/clock_data.c
4 * Copyright (C) 2004 - 2005, 2009 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/clk.h>
17 #include <asm/mach-types.h> /* for machine_is_* */
19 #include <plat/clock.h>
21 #include <plat/clkdev_omap.h>
22 #include <plat/usb.h> /* for OTG_BASE */
26 /*------------------------------------------------------------------------
28 *-------------------------------------------------------------------------*/
30 /* XXX is this necessary? */
31 static struct clk dummy_ck
= {
37 static struct clk ck_ref
= {
43 static struct clk ck_dpll1
= {
50 * FIXME: This clock seems to be necessary but no-one has asked for its
51 * activation. [ FIX: SoSSI, SSR ]
53 static struct arm_idlect1_clk ck_dpll1out
= {
55 .name
= "ck_dpll1out",
56 .ops
= &clkops_generic
,
58 .flags
= CLOCK_IDLE_CONTROL
| ENABLE_REG_32BIT
|
60 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
61 .enable_bit
= EN_CKOUT_ARM
,
62 .recalc
= &followparent_recalc
,
67 static struct clk sossi_ck
= {
69 .ops
= &clkops_generic
,
70 .parent
= &ck_dpll1out
.clk
,
71 .flags
= CLOCK_NO_IDLE_PARENT
| ENABLE_REG_32BIT
,
72 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1
),
74 .recalc
= &omap1_sossi_recalc
,
75 .set_rate
= &omap1_set_sossi_rate
,
78 static struct clk arm_ck
= {
82 .rate_offset
= CKCTL_ARMDIV_OFFSET
,
83 .recalc
= &omap1_ckctl_recalc
,
84 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
85 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
88 static struct arm_idlect1_clk armper_ck
= {
91 .ops
= &clkops_generic
,
93 .flags
= CLOCK_IDLE_CONTROL
,
94 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
95 .enable_bit
= EN_PERCK
,
96 .rate_offset
= CKCTL_PERDIV_OFFSET
,
97 .recalc
= &omap1_ckctl_recalc
,
98 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
99 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
105 * FIXME: This clock seems to be necessary but no-one has asked for its
106 * activation. [ GPIO code for 1510 ]
108 static struct clk arm_gpio_ck
= {
109 .name
= "arm_gpio_ck",
110 .ops
= &clkops_generic
,
112 .flags
= ENABLE_ON_INIT
,
113 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
114 .enable_bit
= EN_GPIOCK
,
115 .recalc
= &followparent_recalc
,
118 static struct arm_idlect1_clk armxor_ck
= {
121 .ops
= &clkops_generic
,
123 .flags
= CLOCK_IDLE_CONTROL
,
124 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
125 .enable_bit
= EN_XORPCK
,
126 .recalc
= &followparent_recalc
,
131 static struct arm_idlect1_clk armtim_ck
= {
134 .ops
= &clkops_generic
,
136 .flags
= CLOCK_IDLE_CONTROL
,
137 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
138 .enable_bit
= EN_TIMCK
,
139 .recalc
= &followparent_recalc
,
144 static struct arm_idlect1_clk armwdt_ck
= {
147 .ops
= &clkops_generic
,
149 .flags
= CLOCK_IDLE_CONTROL
,
150 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
151 .enable_bit
= EN_WDTCK
,
152 .recalc
= &omap1_watchdog_recalc
,
157 static struct clk arminth_ck16xx
= {
158 .name
= "arminth_ck",
161 .recalc
= &followparent_recalc
,
162 /* Note: On 16xx the frequency can be divided by 2 by programming
163 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
165 * 1510 version is in TC clocks.
169 static struct clk dsp_ck
= {
171 .ops
= &clkops_generic
,
173 .enable_reg
= OMAP1_IO_ADDRESS(ARM_CKCTL
),
174 .enable_bit
= EN_DSPCK
,
175 .rate_offset
= CKCTL_DSPDIV_OFFSET
,
176 .recalc
= &omap1_ckctl_recalc
,
177 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
178 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
181 static struct clk dspmmu_ck
= {
185 .rate_offset
= CKCTL_DSPMMUDIV_OFFSET
,
186 .recalc
= &omap1_ckctl_recalc
,
187 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
188 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
191 static struct clk dspper_ck
= {
193 .ops
= &clkops_dspck
,
195 .enable_reg
= DSP_IDLECT2
,
196 .enable_bit
= EN_PERCK
,
197 .rate_offset
= CKCTL_PERDIV_OFFSET
,
198 .recalc
= &omap1_ckctl_recalc_dsp_domain
,
199 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
200 .set_rate
= &omap1_clk_set_rate_dsp_domain
,
203 static struct clk dspxor_ck
= {
205 .ops
= &clkops_dspck
,
207 .enable_reg
= DSP_IDLECT2
,
208 .enable_bit
= EN_XORPCK
,
209 .recalc
= &followparent_recalc
,
212 static struct clk dsptim_ck
= {
214 .ops
= &clkops_dspck
,
216 .enable_reg
= DSP_IDLECT2
,
217 .enable_bit
= EN_DSPTIMCK
,
218 .recalc
= &followparent_recalc
,
221 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
222 static struct arm_idlect1_clk tc_ck
= {
227 .flags
= CLOCK_IDLE_CONTROL
,
228 .rate_offset
= CKCTL_TCDIV_OFFSET
,
229 .recalc
= &omap1_ckctl_recalc
,
230 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
231 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
236 static struct clk arminth_ck1510
= {
237 .name
= "arminth_ck",
239 .parent
= &tc_ck
.clk
,
240 .recalc
= &followparent_recalc
,
241 /* Note: On 1510 the frequency follows TC_CK
243 * 16xx version is in MPU clocks.
247 static struct clk tipb_ck
= {
248 /* No-idle controlled by "tc_ck" */
251 .parent
= &tc_ck
.clk
,
252 .recalc
= &followparent_recalc
,
255 static struct clk l3_ocpi_ck
= {
256 /* No-idle controlled by "tc_ck" */
257 .name
= "l3_ocpi_ck",
258 .ops
= &clkops_generic
,
259 .parent
= &tc_ck
.clk
,
260 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT3
),
261 .enable_bit
= EN_OCPI_CK
,
262 .recalc
= &followparent_recalc
,
265 static struct clk tc1_ck
= {
267 .ops
= &clkops_generic
,
268 .parent
= &tc_ck
.clk
,
269 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT3
),
270 .enable_bit
= EN_TC1_CK
,
271 .recalc
= &followparent_recalc
,
275 * FIXME: This clock seems to be necessary but no-one has asked for its
276 * activation. [ pm.c (SRAM), CCP, Camera ]
278 static struct clk tc2_ck
= {
280 .ops
= &clkops_generic
,
281 .parent
= &tc_ck
.clk
,
282 .flags
= ENABLE_ON_INIT
,
283 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT3
),
284 .enable_bit
= EN_TC2_CK
,
285 .recalc
= &followparent_recalc
,
288 static struct clk dma_ck
= {
289 /* No-idle controlled by "tc_ck" */
292 .parent
= &tc_ck
.clk
,
293 .recalc
= &followparent_recalc
,
296 static struct clk dma_lcdfree_ck
= {
297 .name
= "dma_lcdfree_ck",
299 .parent
= &tc_ck
.clk
,
300 .recalc
= &followparent_recalc
,
303 static struct arm_idlect1_clk api_ck
= {
306 .ops
= &clkops_generic
,
307 .parent
= &tc_ck
.clk
,
308 .flags
= CLOCK_IDLE_CONTROL
,
309 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
310 .enable_bit
= EN_APICK
,
311 .recalc
= &followparent_recalc
,
316 static struct arm_idlect1_clk lb_ck
= {
319 .ops
= &clkops_generic
,
320 .parent
= &tc_ck
.clk
,
321 .flags
= CLOCK_IDLE_CONTROL
,
322 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
323 .enable_bit
= EN_LBCK
,
324 .recalc
= &followparent_recalc
,
329 static struct clk rhea1_ck
= {
332 .parent
= &tc_ck
.clk
,
333 .recalc
= &followparent_recalc
,
336 static struct clk rhea2_ck
= {
339 .parent
= &tc_ck
.clk
,
340 .recalc
= &followparent_recalc
,
343 static struct clk lcd_ck_16xx
= {
345 .ops
= &clkops_generic
,
347 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
348 .enable_bit
= EN_LCDCK
,
349 .rate_offset
= CKCTL_LCDDIV_OFFSET
,
350 .recalc
= &omap1_ckctl_recalc
,
351 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
352 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
355 static struct arm_idlect1_clk lcd_ck_1510
= {
358 .ops
= &clkops_generic
,
360 .flags
= CLOCK_IDLE_CONTROL
,
361 .enable_reg
= OMAP1_IO_ADDRESS(ARM_IDLECT2
),
362 .enable_bit
= EN_LCDCK
,
363 .rate_offset
= CKCTL_LCDDIV_OFFSET
,
364 .recalc
= &omap1_ckctl_recalc
,
365 .round_rate
= omap1_clk_round_rate_ckctl_arm
,
366 .set_rate
= omap1_clk_set_rate_ckctl_arm
,
371 static struct clk uart1_1510
= {
374 /* Direct from ULPD, no real parent */
375 .parent
= &armper_ck
.clk
,
377 .flags
= ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
378 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
379 .enable_bit
= 29, /* Chooses between 12MHz and 48MHz */
380 .set_rate
= &omap1_set_uart_rate
,
381 .recalc
= &omap1_uart_recalc
,
384 static struct uart_clk uart1_16xx
= {
388 /* Direct from ULPD, no real parent */
389 .parent
= &armper_ck
.clk
,
391 .flags
= RATE_FIXED
| ENABLE_REG_32BIT
|
392 CLOCK_NO_IDLE_PARENT
,
393 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
396 .sysc_addr
= 0xfffb0054,
399 static struct clk uart2_ck
= {
402 /* Direct from ULPD, no real parent */
403 .parent
= &armper_ck
.clk
,
405 .flags
= ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
406 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
407 .enable_bit
= 30, /* Chooses between 12MHz and 48MHz */
408 .set_rate
= &omap1_set_uart_rate
,
409 .recalc
= &omap1_uart_recalc
,
412 static struct clk uart3_1510
= {
415 /* Direct from ULPD, no real parent */
416 .parent
= &armper_ck
.clk
,
418 .flags
= ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
419 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
420 .enable_bit
= 31, /* Chooses between 12MHz and 48MHz */
421 .set_rate
= &omap1_set_uart_rate
,
422 .recalc
= &omap1_uart_recalc
,
425 static struct uart_clk uart3_16xx
= {
429 /* Direct from ULPD, no real parent */
430 .parent
= &armper_ck
.clk
,
432 .flags
= RATE_FIXED
| ENABLE_REG_32BIT
|
433 CLOCK_NO_IDLE_PARENT
,
434 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
437 .sysc_addr
= 0xfffb9854,
440 static struct clk usb_clko
= { /* 6 MHz output on W4_USB_CLKO */
442 .ops
= &clkops_generic
,
443 /* Direct from ULPD, no parent */
445 .flags
= RATE_FIXED
| ENABLE_REG_32BIT
,
446 .enable_reg
= OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL
),
447 .enable_bit
= USB_MCLK_EN_BIT
,
450 static struct clk usb_hhc_ck1510
= {
451 .name
= "usb_hhc_ck",
452 .ops
= &clkops_generic
,
453 /* Direct from ULPD, no parent */
454 .rate
= 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
455 .flags
= RATE_FIXED
| ENABLE_REG_32BIT
,
456 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
457 .enable_bit
= USB_HOST_HHC_UHOST_EN
,
460 static struct clk usb_hhc_ck16xx
= {
461 .name
= "usb_hhc_ck",
462 .ops
= &clkops_generic
,
463 /* Direct from ULPD, no parent */
465 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
466 .flags
= RATE_FIXED
| ENABLE_REG_32BIT
,
467 .enable_reg
= OMAP1_IO_ADDRESS(OTG_BASE
+ 0x08), /* OTG_SYSCON_2 */
468 .enable_bit
= 8 /* UHOST_EN */,
471 static struct clk usb_dc_ck
= {
473 .ops
= &clkops_generic
,
474 /* Direct from ULPD, no parent */
477 .enable_reg
= OMAP1_IO_ADDRESS(SOFT_REQ_REG
),
481 static struct clk usb_dc_ck7xx
= {
483 .ops
= &clkops_generic
,
484 /* Direct from ULPD, no parent */
487 .enable_reg
= OMAP1_IO_ADDRESS(SOFT_REQ_REG
),
491 static struct clk mclk_1510
= {
493 .ops
= &clkops_generic
,
494 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
497 .enable_reg
= OMAP1_IO_ADDRESS(SOFT_REQ_REG
),
501 static struct clk mclk_16xx
= {
503 .ops
= &clkops_generic
,
504 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
505 .enable_reg
= OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL
),
506 .enable_bit
= COM_ULPD_PLL_CLK_REQ
,
507 .set_rate
= &omap1_set_ext_clk_rate
,
508 .round_rate
= &omap1_round_ext_clk_rate
,
509 .init
= &omap1_init_ext_clk
,
512 static struct clk bclk_1510
= {
514 .ops
= &clkops_generic
,
515 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
520 static struct clk bclk_16xx
= {
522 .ops
= &clkops_generic
,
523 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
524 .enable_reg
= OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL
),
525 .enable_bit
= SWD_ULPD_PLL_CLK_REQ
,
526 .set_rate
= &omap1_set_ext_clk_rate
,
527 .round_rate
= &omap1_round_ext_clk_rate
,
528 .init
= &omap1_init_ext_clk
,
531 static struct clk mmc1_ck
= {
533 .ops
= &clkops_generic
,
534 /* Functional clock is direct from ULPD, interface clock is ARMPER */
535 .parent
= &armper_ck
.clk
,
537 .flags
= RATE_FIXED
| ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
538 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
542 static struct clk mmc2_ck
= {
545 .ops
= &clkops_generic
,
546 /* Functional clock is direct from ULPD, interface clock is ARMPER */
547 .parent
= &armper_ck
.clk
,
549 .flags
= RATE_FIXED
| ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
550 .enable_reg
= OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0
),
554 static struct clk mmc3_ck
= {
557 .ops
= &clkops_generic
,
558 /* Functional clock is direct from ULPD, interface clock is ARMPER */
559 .parent
= &armper_ck
.clk
,
561 .flags
= RATE_FIXED
| ENABLE_REG_32BIT
| CLOCK_NO_IDLE_PARENT
,
562 .enable_reg
= OMAP1_IO_ADDRESS(SOFT_REQ_REG
),
566 static struct clk virtual_ck_mpu
= {
569 .parent
= &arm_ck
, /* Is smarter alias for */
570 .recalc
= &followparent_recalc
,
571 .set_rate
= &omap1_select_table_rate
,
572 .round_rate
= &omap1_round_to_table_rate
,
575 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
576 remains active during MPU idle whenever this is enabled */
577 static struct clk i2c_fck
= {
581 .flags
= CLOCK_NO_IDLE_PARENT
,
582 .parent
= &armxor_ck
.clk
,
583 .recalc
= &followparent_recalc
,
586 static struct clk i2c_ick
= {
590 .flags
= CLOCK_NO_IDLE_PARENT
,
591 .parent
= &armper_ck
.clk
,
592 .recalc
= &followparent_recalc
,
599 static struct omap_clk omap_clks
[] = {
600 /* non-ULPD clocks */
601 CLK(NULL
, "ck_ref", &ck_ref
, CK_16XX
| CK_1510
| CK_310
| CK_7XX
),
602 CLK(NULL
, "ck_dpll1", &ck_dpll1
, CK_16XX
| CK_1510
| CK_310
),
604 CLK(NULL
, "ck_dpll1out", &ck_dpll1out
.clk
, CK_16XX
),
605 CLK(NULL
, "ck_sossi", &sossi_ck
, CK_16XX
),
606 CLK(NULL
, "arm_ck", &arm_ck
, CK_16XX
| CK_1510
| CK_310
),
607 CLK(NULL
, "armper_ck", &armper_ck
.clk
, CK_16XX
| CK_1510
| CK_310
),
608 CLK(NULL
, "arm_gpio_ck", &arm_gpio_ck
, CK_1510
| CK_310
),
609 CLK(NULL
, "armxor_ck", &armxor_ck
.clk
, CK_16XX
| CK_1510
| CK_310
| CK_7XX
),
610 CLK(NULL
, "armtim_ck", &armtim_ck
.clk
, CK_16XX
| CK_1510
| CK_310
),
611 CLK("omap_wdt", "fck", &armwdt_ck
.clk
, CK_16XX
| CK_1510
| CK_310
),
612 CLK("omap_wdt", "ick", &armper_ck
.clk
, CK_16XX
),
613 CLK("omap_wdt", "ick", &dummy_ck
, CK_1510
| CK_310
),
614 CLK(NULL
, "arminth_ck", &arminth_ck1510
, CK_1510
| CK_310
),
615 CLK(NULL
, "arminth_ck", &arminth_ck16xx
, CK_16XX
),
617 CLK(NULL
, "dsp_ck", &dsp_ck
, CK_16XX
| CK_1510
| CK_310
),
618 CLK(NULL
, "dspmmu_ck", &dspmmu_ck
, CK_16XX
| CK_1510
| CK_310
),
619 CLK(NULL
, "dspper_ck", &dspper_ck
, CK_16XX
| CK_1510
| CK_310
),
620 CLK(NULL
, "dspxor_ck", &dspxor_ck
, CK_16XX
| CK_1510
| CK_310
),
621 CLK(NULL
, "dsptim_ck", &dsptim_ck
, CK_16XX
| CK_1510
| CK_310
),
623 CLK(NULL
, "tc_ck", &tc_ck
.clk
, CK_16XX
| CK_1510
| CK_310
| CK_7XX
),
624 CLK(NULL
, "tipb_ck", &tipb_ck
, CK_1510
| CK_310
),
625 CLK(NULL
, "l3_ocpi_ck", &l3_ocpi_ck
, CK_16XX
| CK_7XX
),
626 CLK(NULL
, "tc1_ck", &tc1_ck
, CK_16XX
),
627 CLK(NULL
, "tc2_ck", &tc2_ck
, CK_16XX
),
628 CLK(NULL
, "dma_ck", &dma_ck
, CK_16XX
| CK_1510
| CK_310
),
629 CLK(NULL
, "dma_lcdfree_ck", &dma_lcdfree_ck
, CK_16XX
),
630 CLK(NULL
, "api_ck", &api_ck
.clk
, CK_16XX
| CK_1510
| CK_310
),
631 CLK(NULL
, "lb_ck", &lb_ck
.clk
, CK_1510
| CK_310
),
632 CLK(NULL
, "rhea1_ck", &rhea1_ck
, CK_16XX
),
633 CLK(NULL
, "rhea2_ck", &rhea2_ck
, CK_16XX
),
634 CLK(NULL
, "lcd_ck", &lcd_ck_16xx
, CK_16XX
| CK_7XX
),
635 CLK(NULL
, "lcd_ck", &lcd_ck_1510
.clk
, CK_1510
| CK_310
),
637 CLK(NULL
, "uart1_ck", &uart1_1510
, CK_1510
| CK_310
),
638 CLK(NULL
, "uart1_ck", &uart1_16xx
.clk
, CK_16XX
),
639 CLK(NULL
, "uart2_ck", &uart2_ck
, CK_16XX
| CK_1510
| CK_310
),
640 CLK(NULL
, "uart3_ck", &uart3_1510
, CK_1510
| CK_310
),
641 CLK(NULL
, "uart3_ck", &uart3_16xx
.clk
, CK_16XX
),
642 CLK(NULL
, "usb_clko", &usb_clko
, CK_16XX
| CK_1510
| CK_310
),
643 CLK(NULL
, "usb_hhc_ck", &usb_hhc_ck1510
, CK_1510
| CK_310
),
644 CLK(NULL
, "usb_hhc_ck", &usb_hhc_ck16xx
, CK_16XX
),
645 CLK(NULL
, "usb_dc_ck", &usb_dc_ck
, CK_16XX
),
646 CLK(NULL
, "usb_dc_ck", &usb_dc_ck7xx
, CK_7XX
),
647 CLK(NULL
, "mclk", &mclk_1510
, CK_1510
| CK_310
),
648 CLK(NULL
, "mclk", &mclk_16xx
, CK_16XX
),
649 CLK(NULL
, "bclk", &bclk_1510
, CK_1510
| CK_310
),
650 CLK(NULL
, "bclk", &bclk_16xx
, CK_16XX
),
651 CLK("mmci-omap.0", "fck", &mmc1_ck
, CK_16XX
| CK_1510
| CK_310
),
652 CLK("mmci-omap.0", "fck", &mmc3_ck
, CK_7XX
),
653 CLK("mmci-omap.0", "ick", &armper_ck
.clk
, CK_16XX
| CK_1510
| CK_310
| CK_7XX
),
654 CLK("mmci-omap.1", "fck", &mmc2_ck
, CK_16XX
),
655 CLK("mmci-omap.1", "ick", &armper_ck
.clk
, CK_16XX
),
657 CLK(NULL
, "mpu", &virtual_ck_mpu
, CK_16XX
| CK_1510
| CK_310
),
658 CLK("i2c_omap.1", "fck", &i2c_fck
, CK_16XX
| CK_1510
| CK_310
| CK_7XX
),
659 CLK("i2c_omap.1", "ick", &i2c_ick
, CK_16XX
),
660 CLK("i2c_omap.1", "ick", &dummy_ck
, CK_1510
| CK_310
| CK_7XX
),
661 CLK("omap_uwire", "fck", &armxor_ck
.clk
, CK_16XX
| CK_1510
| CK_310
),
662 CLK("omap-mcbsp.1", "ick", &dspper_ck
, CK_16XX
),
663 CLK("omap-mcbsp.1", "ick", &dummy_ck
, CK_1510
| CK_310
),
664 CLK("omap-mcbsp.2", "ick", &armper_ck
.clk
, CK_16XX
),
665 CLK("omap-mcbsp.2", "ick", &dummy_ck
, CK_1510
| CK_310
),
666 CLK("omap-mcbsp.3", "ick", &dspper_ck
, CK_16XX
),
667 CLK("omap-mcbsp.3", "ick", &dummy_ck
, CK_1510
| CK_310
),
668 CLK("omap-mcbsp.1", "fck", &dspxor_ck
, CK_16XX
| CK_1510
| CK_310
),
669 CLK("omap-mcbsp.2", "fck", &armper_ck
.clk
, CK_16XX
| CK_1510
| CK_310
),
670 CLK("omap-mcbsp.3", "fck", &dspxor_ck
, CK_16XX
| CK_1510
| CK_310
),
677 static struct clk_functions omap1_clk_functions __initdata
= {
678 .clk_enable
= omap1_clk_enable
,
679 .clk_disable
= omap1_clk_disable
,
680 .clk_round_rate
= omap1_clk_round_rate
,
681 .clk_set_rate
= omap1_clk_set_rate
,
682 .clk_disable_unused
= omap1_clk_disable_unused
,
685 int __init
omap1_clk_init(void)
688 const struct omap_clock_config
*info
;
689 int crystal_type
= 0; /* Default 12 MHz */
692 #ifdef CONFIG_DEBUG_LL
694 * Resets some clocks that may be left on from bootloader,
695 * but leaves serial clocks on.
697 omap_writel(0x3 << 29, MOD_CONF_CTRL_0
);
700 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
701 reg
= omap_readw(SOFT_REQ_REG
) & (1 << 4);
702 omap_writew(reg
, SOFT_REQ_REG
);
703 if (!cpu_is_omap15xx())
704 omap_writew(0, SOFT_REQ_REG2
);
706 clk_init(&omap1_clk_functions
);
708 /* By default all idlect1 clocks are allowed to idle */
709 arm_idlect1_mask
= ~0;
711 for (c
= omap_clks
; c
< omap_clks
+ ARRAY_SIZE(omap_clks
); c
++)
712 clk_preinit(c
->lk
.clk
);
715 if (cpu_is_omap16xx())
717 if (cpu_is_omap1510())
719 if (cpu_is_omap7xx())
721 if (cpu_is_omap310())
724 for (c
= omap_clks
; c
< omap_clks
+ ARRAY_SIZE(omap_clks
); c
++)
725 if (c
->cpu
& cpu_mask
) {
727 clk_register(c
->lk
.clk
);
730 /* Pointers to these clocks are needed by code in clock.c */
731 api_ck_p
= clk_get(NULL
, "api_ck");
732 ck_dpll1_p
= clk_get(NULL
, "ck_dpll1");
733 ck_ref_p
= clk_get(NULL
, "ck_ref");
735 info
= omap_get_config(OMAP_TAG_CLOCK
, struct omap_clock_config
);
737 if (!cpu_is_omap15xx())
738 crystal_type
= info
->system_clock_type
;
741 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
742 ck_ref
.rate
= 13000000;
743 #elif defined(CONFIG_ARCH_OMAP16XX)
744 if (crystal_type
== 2)
745 ck_ref
.rate
= 19200000;
748 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
749 "0x%04x\n", omap_readw(ARM_SYSST
), omap_readw(DPLL_CTL
),
750 omap_readw(ARM_CKCTL
));
752 /* We want to be in syncronous scalable mode */
753 omap_writew(0x1000, ARM_SYSST
);
755 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
756 /* Use values set by bootloader. Determine PLL rate and recalculate
757 * dependent clocks as if kernel had changed PLL or divisors.
760 unsigned pll_ctl_val
= omap_readw(DPLL_CTL
);
762 ck_dpll1
.rate
= ck_ref
.rate
; /* Base xtal rate */
763 if (pll_ctl_val
& 0x10) {
764 /* PLL enabled, apply multiplier and divisor */
765 if (pll_ctl_val
& 0xf80)
766 ck_dpll1
.rate
*= (pll_ctl_val
& 0xf80) >> 7;
767 ck_dpll1
.rate
/= ((pll_ctl_val
& 0x60) >> 5) + 1;
769 /* PLL disabled, apply bypass divisor */
770 switch (pll_ctl_val
& 0xc) {
783 /* Find the highest supported frequency and enable it */
784 if (omap1_select_table_rate(&virtual_ck_mpu
, ~0)) {
785 printk(KERN_ERR
"System frequencies not set. Check your config.\n");
786 /* Guess sane values (60MHz) */
787 omap_writew(0x2290, DPLL_CTL
);
788 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL
);
789 ck_dpll1
.rate
= 60000000;
792 propagate_rate(&ck_dpll1
);
793 /* Cache rates for clocks connected to ck_ref (not dpll1) */
794 propagate_rate(&ck_ref
);
795 printk(KERN_INFO
"Clocking rate (xtal/DPLL1/MPU): "
796 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
797 ck_ref
.rate
/ 1000000, (ck_ref
.rate
/ 100000) % 10,
798 ck_dpll1
.rate
/ 1000000, (ck_dpll1
.rate
/ 100000) % 10,
799 arm_ck
.rate
/ 1000000, (arm_ck
.rate
/ 100000) % 10);
801 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
802 /* Select slicer output as OMAP input clock */
803 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL
) & ~0x1, OMAP7XX_PCC_UPLD_CTRL
);
806 /* Amstrad Delta wants BCLK high when inactive */
807 if (machine_is_ams_delta())
808 omap_writel(omap_readl(ULPD_CLOCK_CTRL
) |
809 (1 << SDW_MCLK_INV_BIT
),
812 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
813 /* (on 730, bit 13 must not be cleared) */
814 if (cpu_is_omap7xx())
815 omap_writew(omap_readw(ARM_CKCTL
) & 0x2fff, ARM_CKCTL
);
817 omap_writew(omap_readw(ARM_CKCTL
) & 0x0fff, ARM_CKCTL
);
819 /* Put DSP/MPUI into reset until needed */
820 omap_writew(0, ARM_RSTCT1
);
821 omap_writew(1, ARM_RSTCT2
);
822 omap_writew(0x400, ARM_IDLECT1
);
825 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
826 * of the ARM_IDLECT2 register must be set to zero. The power-on
827 * default value of this bit is one.
829 omap_writew(0x0000, ARM_IDLECT2
); /* Turn LCD clock off also */
832 * Only enable those clocks we will need, let the drivers
833 * enable other clocks as necessary
835 clk_enable(&armper_ck
.clk
);
836 clk_enable(&armxor_ck
.clk
);
837 clk_enable(&armtim_ck
.clk
); /* This should be done by timer code */
839 if (cpu_is_omap15xx())
840 clk_enable(&arm_gpio_ck
);