arch/arm/mach-omap1/time.c

   1 /*
   2  * linux/arch/arm/mach-omap1/time.c
   3  *
   4  * OMAP Timers
   5  *
   6  * Copyright (C) 2004 Nokia Corporation
   7  * Partial timer rewrite and additional dynamic tick timer support by
   8  * Tony Lindgen <tony@atomide.com> and
   9  * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10  *
  11  * MPU timer code based on the older MPU timer code for OMAP
  12  * Copyright (C) 2000 RidgeRun, Inc.
  13  * Author: Greg Lonnon <glonnon@ridgerun.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify it
  16  * under the terms of the GNU General Public License as published by the
  17  * Free Software Foundation; either version 2 of the License, or (at your
  18  * option) any later version.
  19  *
  20  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  21  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  22  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  23  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  26  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  27  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * You should have received a copy of the  GNU General Public License along
  32  * with this program; if not, write  to the Free Software Foundation, Inc.,
  33  * 675 Mass Ave, Cambridge, MA 02139, USA.
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/init.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/sched.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/clk.h>
  43 #include <linux/err.h>
  44 #include <linux/clocksource.h>
  45 #include <linux/clockchips.h>
  46 #include <linux/io.h>
  47
  48 #include <asm/system.h>
  49 #include <mach/hardware.h>
  50 #include <asm/leds.h>
  51 #include <asm/irq.h>
  52 #include <asm/mach/irq.h>
  53 #include <asm/mach/time.h>
  54
  55 #include <plat/common.h>
  56
  57 #define OMAP_MPU_TIMER_BASE             OMAP_MPU_TIMER1_BASE
  58 #define OMAP_MPU_TIMER_OFFSET           0x100
  59
  60 typedef struct {
  61         u32 cntl;                       /* CNTL_TIMER, R/W */
  62         u32 load_tim;                   /* LOAD_TIM,   W */
  63         u32 read_tim;                   /* READ_TIM,   R */
  64 } omap_mpu_timer_regs_t;
  65
  66 #define omap_mpu_timer_base(n)                                                  \
  67 ((volatile omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE +        \
  68                                  (n)*OMAP_MPU_TIMER_OFFSET))
  69
  70 static inline unsigned long omap_mpu_timer_read(int nr)
  71 {
  72         volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
  73         return timer->read_tim;
  74 }
  75
  76 static inline void omap_mpu_set_autoreset(int nr)
  77 {
  78         volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
  79
  80         timer->cntl = timer->cntl | MPU_TIMER_AR;
  81 }
  82
  83 static inline void omap_mpu_remove_autoreset(int nr)
  84 {
  85         volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
  86
  87         timer->cntl = timer->cntl & ~MPU_TIMER_AR;
  88 }
  89
  90 static inline void omap_mpu_timer_start(int nr, unsigned long load_val,
  91                                         int autoreset)
  92 {
  93         volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
  94         unsigned int timerflags = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST);
  95
  96         if (autoreset) timerflags |= MPU_TIMER_AR;
  97
  98         timer->cntl = MPU_TIMER_CLOCK_ENABLE;
  99         udelay(1);
 100         timer->load_tim = load_val;
 101         udelay(1);
 102         timer->cntl = timerflags;
 103 }
 104
 105 static inline void omap_mpu_timer_stop(int nr)
 106 {
 107         volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
 108
 109         timer->cntl &= ~MPU_TIMER_ST;
 110 }
 111
 112 /*
 113  * ---------------------------------------------------------------------------
 114  * MPU timer 1 ... count down to zero, interrupt, reload
 115  * ---------------------------------------------------------------------------
 116  */
 117 static int omap_mpu_set_next_event(unsigned long cycles,
 118                                    struct clock_event_device *evt)
 119 {
 120         omap_mpu_timer_start(0, cycles, 0);
 121         return 0;
 122 }
 123
 124 static void omap_mpu_set_mode(enum clock_event_mode mode,
 125                               struct clock_event_device *evt)
 126 {
 127         switch (mode) {
 128         case CLOCK_EVT_MODE_PERIODIC:
 129                 omap_mpu_set_autoreset(0);
 130                 break;
 131         case CLOCK_EVT_MODE_ONESHOT:
 132                 omap_mpu_timer_stop(0);
 133                 omap_mpu_remove_autoreset(0);
 134                 break;
 135         case CLOCK_EVT_MODE_UNUSED:
 136         case CLOCK_EVT_MODE_SHUTDOWN:
 137         case CLOCK_EVT_MODE_RESUME:
 138                 break;
 139         }
 140 }
 141
 142 static struct clock_event_device clockevent_mpu_timer1 = {
 143         .name           = "mpu_timer1",
 144         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 145         .shift          = 32,
 146         .set_next_event = omap_mpu_set_next_event,
 147         .set_mode       = omap_mpu_set_mode,
 148 };
 149
 150 static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id)
 151 {
 152         struct clock_event_device *evt = &clockevent_mpu_timer1;
 153
 154         evt->event_handler(evt);
 155
 156         return IRQ_HANDLED;
 157 }
 158
 159 static struct irqaction omap_mpu_timer1_irq = {
 160         .name           = "mpu_timer1",
 161         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 162         .handler        = omap_mpu_timer1_interrupt,
 163 };
 164
 165 static __init void omap_init_mpu_timer(unsigned long rate)
 166 {
 167         setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
 168         omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
 169
 170         clockevent_mpu_timer1.mult = div_sc(rate, NSEC_PER_SEC,
 171                                             clockevent_mpu_timer1.shift);
 172         clockevent_mpu_timer1.max_delta_ns =
 173                 clockevent_delta2ns(-1, &clockevent_mpu_timer1);
 174         clockevent_mpu_timer1.min_delta_ns =
 175                 clockevent_delta2ns(1, &clockevent_mpu_timer1);
 176
 177         clockevent_mpu_timer1.cpumask = cpumask_of(0);
 178         clockevents_register_device(&clockevent_mpu_timer1);
 179 }
 180
 181
 182 /*
 183  * ---------------------------------------------------------------------------
 184  * MPU timer 2 ... free running 32-bit clock source and scheduler clock
 185  * ---------------------------------------------------------------------------
 186  */
 187
 188 static unsigned long omap_mpu_timer2_overflows;
 189
 190 static irqreturn_t omap_mpu_timer2_interrupt(int irq, void *dev_id)
 191 {
 192         omap_mpu_timer2_overflows++;
 193         return IRQ_HANDLED;
 194 }
 195
 196 static struct irqaction omap_mpu_timer2_irq = {
 197         .name           = "mpu_timer2",
 198         .flags          = IRQF_DISABLED,
 199         .handler        = omap_mpu_timer2_interrupt,
 200 };
 201
 202 static cycle_t mpu_read(struct clocksource *cs)
 203 {
 204         return ~omap_mpu_timer_read(1);
 205 }
 206
 207 static struct clocksource clocksource_mpu = {
 208         .name           = "mpu_timer2",
 209         .rating         = 300,
 210         .read           = mpu_read,
 211         .mask           = CLOCKSOURCE_MASK(32),
 212         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 213 };
 214
 215 static void __init omap_init_clocksource(unsigned long rate)
 216 {
 217         static char err[] __initdata = KERN_ERR
 218                         "%s: can't register clocksource!\n";
 219
 220         setup_irq(INT_TIMER2, &omap_mpu_timer2_irq);
 221         omap_mpu_timer_start(1, ~0, 1);
 222
 223         if (clocksource_register_hz(&clocksource_mpu, rate))
 224                 printk(err, clocksource_mpu.name);
 225 }
 226
 227 /*
 228  * ---------------------------------------------------------------------------
 229  * Timer initialization
 230  * ---------------------------------------------------------------------------
 231  */
 232 static void __init omap_timer_init(void)
 233 {
 234         struct clk      *ck_ref = clk_get(NULL, "ck_ref");
 235         unsigned long   rate;
 236
 237         BUG_ON(IS_ERR(ck_ref));
 238
 239         rate = clk_get_rate(ck_ref);
 240         clk_put(ck_ref);
 241
 242         /* PTV = 0 */
 243         rate /= 2;
 244
 245         omap_init_mpu_timer(rate);
 246         omap_init_clocksource(rate);
 247 }
 248
 249 struct sys_timer omap_timer = {
 250         .init           = omap_timer_init,
 251 };