arch/arm/mach-omap2/cclock2430_data.c

   1 /*
   2  * OMAP2430 clock data
   3  *
   4  * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2011 Nokia Corporation
   6  *
   7  * Contacts:
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/clk.h>
  18 #include <linux/clk-private.h>
  19 #include <linux/list.h>
  20
  21 #include "soc.h"
  22 #include "iomap.h"
  23 #include "clock.h"
  24 #include "clock2xxx.h"
  25 #include "opp2xxx.h"
  26 #include "cm2xxx.h"
  27 #include "prm2xxx.h"
  28 #include "prm-regbits-24xx.h"
  29 #include "cm-regbits-24xx.h"
  30 #include "sdrc.h"
  31 #include "control.h"
  32
  33 #define OMAP_CM_REGADDR                 OMAP2430_CM_REGADDR
  34
  35 /*
  36  * 2430 clock tree.
  37  *
  38  * NOTE:In many cases here we are assigning a 'default' parent. In
  39  *      many cases the parent is selectable. The set parent calls will
  40  *      also switch sources.
  41  *
  42  *      Several sources are given initial rates which may be wrong, this will
  43  *      be fixed up in the init func.
  44  *
  45  *      Things are broadly separated below by clock domains. It is
  46  *      noteworthy that most peripherals have dependencies on multiple clock
  47  *      domains. Many get their interface clocks from the L4 domain, but get
  48  *      functional clocks from fixed sources or other core domain derived
  49  *      clocks.
  50  */
  51
  52 DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
  53
  54 DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
  55
  56 DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
  57
  58 static struct clk osc_ck;
  59
  60 static const struct clk_ops osc_ck_ops = {
  61         .enable         = &omap2_enable_osc_ck,
  62         .disable        = omap2_disable_osc_ck,
  63         .recalc_rate    = &omap2_osc_clk_recalc,
  64 };
  65
  66 static struct clk_hw_omap osc_ck_hw = {
  67         .hw = {
  68                 .clk = &osc_ck,
  69         },
  70 };
  71
  72 static struct clk osc_ck = {
  73         .name   = "osc_ck",
  74         .ops    = &osc_ck_ops,
  75         .hw     = &osc_ck_hw.hw,
  76         .flags  = CLK_IS_ROOT,
  77 };
  78
  79 DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
  80
  81 static struct clk sys_ck;
  82
  83 static const char *sys_ck_parent_names[] = {
  84         "osc_ck",
  85 };
  86
  87 static const struct clk_ops sys_ck_ops = {
  88         .init           = &omap2_init_clk_clkdm,
  89         .recalc_rate    = &omap2xxx_sys_clk_recalc,
  90 };
  91
  92 DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
  93 DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
  94
  95 static struct dpll_data dpll_dd = {
  96         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  97         .mult_mask      = OMAP24XX_DPLL_MULT_MASK,
  98         .div1_mask      = OMAP24XX_DPLL_DIV_MASK,
  99         .clk_bypass     = &sys_ck,
 100         .clk_ref        = &sys_ck,
 101         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 102         .enable_mask    = OMAP24XX_EN_DPLL_MASK,
 103         .max_multiplier = 1023,
 104         .min_divider    = 1,
 105         .max_divider    = 16,
 106 };
 107
 108 static struct clk dpll_ck;
 109
 110 static const char *dpll_ck_parent_names[] = {
 111         "sys_ck",
 112 };
 113
 114 static const struct clk_ops dpll_ck_ops = {
 115         .init           = &omap2_init_clk_clkdm,
 116         .get_parent     = &omap2_init_dpll_parent,
 117         .recalc_rate    = &omap2_dpllcore_recalc,
 118         .round_rate     = &omap2_dpll_round_rate,
 119         .set_rate       = &omap2_reprogram_dpllcore,
 120 };
 121
 122 static struct clk_hw_omap dpll_ck_hw = {
 123         .hw = {
 124                 .clk = &dpll_ck,
 125         },
 126         .ops            = &clkhwops_omap2xxx_dpll,
 127         .dpll_data      = &dpll_dd,
 128         .clkdm_name     = "wkup_clkdm",
 129 };
 130
 131 DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops);
 132
 133 static struct clk core_ck;
 134
 135 static const char *core_ck_parent_names[] = {
 136         "dpll_ck",
 137 };
 138
 139 static const struct clk_ops core_ck_ops = {
 140         .init           = &omap2_init_clk_clkdm,
 141 };
 142
 143 DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm");
 144 DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
 145
 146 DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
 147                    OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 148                    OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
 149                    CLK_DIVIDER_ONE_BASED, NULL);
 150
 151 DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
 152                    OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 153                    OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
 154                    CLK_DIVIDER_ONE_BASED, NULL);
 155
 156 static struct clk aes_ick;
 157
 158 static const char *aes_ick_parent_names[] = {
 159         "l4_ck",
 160 };
 161
 162 static const struct clk_ops aes_ick_ops = {
 163         .init           = &omap2_init_clk_clkdm,
 164         .enable         = &omap2_dflt_clk_enable,
 165         .disable        = &omap2_dflt_clk_disable,
 166         .is_enabled     = &omap2_dflt_clk_is_enabled,
 167 };
 168
 169 static struct clk_hw_omap aes_ick_hw = {
 170         .hw = {
 171                 .clk = &aes_ick,
 172         },
 173         .ops            = &clkhwops_iclk_wait,
 174         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
 175         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
 176         .clkdm_name     = "core_l4_clkdm",
 177 };
 178
 179 DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops);
 180
 181 static struct clk apll54_ck;
 182
 183 static const struct clk_ops apll54_ck_ops = {
 184         .init           = &omap2_init_clk_clkdm,
 185         .enable         = &omap2_clk_apll54_enable,
 186         .disable        = &omap2_clk_apll54_disable,
 187         .recalc_rate    = &omap2_clk_apll54_recalc,
 188 };
 189
 190 static struct clk_hw_omap apll54_ck_hw = {
 191         .hw = {
 192                 .clk = &apll54_ck,
 193         },
 194         .ops            = &clkhwops_apll54,
 195         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 196         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 197         .flags          = ENABLE_ON_INIT,
 198         .clkdm_name     = "wkup_clkdm",
 199 };
 200
 201 DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops);
 202
 203 static struct clk apll96_ck;
 204
 205 static const struct clk_ops apll96_ck_ops = {
 206         .init           = &omap2_init_clk_clkdm,
 207         .enable         = &omap2_clk_apll96_enable,
 208         .disable        = &omap2_clk_apll96_disable,
 209         .recalc_rate    = &omap2_clk_apll96_recalc,
 210 };
 211
 212 static struct clk_hw_omap apll96_ck_hw = {
 213         .hw = {
 214                 .clk = &apll96_ck,
 215         },
 216         .ops            = &clkhwops_apll96,
 217         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 218         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 219         .flags          = ENABLE_ON_INIT,
 220         .clkdm_name     = "wkup_clkdm",
 221 };
 222
 223 DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops);
 224
 225 static const char *func_96m_ck_parent_names[] = {
 226         "apll96_ck", "alt_ck",
 227 };
 228
 229 DEFINE_CLK_MUX(func_96m_ck, func_96m_ck_parent_names, NULL, 0x0,
 230                OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP2430_96M_SOURCE_SHIFT,
 231                OMAP2430_96M_SOURCE_WIDTH, 0x0, NULL);
 232
 233 static struct clk cam_fck;
 234
 235 static const char *cam_fck_parent_names[] = {
 236         "func_96m_ck",
 237 };
 238
 239 static struct clk_hw_omap cam_fck_hw = {
 240         .hw = {
 241                 .clk = &cam_fck,
 242         },
 243         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 244         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
 245         .clkdm_name     = "core_l3_clkdm",
 246 };
 247
 248 DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops);
 249
 250 static struct clk cam_ick;
 251
 252 static struct clk_hw_omap cam_ick_hw = {
 253         .hw = {
 254                 .clk = &cam_ick,
 255         },
 256         .ops            = &clkhwops_iclk,
 257         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 258         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
 259         .clkdm_name     = "core_l4_clkdm",
 260 };
 261
 262 DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops);
 263
 264 static struct clk des_ick;
 265
 266 static struct clk_hw_omap des_ick_hw = {
 267         .hw = {
 268                 .clk = &des_ick,
 269         },
 270         .ops            = &clkhwops_iclk_wait,
 271         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
 272         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
 273         .clkdm_name     = "core_l4_clkdm",
 274 };
 275
 276 DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops);
 277
 278 static const struct clksel_rate dsp_fck_core_rates[] = {
 279         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 280         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 281         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 282         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 283         { .div = 0 }
 284 };
 285
 286 static const struct clksel dsp_fck_clksel[] = {
 287         { .parent = &core_ck, .rates = dsp_fck_core_rates },
 288         { .parent = NULL },
 289 };
 290
 291 static const char *dsp_fck_parent_names[] = {
 292         "core_ck",
 293 };
 294
 295 static struct clk dsp_fck;
 296
 297 static const struct clk_ops dsp_fck_ops = {
 298         .init           = &omap2_init_clk_clkdm,
 299         .enable         = &omap2_dflt_clk_enable,
 300         .disable        = &omap2_dflt_clk_disable,
 301         .is_enabled     = &omap2_dflt_clk_is_enabled,
 302         .recalc_rate    = &omap2_clksel_recalc,
 303         .set_rate       = &omap2_clksel_set_rate,
 304         .round_rate     = &omap2_clksel_round_rate,
 305 };
 306
 307 DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
 308                          OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 309                          OMAP24XX_CLKSEL_DSP_MASK,
 310                          OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
 311                          OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
 312                          dsp_fck_parent_names, dsp_fck_ops);
 313
 314 static const struct clksel_rate dss1_fck_sys_rates[] = {
 315         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 316         { .div = 0 }
 317 };
 318
 319 static const struct clksel_rate dss1_fck_core_rates[] = {
 320         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 321         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 322         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 323         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 324         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
 325         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
 326         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
 327         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
 328         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
 329         { .div = 16, .val = 16, .flags = RATE_IN_24XX },
 330         { .div = 0 }
 331 };
 332
 333 static const struct clksel dss1_fck_clksel[] = {
 334         { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
 335         { .parent = &core_ck, .rates = dss1_fck_core_rates },
 336         { .parent = NULL },
 337 };
 338
 339 static const char *dss1_fck_parent_names[] = {
 340         "sys_ck", "core_ck",
 341 };
 342
 343 static const struct clk_ops dss1_fck_ops = {
 344         .init           = &omap2_init_clk_clkdm,
 345         .enable         = &omap2_dflt_clk_enable,
 346         .disable        = &omap2_dflt_clk_disable,
 347         .is_enabled     = &omap2_dflt_clk_is_enabled,
 348         .recalc_rate    = &omap2_clksel_recalc,
 349         .get_parent     = &omap2_clksel_find_parent_index,
 350         .set_parent     = &omap2_clksel_set_parent,
 351 };
 352
 353 DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
 354                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 355                          OMAP24XX_CLKSEL_DSS1_MASK,
 356                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 357                          OMAP24XX_EN_DSS1_SHIFT, NULL,
 358                          dss1_fck_parent_names, dss1_fck_ops);
 359
 360 static const struct clksel_rate dss2_fck_sys_rates[] = {
 361         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 362         { .div = 0 }
 363 };
 364
 365 static const struct clksel_rate dss2_fck_48m_rates[] = {
 366         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 367         { .div = 0 }
 368 };
 369
 370 static const struct clksel_rate func_48m_apll96_rates[] = {
 371         { .div = 2, .val = 0, .flags = RATE_IN_24XX },
 372         { .div = 0 }
 373 };
 374
 375 static const struct clksel_rate func_48m_alt_rates[] = {
 376         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 377         { .div = 0 }
 378 };
 379
 380 static const struct clksel func_48m_clksel[] = {
 381         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 382         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 383         { .parent = NULL },
 384 };
 385
 386 static const char *func_48m_ck_parent_names[] = {
 387         "apll96_ck", "alt_ck",
 388 };
 389
 390 static struct clk func_48m_ck;
 391
 392 static const struct clk_ops func_48m_ck_ops = {
 393         .init           = &omap2_init_clk_clkdm,
 394         .recalc_rate    = &omap2_clksel_recalc,
 395         .set_rate       = &omap2_clksel_set_rate,
 396         .round_rate     = &omap2_clksel_round_rate,
 397         .get_parent     = &omap2_clksel_find_parent_index,
 398         .set_parent     = &omap2_clksel_set_parent,
 399 };
 400
 401 static struct clk_hw_omap func_48m_ck_hw = {
 402         .hw = {
 403                 .clk = &func_48m_ck,
 404         },
 405         .clksel         = func_48m_clksel,
 406         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 407         .clksel_mask    = OMAP24XX_48M_SOURCE_MASK,
 408         .clkdm_name     = "wkup_clkdm",
 409 };
 410
 411 DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
 412
 413 static const struct clksel dss2_fck_clksel[] = {
 414         { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
 415         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
 416         { .parent = NULL },
 417 };
 418
 419 static const char *dss2_fck_parent_names[] = {
 420         "sys_ck", "func_48m_ck",
 421 };
 422
 423 DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
 424                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 425                          OMAP24XX_CLKSEL_DSS2_MASK,
 426                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 427                          OMAP24XX_EN_DSS2_SHIFT, NULL,
 428                          dss2_fck_parent_names, dss1_fck_ops);
 429
 430 static const char *func_54m_ck_parent_names[] = {
 431         "apll54_ck", "alt_ck",
 432 };
 433
 434 DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
 435                OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 436                OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL);
 437
 438 static struct clk dss_54m_fck;
 439
 440 static const char *dss_54m_fck_parent_names[] = {
 441         "func_54m_ck",
 442 };
 443
 444 static struct clk_hw_omap dss_54m_fck_hw = {
 445         .hw = {
 446                 .clk = &dss_54m_fck,
 447         },
 448         .ops            = &clkhwops_wait,
 449         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 450         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
 451         .clkdm_name     = "dss_clkdm",
 452 };
 453
 454 DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops);
 455
 456 static struct clk dss_ick;
 457
 458 static struct clk_hw_omap dss_ick_hw = {
 459         .hw = {
 460                 .clk = &dss_ick,
 461         },
 462         .ops            = &clkhwops_iclk,
 463         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 464         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
 465         .clkdm_name     = "dss_clkdm",
 466 };
 467
 468 DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops);
 469
 470 static struct clk emul_ck;
 471
 472 static struct clk_hw_omap emul_ck_hw = {
 473         .hw = {
 474                 .clk = &emul_ck,
 475         },
 476         .enable_reg     = OMAP2430_PRCM_CLKEMUL_CTRL,
 477         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 478         .clkdm_name     = "wkup_clkdm",
 479 };
 480
 481 DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops);
 482
 483 DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4);
 484
 485 static struct clk fac_fck;
 486
 487 static const char *fac_fck_parent_names[] = {
 488         "func_12m_ck",
 489 };
 490
 491 static struct clk_hw_omap fac_fck_hw = {
 492         .hw = {
 493                 .clk = &fac_fck,
 494         },
 495         .ops            = &clkhwops_wait,
 496         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 497         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
 498         .clkdm_name     = "core_l4_clkdm",
 499 };
 500
 501 DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops);
 502
 503 static struct clk fac_ick;
 504
 505 static struct clk_hw_omap fac_ick_hw = {
 506         .hw = {
 507                 .clk = &fac_ick,
 508         },
 509         .ops            = &clkhwops_iclk_wait,
 510         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 511         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
 512         .clkdm_name     = "core_l4_clkdm",
 513 };
 514
 515 DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops);
 516
 517 static const struct clksel gfx_fck_clksel[] = {
 518         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
 519         { .parent = NULL },
 520 };
 521
 522 static const char *gfx_2d_fck_parent_names[] = {
 523         "core_l3_ck",
 524 };
 525
 526 DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel,
 527                          OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
 528                          OMAP_CLKSEL_GFX_MASK,
 529                          OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 530                          OMAP24XX_EN_2D_SHIFT, &clkhwops_wait,
 531                          gfx_2d_fck_parent_names, dsp_fck_ops);
 532
 533 DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel,
 534                          OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
 535                          OMAP_CLKSEL_GFX_MASK,
 536                          OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 537                          OMAP24XX_EN_3D_SHIFT, &clkhwops_wait,
 538                          gfx_2d_fck_parent_names, dsp_fck_ops);
 539
 540 static struct clk gfx_ick;
 541
 542 static const char *gfx_ick_parent_names[] = {
 543         "core_l3_ck",
 544 };
 545
 546 static struct clk_hw_omap gfx_ick_hw = {
 547         .hw = {
 548                 .clk = &gfx_ick,
 549         },
 550         .ops            = &clkhwops_wait,
 551         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
 552         .enable_bit     = OMAP_EN_GFX_SHIFT,
 553         .clkdm_name     = "gfx_clkdm",
 554 };
 555
 556 DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops);
 557
 558 static struct clk gpio5_fck;
 559
 560 static const char *gpio5_fck_parent_names[] = {
 561         "func_32k_ck",
 562 };
 563
 564 static struct clk_hw_omap gpio5_fck_hw = {
 565         .hw = {
 566                 .clk = &gpio5_fck,
 567         },
 568         .ops            = &clkhwops_wait,
 569         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 570         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
 571         .clkdm_name     = "core_l4_clkdm",
 572 };
 573
 574 DEFINE_STRUCT_CLK(gpio5_fck, gpio5_fck_parent_names, aes_ick_ops);
 575
 576 static struct clk gpio5_ick;
 577
 578 static struct clk_hw_omap gpio5_ick_hw = {
 579         .hw = {
 580                 .clk = &gpio5_ick,
 581         },
 582         .ops            = &clkhwops_iclk_wait,
 583         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 584         .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
 585         .clkdm_name     = "core_l4_clkdm",
 586 };
 587
 588 DEFINE_STRUCT_CLK(gpio5_ick, aes_ick_parent_names, aes_ick_ops);
 589
 590 static struct clk gpios_fck;
 591
 592 static struct clk_hw_omap gpios_fck_hw = {
 593         .hw = {
 594                 .clk = &gpios_fck,
 595         },
 596         .ops            = &clkhwops_wait,
 597         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 598         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
 599         .clkdm_name     = "wkup_clkdm",
 600 };
 601
 602 DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops);
 603
 604 static struct clk wu_l4_ick;
 605
 606 DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
 607 DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
 608
 609 static struct clk gpios_ick;
 610
 611 static const char *gpios_ick_parent_names[] = {
 612         "wu_l4_ick",
 613 };
 614
 615 static struct clk_hw_omap gpios_ick_hw = {
 616         .hw = {
 617                 .clk = &gpios_ick,
 618         },
 619         .ops            = &clkhwops_iclk_wait,
 620         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 621         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
 622         .clkdm_name     = "wkup_clkdm",
 623 };
 624
 625 DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops);
 626
 627 static struct clk gpmc_fck;
 628
 629 static struct clk_hw_omap gpmc_fck_hw = {
 630         .hw = {
 631                 .clk = &gpmc_fck,
 632         },
 633         .ops            = &clkhwops_iclk,
 634         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
 635         .enable_bit     = OMAP24XX_AUTO_GPMC_SHIFT,
 636         .flags          = ENABLE_ON_INIT,
 637         .clkdm_name     = "core_l3_clkdm",
 638 };
 639
 640 DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops);
 641
 642 static const struct clksel_rate gpt_alt_rates[] = {
 643         { .div = 1, .val = 2, .flags = RATE_IN_24XX },
 644         { .div = 0 }
 645 };
 646
 647 static const struct clksel omap24xx_gpt_clksel[] = {
 648         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
 649         { .parent = &sys_ck, .rates = gpt_sys_rates },
 650         { .parent = &alt_ck, .rates = gpt_alt_rates },
 651         { .parent = NULL },
 652 };
 653
 654 static const char *gpt10_fck_parent_names[] = {
 655         "func_32k_ck", "sys_ck", "alt_ck",
 656 };
 657
 658 DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
 659                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 660                          OMAP24XX_CLKSEL_GPT10_MASK,
 661                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 662                          OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait,
 663                          gpt10_fck_parent_names, dss1_fck_ops);
 664
 665 static struct clk gpt10_ick;
 666
 667 static struct clk_hw_omap gpt10_ick_hw = {
 668         .hw = {
 669                 .clk = &gpt10_ick,
 670         },
 671         .ops            = &clkhwops_iclk_wait,
 672         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 673         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
 674         .clkdm_name     = "core_l4_clkdm",
 675 };
 676
 677 DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops);
 678
 679 DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
 680                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 681                          OMAP24XX_CLKSEL_GPT11_MASK,
 682                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 683                          OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait,
 684                          gpt10_fck_parent_names, dss1_fck_ops);
 685
 686 static struct clk gpt11_ick;
 687
 688 static struct clk_hw_omap gpt11_ick_hw = {
 689         .hw = {
 690                 .clk = &gpt11_ick,
 691         },
 692         .ops            = &clkhwops_iclk_wait,
 693         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 694         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
 695         .clkdm_name     = "core_l4_clkdm",
 696 };
 697
 698 DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops);
 699
 700 DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
 701                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 702                          OMAP24XX_CLKSEL_GPT12_MASK,
 703                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 704                          OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait,
 705                          gpt10_fck_parent_names, dss1_fck_ops);
 706
 707 static struct clk gpt12_ick;
 708
 709 static struct clk_hw_omap gpt12_ick_hw = {
 710         .hw = {
 711                 .clk = &gpt12_ick,
 712         },
 713         .ops            = &clkhwops_iclk_wait,
 714         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 715         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
 716         .clkdm_name     = "core_l4_clkdm",
 717 };
 718
 719 DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops);
 720
 721 static const struct clk_ops gpt1_fck_ops = {
 722         .init           = &omap2_init_clk_clkdm,
 723         .enable         = &omap2_dflt_clk_enable,
 724         .disable        = &omap2_dflt_clk_disable,
 725         .is_enabled     = &omap2_dflt_clk_is_enabled,
 726         .recalc_rate    = &omap2_clksel_recalc,
 727         .set_rate       = &omap2_clksel_set_rate,
 728         .round_rate     = &omap2_clksel_round_rate,
 729         .get_parent     = &omap2_clksel_find_parent_index,
 730         .set_parent     = &omap2_clksel_set_parent,
 731 };
 732
 733 DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
 734                          OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
 735                          OMAP24XX_CLKSEL_GPT1_MASK,
 736                          OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 737                          OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
 738                          gpt10_fck_parent_names, gpt1_fck_ops);
 739
 740 static struct clk gpt1_ick;
 741
 742 static struct clk_hw_omap gpt1_ick_hw = {
 743         .hw = {
 744                 .clk = &gpt1_ick,
 745         },
 746         .ops            = &clkhwops_iclk_wait,
 747         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 748         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
 749         .clkdm_name     = "wkup_clkdm",
 750 };
 751
 752 DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
 753
 754 DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
 755                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 756                          OMAP24XX_CLKSEL_GPT2_MASK,
 757                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 758                          OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
 759                          gpt10_fck_parent_names, dss1_fck_ops);
 760
 761 static struct clk gpt2_ick;
 762
 763 static struct clk_hw_omap gpt2_ick_hw = {
 764         .hw = {
 765                 .clk = &gpt2_ick,
 766         },
 767         .ops            = &clkhwops_iclk_wait,
 768         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 769         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
 770         .clkdm_name     = "core_l4_clkdm",
 771 };
 772
 773 DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops);
 774
 775 DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
 776                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 777                          OMAP24XX_CLKSEL_GPT3_MASK,
 778                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 779                          OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait,
 780                          gpt10_fck_parent_names, dss1_fck_ops);
 781
 782 static struct clk gpt3_ick;
 783
 784 static struct clk_hw_omap gpt3_ick_hw = {
 785         .hw = {
 786                 .clk = &gpt3_ick,
 787         },
 788         .ops            = &clkhwops_iclk_wait,
 789         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 790         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
 791         .clkdm_name     = "core_l4_clkdm",
 792 };
 793
 794 DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops);
 795
 796 DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
 797                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 798                          OMAP24XX_CLKSEL_GPT4_MASK,
 799                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 800                          OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait,
 801                          gpt10_fck_parent_names, dss1_fck_ops);
 802
 803 static struct clk gpt4_ick;
 804
 805 static struct clk_hw_omap gpt4_ick_hw = {
 806         .hw = {
 807                 .clk = &gpt4_ick,
 808         },
 809         .ops            = &clkhwops_iclk_wait,
 810         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 811         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
 812         .clkdm_name     = "core_l4_clkdm",
 813 };
 814
 815 DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops);
 816
 817 DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
 818                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 819                          OMAP24XX_CLKSEL_GPT5_MASK,
 820                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 821                          OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
 822                          gpt10_fck_parent_names, dss1_fck_ops);
 823
 824 static struct clk gpt5_ick;
 825
 826 static struct clk_hw_omap gpt5_ick_hw = {
 827         .hw = {
 828                 .clk = &gpt5_ick,
 829         },
 830         .ops            = &clkhwops_iclk_wait,
 831         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 832         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
 833         .clkdm_name     = "core_l4_clkdm",
 834 };
 835
 836 DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
 837
 838 DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
 839                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 840                          OMAP24XX_CLKSEL_GPT6_MASK,
 841                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 842                          OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
 843                          gpt10_fck_parent_names, dss1_fck_ops);
 844
 845 static struct clk gpt6_ick;
 846
 847 static struct clk_hw_omap gpt6_ick_hw = {
 848         .hw = {
 849                 .clk = &gpt6_ick,
 850         },
 851         .ops            = &clkhwops_iclk_wait,
 852         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 853         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
 854         .clkdm_name     = "core_l4_clkdm",
 855 };
 856
 857 DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
 858
 859 DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
 860                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 861                          OMAP24XX_CLKSEL_GPT7_MASK,
 862                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 863                          OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
 864                          gpt10_fck_parent_names, dss1_fck_ops);
 865
 866 static struct clk gpt7_ick;
 867
 868 static struct clk_hw_omap gpt7_ick_hw = {
 869         .hw = {
 870                 .clk = &gpt7_ick,
 871         },
 872         .ops            = &clkhwops_iclk_wait,
 873         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 874         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
 875         .clkdm_name     = "core_l4_clkdm",
 876 };
 877
 878 DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
 879
 880 static struct clk gpt8_fck;
 881
 882 DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
 883                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 884                          OMAP24XX_CLKSEL_GPT8_MASK,
 885                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 886                          OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait,
 887                          gpt10_fck_parent_names, dss1_fck_ops);
 888
 889 static struct clk gpt8_ick;
 890
 891 static struct clk_hw_omap gpt8_ick_hw = {
 892         .hw = {
 893                 .clk = &gpt8_ick,
 894         },
 895         .ops            = &clkhwops_iclk_wait,
 896         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 897         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
 898         .clkdm_name     = "core_l4_clkdm",
 899 };
 900
 901 DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops);
 902
 903 DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
 904                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 905                          OMAP24XX_CLKSEL_GPT9_MASK,
 906                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 907                          OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait,
 908                          gpt10_fck_parent_names, dss1_fck_ops);
 909
 910 static struct clk gpt9_ick;
 911
 912 static struct clk_hw_omap gpt9_ick_hw = {
 913         .hw = {
 914                 .clk = &gpt9_ick,
 915         },
 916         .ops            = &clkhwops_iclk_wait,
 917         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 918         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
 919         .clkdm_name     = "core_l4_clkdm",
 920 };
 921
 922 DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops);
 923
 924 static struct clk hdq_fck;
 925
 926 static struct clk_hw_omap hdq_fck_hw = {
 927         .hw = {
 928                 .clk = &hdq_fck,
 929         },
 930         .ops            = &clkhwops_wait,
 931         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 932         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
 933         .clkdm_name     = "core_l4_clkdm",
 934 };
 935
 936 DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops);
 937
 938 static struct clk hdq_ick;
 939
 940 static struct clk_hw_omap hdq_ick_hw = {
 941         .hw = {
 942                 .clk = &hdq_ick,
 943         },
 944         .ops            = &clkhwops_iclk_wait,
 945         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 946         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
 947         .clkdm_name     = "core_l4_clkdm",
 948 };
 949
 950 DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops);
 951
 952 static struct clk i2c1_ick;
 953
 954 static struct clk_hw_omap i2c1_ick_hw = {
 955         .hw = {
 956                 .clk = &i2c1_ick,
 957         },
 958         .ops            = &clkhwops_iclk_wait,
 959         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 960         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
 961         .clkdm_name     = "core_l4_clkdm",
 962 };
 963
 964 DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops);
 965
 966 static struct clk i2c2_ick;
 967
 968 static struct clk_hw_omap i2c2_ick_hw = {
 969         .hw = {
 970                 .clk = &i2c2_ick,
 971         },
 972         .ops            = &clkhwops_iclk_wait,
 973         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 974         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
 975         .clkdm_name     = "core_l4_clkdm",
 976 };
 977
 978 DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops);
 979
 980 static struct clk i2chs1_fck;
 981
 982 static struct clk_hw_omap i2chs1_fck_hw = {
 983         .hw = {
 984                 .clk = &i2chs1_fck,
 985         },
 986         .ops            = &clkhwops_omap2430_i2chs_wait,
 987         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 988         .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
 989         .clkdm_name     = "core_l4_clkdm",
 990 };
 991
 992 DEFINE_STRUCT_CLK(i2chs1_fck, cam_fck_parent_names, aes_ick_ops);
 993
 994 static struct clk i2chs2_fck;
 995
 996 static struct clk_hw_omap i2chs2_fck_hw = {
 997         .hw = {
 998                 .clk = &i2chs2_fck,
 999         },
1000         .ops            = &clkhwops_omap2430_i2chs_wait,
1001         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1002         .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
1003         .clkdm_name     = "core_l4_clkdm",
1004 };
1005
1006 DEFINE_STRUCT_CLK(i2chs2_fck, cam_fck_parent_names, aes_ick_ops);
1007
1008 static struct clk icr_ick;
1009
1010 static struct clk_hw_omap icr_ick_hw = {
1011         .hw = {
1012                 .clk = &icr_ick,
1013         },
1014         .ops            = &clkhwops_iclk_wait,
1015         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1016         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
1017         .clkdm_name     = "wkup_clkdm",
1018 };
1019
1020 DEFINE_STRUCT_CLK(icr_ick, gpios_ick_parent_names, aes_ick_ops);
1021
1022 static const struct clksel dsp_ick_clksel[] = {
1023         { .parent = &dsp_fck, .rates = dsp_ick_rates },
1024         { .parent = NULL },
1025 };
1026
1027 static const char *iva2_1_ick_parent_names[] = {
1028         "dsp_fck",
1029 };
1030
1031 DEFINE_CLK_OMAP_MUX_GATE(iva2_1_ick, "dsp_clkdm", dsp_ick_clksel,
1032                          OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1033                          OMAP24XX_CLKSEL_DSP_IF_MASK,
1034                          OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1035                          OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
1036                          iva2_1_ick_parent_names, dsp_fck_ops);
1037
1038 static struct clk mailboxes_ick;
1039
1040 static struct clk_hw_omap mailboxes_ick_hw = {
1041         .hw = {
1042                 .clk = &mailboxes_ick,
1043         },
1044         .ops            = &clkhwops_iclk_wait,
1045         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1046         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
1047         .clkdm_name     = "core_l4_clkdm",
1048 };
1049
1050 DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops);
1051
1052 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1053         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1054         { .div = 0 }
1055 };
1056
1057 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1058         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1059         { .div = 0 }
1060 };
1061
1062 static const struct clksel mcbsp_fck_clksel[] = {
1063         { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1064         { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1065         { .parent = NULL },
1066 };
1067
1068 static const char *mcbsp1_fck_parent_names[] = {
1069         "func_96m_ck", "mcbsp_clks",
1070 };
1071
1072 DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1073                          OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1074                          OMAP2_MCBSP1_CLKS_MASK,
1075                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1076                          OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait,
1077                          mcbsp1_fck_parent_names, dss1_fck_ops);
1078
1079 static struct clk mcbsp1_ick;
1080
1081 static struct clk_hw_omap mcbsp1_ick_hw = {
1082         .hw = {
1083                 .clk = &mcbsp1_ick,
1084         },
1085         .ops            = &clkhwops_iclk_wait,
1086         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1087         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1088         .clkdm_name     = "core_l4_clkdm",
1089 };
1090
1091 DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops);
1092
1093 DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1094                          OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1095                          OMAP2_MCBSP2_CLKS_MASK,
1096                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1097                          OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait,
1098                          mcbsp1_fck_parent_names, dss1_fck_ops);
1099
1100 static struct clk mcbsp2_ick;
1101
1102 static struct clk_hw_omap mcbsp2_ick_hw = {
1103         .hw = {
1104                 .clk = &mcbsp2_ick,
1105         },
1106         .ops            = &clkhwops_iclk_wait,
1107         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1108         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1109         .clkdm_name     = "core_l4_clkdm",
1110 };
1111
1112 DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops);
1113
1114 DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1115                          OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1116                          OMAP2_MCBSP3_CLKS_MASK,
1117                          OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1118                          OMAP2430_EN_MCBSP3_SHIFT, &clkhwops_wait,
1119                          mcbsp1_fck_parent_names, dss1_fck_ops);
1120
1121 static struct clk mcbsp3_ick;
1122
1123 static struct clk_hw_omap mcbsp3_ick_hw = {
1124         .hw = {
1125                 .clk = &mcbsp3_ick,
1126         },
1127         .ops            = &clkhwops_iclk_wait,
1128         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1129         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
1130         .clkdm_name     = "core_l4_clkdm",
1131 };
1132
1133 DEFINE_STRUCT_CLK(mcbsp3_ick, aes_ick_parent_names, aes_ick_ops);
1134
1135 DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1136                          OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1137                          OMAP2_MCBSP4_CLKS_MASK,
1138                          OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1139                          OMAP2430_EN_MCBSP4_SHIFT, &clkhwops_wait,
1140                          mcbsp1_fck_parent_names, dss1_fck_ops);
1141
1142 static struct clk mcbsp4_ick;
1143
1144 static struct clk_hw_omap mcbsp4_ick_hw = {
1145         .hw = {
1146                 .clk = &mcbsp4_ick,
1147         },
1148         .ops            = &clkhwops_iclk_wait,
1149         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1150         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
1151         .clkdm_name     = "core_l4_clkdm",
1152 };
1153
1154 DEFINE_STRUCT_CLK(mcbsp4_ick, aes_ick_parent_names, aes_ick_ops);
1155
1156 DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1157                          OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1158                          OMAP2_MCBSP5_CLKS_MASK,
1159                          OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1160                          OMAP2430_EN_MCBSP5_SHIFT, &clkhwops_wait,
1161                          mcbsp1_fck_parent_names, dss1_fck_ops);
1162
1163 static struct clk mcbsp5_ick;
1164
1165 static struct clk_hw_omap mcbsp5_ick_hw = {
1166         .hw = {
1167                 .clk = &mcbsp5_ick,
1168         },
1169         .ops            = &clkhwops_iclk_wait,
1170         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1171         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
1172         .clkdm_name     = "core_l4_clkdm",
1173 };
1174
1175 DEFINE_STRUCT_CLK(mcbsp5_ick, aes_ick_parent_names, aes_ick_ops);
1176
1177 static struct clk mcspi1_fck;
1178
1179 static const char *mcspi1_fck_parent_names[] = {
1180         "func_48m_ck",
1181 };
1182
1183 static struct clk_hw_omap mcspi1_fck_hw = {
1184         .hw = {
1185                 .clk = &mcspi1_fck,
1186         },
1187         .ops            = &clkhwops_wait,
1188         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1189         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1190         .clkdm_name     = "core_l4_clkdm",
1191 };
1192
1193 DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops);
1194
1195 static struct clk mcspi1_ick;
1196
1197 static struct clk_hw_omap mcspi1_ick_hw = {
1198         .hw = {
1199                 .clk = &mcspi1_ick,
1200         },
1201         .ops            = &clkhwops_iclk_wait,
1202         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1203         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1204         .clkdm_name     = "core_l4_clkdm",
1205 };
1206
1207 DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops);
1208
1209 static struct clk mcspi2_fck;
1210
1211 static struct clk_hw_omap mcspi2_fck_hw = {
1212         .hw = {
1213                 .clk = &mcspi2_fck,
1214         },
1215         .ops            = &clkhwops_wait,
1216         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1217         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1218         .clkdm_name     = "core_l4_clkdm",
1219 };
1220
1221 DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops);
1222
1223 static struct clk mcspi2_ick;
1224
1225 static struct clk_hw_omap mcspi2_ick_hw = {
1226         .hw = {
1227                 .clk = &mcspi2_ick,
1228         },
1229         .ops            = &clkhwops_iclk_wait,
1230         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1231         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1232         .clkdm_name     = "core_l4_clkdm",
1233 };
1234
1235 DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops);
1236
1237 static struct clk mcspi3_fck;
1238
1239 static struct clk_hw_omap mcspi3_fck_hw = {
1240         .hw = {
1241                 .clk = &mcspi3_fck,
1242         },
1243         .ops            = &clkhwops_wait,
1244         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1245         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1246         .clkdm_name     = "core_l4_clkdm",
1247 };
1248
1249 DEFINE_STRUCT_CLK(mcspi3_fck, mcspi1_fck_parent_names, aes_ick_ops);
1250
1251 static struct clk mcspi3_ick;
1252
1253 static struct clk_hw_omap mcspi3_ick_hw = {
1254         .hw = {
1255                 .clk = &mcspi3_ick,
1256         },
1257         .ops            = &clkhwops_iclk_wait,
1258         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1259         .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
1260         .clkdm_name     = "core_l4_clkdm",
1261 };
1262
1263 DEFINE_STRUCT_CLK(mcspi3_ick, aes_ick_parent_names, aes_ick_ops);
1264
1265 static const struct clksel_rate mdm_ick_core_rates[] = {
1266         { .div = 1, .val = 1, .flags = RATE_IN_243X },
1267         { .div = 4, .val = 4, .flags = RATE_IN_243X },
1268         { .div = 6, .val = 6, .flags = RATE_IN_243X },
1269         { .div = 9, .val = 9, .flags = RATE_IN_243X },
1270         { .div = 0 }
1271 };
1272
1273 static const struct clksel mdm_ick_clksel[] = {
1274         { .parent = &core_ck, .rates = mdm_ick_core_rates },
1275         { .parent = NULL },
1276 };
1277
1278 static const char *mdm_ick_parent_names[] = {
1279         "core_ck",
1280 };
1281
1282 DEFINE_CLK_OMAP_MUX_GATE(mdm_ick, "mdm_clkdm", mdm_ick_clksel,
1283                          OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1284                          OMAP2430_CLKSEL_MDM_MASK,
1285                          OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1286                          OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1287                          &clkhwops_iclk_wait, mdm_ick_parent_names,
1288                          dsp_fck_ops);
1289
1290 static struct clk mdm_intc_ick;
1291
1292 static struct clk_hw_omap mdm_intc_ick_hw = {
1293         .hw = {
1294                 .clk = &mdm_intc_ick,
1295         },
1296         .ops            = &clkhwops_iclk_wait,
1297         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1298         .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
1299         .clkdm_name     = "core_l4_clkdm",
1300 };
1301
1302 DEFINE_STRUCT_CLK(mdm_intc_ick, aes_ick_parent_names, aes_ick_ops);
1303
1304 static struct clk mdm_osc_ck;
1305
1306 static struct clk_hw_omap mdm_osc_ck_hw = {
1307         .hw = {
1308                 .clk = &mdm_osc_ck,
1309         },
1310         .ops            = &clkhwops_iclk_wait,
1311         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1312         .enable_bit     = OMAP2430_EN_OSC_SHIFT,
1313         .clkdm_name     = "mdm_clkdm",
1314 };
1315
1316 DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops);
1317
1318 static struct clk mmchs1_fck;
1319
1320 static struct clk_hw_omap mmchs1_fck_hw = {
1321         .hw = {
1322                 .clk = &mmchs1_fck,
1323         },
1324         .ops            = &clkhwops_wait,
1325         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1326         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
1327         .clkdm_name     = "core_l4_clkdm",
1328 };
1329
1330 DEFINE_STRUCT_CLK(mmchs1_fck, cam_fck_parent_names, aes_ick_ops);
1331
1332 static struct clk mmchs1_ick;
1333
1334 static struct clk_hw_omap mmchs1_ick_hw = {
1335         .hw = {
1336                 .clk = &mmchs1_ick,
1337         },
1338         .ops            = &clkhwops_iclk_wait,
1339         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1340         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
1341         .clkdm_name     = "core_l4_clkdm",
1342 };
1343
1344 DEFINE_STRUCT_CLK(mmchs1_ick, aes_ick_parent_names, aes_ick_ops);
1345
1346 static struct clk mmchs2_fck;
1347
1348 static struct clk_hw_omap mmchs2_fck_hw = {
1349         .hw = {
1350                 .clk = &mmchs2_fck,
1351         },
1352         .ops            = &clkhwops_wait,
1353         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1354         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
1355         .clkdm_name     = "core_l4_clkdm",
1356 };
1357
1358 DEFINE_STRUCT_CLK(mmchs2_fck, cam_fck_parent_names, aes_ick_ops);
1359
1360 static struct clk mmchs2_ick;
1361
1362 static struct clk_hw_omap mmchs2_ick_hw = {
1363         .hw = {
1364                 .clk = &mmchs2_ick,
1365         },
1366         .ops            = &clkhwops_iclk_wait,
1367         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1368         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
1369         .clkdm_name     = "core_l4_clkdm",
1370 };
1371
1372 DEFINE_STRUCT_CLK(mmchs2_ick, aes_ick_parent_names, aes_ick_ops);
1373
1374 static struct clk mmchsdb1_fck;
1375
1376 static struct clk_hw_omap mmchsdb1_fck_hw = {
1377         .hw = {
1378                 .clk = &mmchsdb1_fck,
1379         },
1380         .ops            = &clkhwops_wait,
1381         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1382         .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
1383         .clkdm_name     = "core_l4_clkdm",
1384 };
1385
1386 DEFINE_STRUCT_CLK(mmchsdb1_fck, gpio5_fck_parent_names, aes_ick_ops);
1387
1388 static struct clk mmchsdb2_fck;
1389
1390 static struct clk_hw_omap mmchsdb2_fck_hw = {
1391         .hw = {
1392                 .clk = &mmchsdb2_fck,
1393         },
1394         .ops            = &clkhwops_wait,
1395         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1396         .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
1397         .clkdm_name     = "core_l4_clkdm",
1398 };
1399
1400 DEFINE_STRUCT_CLK(mmchsdb2_fck, gpio5_fck_parent_names, aes_ick_ops);
1401
1402 DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
1403                    OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
1404                    OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
1405                    CLK_DIVIDER_ONE_BASED, NULL);
1406
1407 static struct clk mpu_wdt_fck;
1408
1409 static struct clk_hw_omap mpu_wdt_fck_hw = {
1410         .hw = {
1411                 .clk = &mpu_wdt_fck,
1412         },
1413         .ops            = &clkhwops_wait,
1414         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1415         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1416         .clkdm_name     = "wkup_clkdm",
1417 };
1418
1419 DEFINE_STRUCT_CLK(mpu_wdt_fck, gpio5_fck_parent_names, aes_ick_ops);
1420
1421 static struct clk mpu_wdt_ick;
1422
1423 static struct clk_hw_omap mpu_wdt_ick_hw = {
1424         .hw = {
1425                 .clk = &mpu_wdt_ick,
1426         },
1427         .ops            = &clkhwops_iclk_wait,
1428         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1429         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1430         .clkdm_name     = "wkup_clkdm",
1431 };
1432
1433 DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops);
1434
1435 static struct clk mspro_fck;
1436
1437 static struct clk_hw_omap mspro_fck_hw = {
1438         .hw = {
1439                 .clk = &mspro_fck,
1440         },
1441         .ops            = &clkhwops_wait,
1442         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1443         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
1444         .clkdm_name     = "core_l4_clkdm",
1445 };
1446
1447 DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops);
1448
1449 static struct clk mspro_ick;
1450
1451 static struct clk_hw_omap mspro_ick_hw = {
1452         .hw = {
1453                 .clk = &mspro_ick,
1454         },
1455         .ops            = &clkhwops_iclk_wait,
1456         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1457         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
1458         .clkdm_name     = "core_l4_clkdm",
1459 };
1460
1461 DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops);
1462
1463 static struct clk omapctrl_ick;
1464
1465 static struct clk_hw_omap omapctrl_ick_hw = {
1466         .hw = {
1467                 .clk = &omapctrl_ick,
1468         },
1469         .ops            = &clkhwops_iclk_wait,
1470         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1471         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
1472         .flags          = ENABLE_ON_INIT,
1473         .clkdm_name     = "wkup_clkdm",
1474 };
1475
1476 DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops);
1477
1478 static struct clk pka_ick;
1479
1480 static struct clk_hw_omap pka_ick_hw = {
1481         .hw = {
1482                 .clk = &pka_ick,
1483         },
1484         .ops            = &clkhwops_iclk_wait,
1485         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1486         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
1487         .clkdm_name     = "core_l4_clkdm",
1488 };
1489
1490 DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops);
1491
1492 static struct clk rng_ick;
1493
1494 static struct clk_hw_omap rng_ick_hw = {
1495         .hw = {
1496                 .clk = &rng_ick,
1497         },
1498         .ops            = &clkhwops_iclk_wait,
1499         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1500         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
1501         .clkdm_name     = "core_l4_clkdm",
1502 };
1503
1504 DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops);
1505
1506 static struct clk sdma_fck;
1507
1508 DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm");
1509 DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops);
1510
1511 static struct clk sdma_ick;
1512
1513 static struct clk_hw_omap sdma_ick_hw = {
1514         .hw = {
1515                 .clk = &sdma_ick,
1516         },
1517         .ops            = &clkhwops_iclk,
1518         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1519         .enable_bit     = OMAP24XX_AUTO_SDMA_SHIFT,
1520         .clkdm_name     = "core_l3_clkdm",
1521 };
1522
1523 DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops);
1524
1525 static struct clk sdrc_ick;
1526
1527 static struct clk_hw_omap sdrc_ick_hw = {
1528         .hw = {
1529                 .clk = &sdrc_ick,
1530         },
1531         .ops            = &clkhwops_iclk,
1532         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1533         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
1534         .flags          = ENABLE_ON_INIT,
1535         .clkdm_name     = "core_l3_clkdm",
1536 };
1537
1538 DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops);
1539
1540 static struct clk sha_ick;
1541
1542 static struct clk_hw_omap sha_ick_hw = {
1543         .hw = {
1544                 .clk = &sha_ick,
1545         },
1546         .ops            = &clkhwops_iclk_wait,
1547         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1548         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
1549         .clkdm_name     = "core_l4_clkdm",
1550 };
1551
1552 DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops);
1553
1554 static struct clk ssi_l4_ick;
1555
1556 static struct clk_hw_omap ssi_l4_ick_hw = {
1557         .hw = {
1558                 .clk = &ssi_l4_ick,
1559         },
1560         .ops            = &clkhwops_iclk_wait,
1561         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1562         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
1563         .clkdm_name     = "core_l4_clkdm",
1564 };
1565
1566 DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops);
1567
1568 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1569         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1570         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1571         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1572         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1573         { .div = 5, .val = 5, .flags = RATE_IN_243X },
1574         { .div = 0 }
1575 };
1576
1577 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1578         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1579         { .parent = NULL },
1580 };
1581
1582 static const char *ssi_ssr_sst_fck_parent_names[] = {
1583         "core_ck",
1584 };
1585
1586 DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm",
1587                          ssi_ssr_sst_fck_clksel,
1588                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1589                          OMAP24XX_CLKSEL_SSI_MASK,
1590                          OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1591                          OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait,
1592                          ssi_ssr_sst_fck_parent_names, dsp_fck_ops);
1593
1594 static struct clk sync_32k_ick;
1595
1596 static struct clk_hw_omap sync_32k_ick_hw = {
1597         .hw = {
1598                 .clk = &sync_32k_ick,
1599         },
1600         .ops            = &clkhwops_iclk_wait,
1601         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1602         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
1603         .flags          = ENABLE_ON_INIT,
1604         .clkdm_name     = "wkup_clkdm",
1605 };
1606
1607 DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops);
1608
1609 static const struct clksel_rate common_clkout_src_core_rates[] = {
1610         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1611         { .div = 0 }
1612 };
1613
1614 static const struct clksel_rate common_clkout_src_sys_rates[] = {
1615         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1616         { .div = 0 }
1617 };
1618
1619 static const struct clksel_rate common_clkout_src_96m_rates[] = {
1620         { .div = 1, .val = 2, .flags = RATE_IN_24XX },
1621         { .div = 0 }
1622 };
1623
1624 static const struct clksel_rate common_clkout_src_54m_rates[] = {
1625         { .div = 1, .val = 3, .flags = RATE_IN_24XX },
1626         { .div = 0 }
1627 };
1628
1629 static const struct clksel common_clkout_src_clksel[] = {
1630         { .parent = &core_ck, .rates = common_clkout_src_core_rates },
1631         { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
1632         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
1633         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
1634         { .parent = NULL },
1635 };
1636
1637 static const char *sys_clkout_src_parent_names[] = {
1638         "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck",
1639 };
1640
1641 DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
1642                          OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK,
1643                          OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT,
1644                          NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
1645
1646 DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
1647                    OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
1648                    OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
1649
1650 static struct clk uart1_fck;
1651
1652 static struct clk_hw_omap uart1_fck_hw = {
1653         .hw = {
1654                 .clk = &uart1_fck,
1655         },
1656         .ops            = &clkhwops_wait,
1657         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1658         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1659         .clkdm_name     = "core_l4_clkdm",
1660 };
1661
1662 DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops);
1663
1664 static struct clk uart1_ick;
1665
1666 static struct clk_hw_omap uart1_ick_hw = {
1667         .hw = {
1668                 .clk = &uart1_ick,
1669         },
1670         .ops            = &clkhwops_iclk_wait,
1671         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1672         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1673         .clkdm_name     = "core_l4_clkdm",
1674 };
1675
1676 DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops);
1677
1678 static struct clk uart2_fck;
1679
1680 static struct clk_hw_omap uart2_fck_hw = {
1681         .hw = {
1682                 .clk = &uart2_fck,
1683         },
1684         .ops            = &clkhwops_wait,
1685         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1686         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1687         .clkdm_name     = "core_l4_clkdm",
1688 };
1689
1690 DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops);
1691
1692 static struct clk uart2_ick;
1693
1694 static struct clk_hw_omap uart2_ick_hw = {
1695         .hw = {
1696                 .clk = &uart2_ick,
1697         },
1698         .ops            = &clkhwops_iclk_wait,
1699         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1700         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1701         .clkdm_name     = "core_l4_clkdm",
1702 };
1703
1704 DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops);
1705
1706 static struct clk uart3_fck;
1707
1708 static struct clk_hw_omap uart3_fck_hw = {
1709         .hw = {
1710                 .clk = &uart3_fck,
1711         },
1712         .ops            = &clkhwops_wait,
1713         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1714         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1715         .clkdm_name     = "core_l4_clkdm",
1716 };
1717
1718 DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops);
1719
1720 static struct clk uart3_ick;
1721
1722 static struct clk_hw_omap uart3_ick_hw = {
1723         .hw = {
1724                 .clk = &uart3_ick,
1725         },
1726         .ops            = &clkhwops_iclk_wait,
1727         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1728         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1729         .clkdm_name     = "core_l4_clkdm",
1730 };
1731
1732 DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops);
1733
1734 static struct clk usb_fck;
1735
1736 static struct clk_hw_omap usb_fck_hw = {
1737         .hw = {
1738                 .clk = &usb_fck,
1739         },
1740         .ops            = &clkhwops_wait,
1741         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1742         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1743         .clkdm_name     = "core_l3_clkdm",
1744 };
1745
1746 DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops);
1747
1748 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1749         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1750         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1751         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1752         { .div = 0 }
1753 };
1754
1755 static const struct clksel usb_l4_ick_clksel[] = {
1756         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1757         { .parent = NULL },
1758 };
1759
1760 static const char *usb_l4_ick_parent_names[] = {
1761         "core_l3_ck",
1762 };
1763
1764 DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel,
1765                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1766                          OMAP24XX_CLKSEL_USB_MASK,
1767                          OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1768                          OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait,
1769                          usb_l4_ick_parent_names, dsp_fck_ops);
1770
1771 static struct clk usbhs_ick;
1772
1773 static struct clk_hw_omap usbhs_ick_hw = {
1774         .hw = {
1775                 .clk = &usbhs_ick,
1776         },
1777         .ops            = &clkhwops_iclk_wait,
1778         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1779         .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
1780         .clkdm_name     = "core_l3_clkdm",
1781 };
1782
1783 DEFINE_STRUCT_CLK(usbhs_ick, gfx_ick_parent_names, aes_ick_ops);
1784
1785 static struct clk virt_prcm_set;
1786
1787 static const char *virt_prcm_set_parent_names[] = {
1788         "mpu_ck",
1789 };
1790
1791 static const struct clk_ops virt_prcm_set_ops = {
1792         .recalc_rate    = &omap2_table_mpu_recalc,
1793         .set_rate       = &omap2_select_table_rate,
1794         .round_rate     = &omap2_round_to_table_rate,
1795 };
1796
1797 DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL);
1798 DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops);
1799
1800 static struct clk wdt1_ick;
1801
1802 static struct clk_hw_omap wdt1_ick_hw = {
1803         .hw = {
1804                 .clk = &wdt1_ick,
1805         },
1806         .ops            = &clkhwops_iclk_wait,
1807         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1808         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
1809         .clkdm_name     = "wkup_clkdm",
1810 };
1811
1812 DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
1813
1814 static struct clk wdt1_osc_ck;
1815
1816 static const struct clk_ops wdt1_osc_ck_ops = {};
1817
1818 DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL);
1819 DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops);
1820
1821 static struct clk wdt4_fck;
1822
1823 static struct clk_hw_omap wdt4_fck_hw = {
1824         .hw = {
1825                 .clk = &wdt4_fck,
1826         },
1827         .ops            = &clkhwops_wait,
1828         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1829         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
1830         .clkdm_name     = "core_l4_clkdm",
1831 };
1832
1833 DEFINE_STRUCT_CLK(wdt4_fck, gpio5_fck_parent_names, aes_ick_ops);
1834
1835 static struct clk wdt4_ick;
1836
1837 static struct clk_hw_omap wdt4_ick_hw = {
1838         .hw = {
1839                 .clk = &wdt4_ick,
1840         },
1841         .ops            = &clkhwops_iclk_wait,
1842         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1843         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
1844         .clkdm_name     = "core_l4_clkdm",
1845 };
1846
1847 DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
1848
1849 /*
1850  * clkdev integration
1851  */
1852
1853 static struct omap_clk omap2430_clks[] = {
1854         /* external root sources */
1855         CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_243X),
1856         CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_243X),
1857         CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X),
1858         CLK("twl",      "fck",          &osc_ck,        CK_243X),
1859         CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X),
1860         CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X),
1861         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_243X),
1862         /* internal analog sources */
1863         CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X),
1864         CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_243X),
1865         CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_243X),
1866         /* internal prcm root sources */
1867         CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X),
1868         CLK(NULL,       "core_ck",      &core_ck,       CK_243X),
1869         CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X),
1870         CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X),
1871         CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X),
1872         CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_243X),
1873         CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_243X),
1874         CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_243X),
1875         CLK(NULL,       "emul_ck",      &emul_ck,       CK_243X),
1876         /* mpu domain clocks */
1877         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_243X),
1878         /* dsp domain clocks */
1879         CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_243X),
1880         CLK(NULL,       "iva2_1_ick",   &iva2_1_ick,    CK_243X),
1881         /* GFX domain clocks */
1882         CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_243X),
1883         CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_243X),
1884         CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_243X),
1885         /* Modem domain clocks */
1886         CLK(NULL,       "mdm_ick",      &mdm_ick,       CK_243X),
1887         CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
1888         /* DSS domain clocks */
1889         CLK("omapdss_dss",      "ick",          &dss_ick,       CK_243X),
1890         CLK(NULL,       "dss_ick",              &dss_ick,       CK_243X),
1891         CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_243X),
1892         CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_243X),
1893         CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_243X),
1894         /* L3 domain clocks */
1895         CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_243X),
1896         CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_243X),
1897         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_243X),
1898         /* L4 domain clocks */
1899         CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X),
1900         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X),
1901         CLK(NULL,       "wu_l4_ick",    &wu_l4_ick,     CK_243X),
1902         /* virtual meta-group clock */
1903         CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X),
1904         /* general l4 interface ck, multi-parent functional clk */
1905         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_243X),
1906         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_243X),
1907         CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_243X),
1908         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_243X),
1909         CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_243X),
1910         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_243X),
1911         CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_243X),
1912         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_243X),
1913         CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_243X),
1914         CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_243X),
1915         CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_243X),
1916         CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_243X),
1917         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_243X),
1918         CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_243X),
1919         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_243X),
1920         CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_243X),
1921         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_243X),
1922         CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_243X),
1923         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_243X),
1924         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_243X),
1925         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_243X),
1926         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_243X),
1927         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X),
1928         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X),
1929         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X),
1930         CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_243X),
1931         CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_243X),
1932         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X),
1933         CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick,    CK_243X),
1934         CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_243X),
1935         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
1936         CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick,    CK_243X),
1937         CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_243X),
1938         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
1939         CLK(NULL,       "mcbsp4_ick",   &mcbsp4_ick,    CK_243X),
1940         CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_243X),
1941         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
1942         CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick,    CK_243X),
1943         CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_243X),
1944         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X),
1945         CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_243X),
1946         CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_243X),
1947         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X),
1948         CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_243X),
1949         CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_243X),
1950         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
1951         CLK(NULL,       "mcspi3_ick",   &mcspi3_ick,    CK_243X),
1952         CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_243X),
1953         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X),
1954         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X),
1955         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_243X),
1956         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_243X),
1957         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_243X),
1958         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_243X),
1959         CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X),
1960         CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X),
1961         CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X),
1962         CLK(NULL,       "mpu_wdt_ick",  &mpu_wdt_ick,   CK_243X),
1963         CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_243X),
1964         CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X),
1965         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X),
1966         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X),
1967         CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
1968         CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X),
1969         CLK(NULL,       "cam_fck",      &cam_fck,       CK_243X),
1970         CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X),
1971         CLK(NULL,       "cam_ick",      &cam_ick,       CK_243X),
1972         CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X),
1973         CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X),
1974         CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X),
1975         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_243X),
1976         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_243X),
1977         CLK(NULL,       "fac_ick",      &fac_ick,       CK_243X),
1978         CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X),
1979         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X),
1980         CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_243X),
1981         CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X),
1982         CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_243X),
1983         CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_243X),
1984         CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_243X),
1985         CLK(NULL,       "i2chs1_fck",   &i2chs1_fck,    CK_243X),
1986         CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_243X),
1987         CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_243X),
1988         CLK(NULL,       "i2chs2_fck",   &i2chs2_fck,    CK_243X),
1989         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X),
1990         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X),
1991         CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_243X),
1992         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_243X),
1993         CLK(NULL,       "des_ick",      &des_ick,       CK_243X),
1994         CLK("omap-sham",        "ick",  &sha_ick,       CK_243X),
1995         CLK("omap_rng", "ick",          &rng_ick,       CK_243X),
1996         CLK(NULL,       "rng_ick",      &rng_ick,       CK_243X),
1997         CLK("omap-aes", "ick",  &aes_ick,       CK_243X),
1998         CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X),
1999         CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X),
2000         CLK("musb-omap2430",    "ick",  &usbhs_ick,     CK_243X),
2001         CLK(NULL,       "usbhs_ick",    &usbhs_ick,     CK_243X),
2002         CLK("omap_hsmmc.0", "ick",      &mmchs1_ick,    CK_243X),
2003         CLK(NULL,       "mmchs1_ick",   &mmchs1_ick,    CK_243X),
2004         CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_243X),
2005         CLK("omap_hsmmc.1", "ick",      &mmchs2_ick,    CK_243X),
2006         CLK(NULL,       "mmchs2_ick",   &mmchs2_ick,    CK_243X),
2007         CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_243X),
2008         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
2009         CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
2010         CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
2011         CLK("omap_hsmmc.0", "mmchsdb_fck",      &mmchsdb1_fck,  CK_243X),
2012         CLK(NULL,        "mmchsdb1_fck",        &mmchsdb1_fck,  CK_243X),
2013         CLK("omap_hsmmc.1", "mmchsdb_fck",      &mmchsdb2_fck,  CK_243X),
2014         CLK(NULL,        "mmchsdb2_fck",        &mmchsdb2_fck,  CK_243X),
2015         CLK(NULL,       "timer_32k_ck",  &func_32k_ck,   CK_243X),
2016         CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_243X),
2017         CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_243X),
2018         CLK(NULL,       "cpufreq_ck",   &virt_prcm_set, CK_243X),
2019 };
2020
2021 static const char *enable_init_clks[] = {
2022         "apll96_ck",
2023         "apll54_ck",
2024         "sync_32k_ick",
2025         "omapctrl_ick",
2026         "gpmc_fck",
2027         "sdrc_ick",
2028 };
2029
2030 /*
2031  * init code
2032  */
2033
2034 int __init omap2430_clk_init(void)
2035 {
2036         struct omap_clk *c;
2037
2038         prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
2039         cpu_mask = RATE_IN_243X;
2040         rate_table = omap2430_rate_table;
2041
2042         omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw);
2043
2044         omap2xxx_clkt_vps_check_bootloader_rates();
2045
2046         for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
2047              c++) {
2048                 clkdev_add(&c->lk);
2049                 if (!__clk_init(NULL, c->lk.clk))
2050                         omap2_init_clk_hw_omap_clocks(c->lk.clk);
2051         }
2052
2053         omap2_clk_disable_autoidle_all();
2054
2055         omap2_clk_enable_init_clocks(enable_init_clks,
2056                                      ARRAY_SIZE(enable_init_clks));
2057
2058         pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
2059                 (clk_get_rate(&sys_ck) / 1000000),
2060                 (clk_get_rate(&sys_ck) / 100000) % 10,
2061                 (clk_get_rate(&dpll_ck) / 1000000),
2062                 (clk_get_rate(&mpu_ck) / 1000000));
2063
2064         return 0;
2065 }