4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/kernel.h>
18 #include <linux/list.h>
19 #include <linux/clk-private.h>
20 #include <linux/clkdev.h>
30 #include "cm-regbits-33xx.h"
33 /* Modulemode control */
34 #define AM33XX_MODULEMODE_HWCTRL_SHIFT 0
35 #define AM33XX_MODULEMODE_SWCTRL_SHIFT 1
37 /*LIST_HEAD(clocks);*/
42 DEFINE_CLK_FIXED_RATE(clk_32768_ck
, CLK_IS_ROOT
, 32768, 0x0);
44 /* On-Chip 32KHz RC OSC */
45 DEFINE_CLK_FIXED_RATE(clk_rc32k_ck
, CLK_IS_ROOT
, 32000, 0x0);
47 /* Crystal input clks */
48 DEFINE_CLK_FIXED_RATE(virt_19200000_ck
, CLK_IS_ROOT
, 19200000, 0x0);
50 DEFINE_CLK_FIXED_RATE(virt_24000000_ck
, CLK_IS_ROOT
, 24000000, 0x0);
52 DEFINE_CLK_FIXED_RATE(virt_25000000_ck
, CLK_IS_ROOT
, 25000000, 0x0);
54 DEFINE_CLK_FIXED_RATE(virt_26000000_ck
, CLK_IS_ROOT
, 26000000, 0x0);
56 /* Oscillator clock */
57 /* 19.2, 24, 25 or 26 MHz */
58 static const char *sys_clkin_ck_parents
[] = {
59 "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
64 * sys_clk in: input to the dpll and also used as funtional clock for,
65 * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
68 DEFINE_CLK_MUX(sys_clkin_ck
, sys_clkin_ck_parents
, NULL
, 0x0,
69 AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS
),
70 AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT
,
71 AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH
,
74 /* External clock - 12 MHz */
75 DEFINE_CLK_FIXED_RATE(tclkin_ck
, CLK_IS_ROOT
, 12000000, 0x0);
77 /* Module clocks and DPLL outputs */
80 static struct dpll_data dpll_core_dd
= {
81 .mult_div1_reg
= AM33XX_CM_CLKSEL_DPLL_CORE
,
82 .clk_bypass
= &sys_clkin_ck
,
83 .clk_ref
= &sys_clkin_ck
,
84 .control_reg
= AM33XX_CM_CLKMODE_DPLL_CORE
,
85 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
86 .idlest_reg
= AM33XX_CM_IDLEST_DPLL_CORE
,
87 .mult_mask
= AM33XX_DPLL_MULT_MASK
,
88 .div1_mask
= AM33XX_DPLL_DIV_MASK
,
89 .enable_mask
= AM33XX_DPLL_EN_MASK
,
90 .idlest_mask
= AM33XX_ST_DPLL_CLK_MASK
,
91 .max_multiplier
= 2047,
96 /* CLKDCOLDO output */
97 static const char *dpll_core_ck_parents
[] = {
101 static struct clk dpll_core_ck
;
103 static const struct clk_ops dpll_core_ck_ops
= {
104 .recalc_rate
= &omap3_dpll_recalc
,
105 .get_parent
= &omap2_init_dpll_parent
,
108 static struct clk_hw_omap dpll_core_ck_hw
= {
110 .clk
= &dpll_core_ck
,
112 .dpll_data
= &dpll_core_dd
,
113 .ops
= &clkhwops_omap3_dpll
,
116 DEFINE_STRUCT_CLK(dpll_core_ck
, dpll_core_ck_parents
, dpll_core_ck_ops
);
118 static const char *dpll_core_x2_ck_parents
[] = {
122 static struct clk dpll_core_x2_ck
;
124 static const struct clk_ops dpll_x2_ck_ops
= {
125 .recalc_rate
= &omap3_clkoutx2_recalc
,
128 static struct clk_hw_omap dpll_core_x2_ck_hw
= {
130 .clk
= &dpll_core_x2_ck
,
132 .flags
= CLOCK_CLKOUTX2
,
135 DEFINE_STRUCT_CLK(dpll_core_x2_ck
, dpll_core_x2_ck_parents
, dpll_x2_ck_ops
);
137 DEFINE_CLK_DIVIDER(dpll_core_m4_ck
, "dpll_core_x2_ck", &dpll_core_x2_ck
,
138 0x0, AM33XX_CM_DIV_M4_DPLL_CORE
,
139 AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT
,
140 AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH
, CLK_DIVIDER_ONE_BASED
,
143 DEFINE_CLK_DIVIDER(dpll_core_m5_ck
, "dpll_core_x2_ck", &dpll_core_x2_ck
,
144 0x0, AM33XX_CM_DIV_M5_DPLL_CORE
,
145 AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT
,
146 AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH
,
147 CLK_DIVIDER_ONE_BASED
, NULL
);
149 DEFINE_CLK_DIVIDER(dpll_core_m6_ck
, "dpll_core_x2_ck", &dpll_core_x2_ck
,
150 0x0, AM33XX_CM_DIV_M6_DPLL_CORE
,
151 AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT
,
152 AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH
,
153 CLK_DIVIDER_ONE_BASED
, NULL
);
157 static struct dpll_data dpll_mpu_dd
= {
158 .mult_div1_reg
= AM33XX_CM_CLKSEL_DPLL_MPU
,
159 .clk_bypass
= &sys_clkin_ck
,
160 .clk_ref
= &sys_clkin_ck
,
161 .control_reg
= AM33XX_CM_CLKMODE_DPLL_MPU
,
162 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
163 .idlest_reg
= AM33XX_CM_IDLEST_DPLL_MPU
,
164 .mult_mask
= AM33XX_DPLL_MULT_MASK
,
165 .div1_mask
= AM33XX_DPLL_DIV_MASK
,
166 .enable_mask
= AM33XX_DPLL_EN_MASK
,
167 .idlest_mask
= AM33XX_ST_DPLL_CLK_MASK
,
168 .max_multiplier
= 2047,
173 /* CLKOUT: fdpll/M2 */
174 static struct clk dpll_mpu_ck
;
176 static const struct clk_ops dpll_mpu_ck_ops
= {
177 .enable
= &omap3_noncore_dpll_enable
,
178 .disable
= &omap3_noncore_dpll_disable
,
179 .recalc_rate
= &omap3_dpll_recalc
,
180 .round_rate
= &omap2_dpll_round_rate
,
181 .set_rate
= &omap3_noncore_dpll_set_rate
,
182 .get_parent
= &omap2_init_dpll_parent
,
185 static struct clk_hw_omap dpll_mpu_ck_hw
= {
189 .dpll_data
= &dpll_mpu_dd
,
190 .ops
= &clkhwops_omap3_dpll
,
193 DEFINE_STRUCT_CLK(dpll_mpu_ck
, dpll_core_ck_parents
, dpll_mpu_ck_ops
);
196 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
199 DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck
, "dpll_mpu_ck", &dpll_mpu_ck
,
200 0x0, AM33XX_CM_DIV_M2_DPLL_MPU
, AM33XX_DPLL_CLKOUT_DIV_SHIFT
,
201 AM33XX_DPLL_CLKOUT_DIV_WIDTH
, CLK_DIVIDER_ONE_BASED
, NULL
);
204 static struct dpll_data dpll_ddr_dd
= {
205 .mult_div1_reg
= AM33XX_CM_CLKSEL_DPLL_DDR
,
206 .clk_bypass
= &sys_clkin_ck
,
207 .clk_ref
= &sys_clkin_ck
,
208 .control_reg
= AM33XX_CM_CLKMODE_DPLL_DDR
,
209 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
210 .idlest_reg
= AM33XX_CM_IDLEST_DPLL_DDR
,
211 .mult_mask
= AM33XX_DPLL_MULT_MASK
,
212 .div1_mask
= AM33XX_DPLL_DIV_MASK
,
213 .enable_mask
= AM33XX_DPLL_EN_MASK
,
214 .idlest_mask
= AM33XX_ST_DPLL_CLK_MASK
,
215 .max_multiplier
= 2047,
220 /* CLKOUT: fdpll/M2 */
221 static struct clk dpll_ddr_ck
;
223 static const struct clk_ops dpll_ddr_ck_ops
= {
224 .recalc_rate
= &omap3_dpll_recalc
,
225 .get_parent
= &omap2_init_dpll_parent
,
226 .round_rate
= &omap2_dpll_round_rate
,
227 .set_rate
= &omap3_noncore_dpll_set_rate
,
230 static struct clk_hw_omap dpll_ddr_ck_hw
= {
234 .dpll_data
= &dpll_ddr_dd
,
235 .ops
= &clkhwops_omap3_dpll
,
238 DEFINE_STRUCT_CLK(dpll_ddr_ck
, dpll_core_ck_parents
, dpll_ddr_ck_ops
);
241 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
244 DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck
, "dpll_ddr_ck", &dpll_ddr_ck
,
245 0x0, AM33XX_CM_DIV_M2_DPLL_DDR
,
246 AM33XX_DPLL_CLKOUT_DIV_SHIFT
, AM33XX_DPLL_CLKOUT_DIV_WIDTH
,
247 CLK_DIVIDER_ONE_BASED
, NULL
);
249 /* emif_fck functional clock */
250 DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck
, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck
,
254 static struct dpll_data dpll_disp_dd
= {
255 .mult_div1_reg
= AM33XX_CM_CLKSEL_DPLL_DISP
,
256 .clk_bypass
= &sys_clkin_ck
,
257 .clk_ref
= &sys_clkin_ck
,
258 .control_reg
= AM33XX_CM_CLKMODE_DPLL_DISP
,
259 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
260 .idlest_reg
= AM33XX_CM_IDLEST_DPLL_DISP
,
261 .mult_mask
= AM33XX_DPLL_MULT_MASK
,
262 .div1_mask
= AM33XX_DPLL_DIV_MASK
,
263 .enable_mask
= AM33XX_DPLL_EN_MASK
,
264 .idlest_mask
= AM33XX_ST_DPLL_CLK_MASK
,
265 .max_multiplier
= 2047,
270 /* CLKOUT: fdpll/M2 */
271 static struct clk dpll_disp_ck
;
273 static struct clk_hw_omap dpll_disp_ck_hw
= {
275 .clk
= &dpll_disp_ck
,
277 .dpll_data
= &dpll_disp_dd
,
278 .ops
= &clkhwops_omap3_dpll
,
281 DEFINE_STRUCT_CLK(dpll_disp_ck
, dpll_core_ck_parents
, dpll_ddr_ck_ops
);
284 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
287 DEFINE_CLK_DIVIDER(dpll_disp_m2_ck
, "dpll_disp_ck", &dpll_disp_ck
,
288 CLK_SET_RATE_PARENT
, AM33XX_CM_DIV_M2_DPLL_DISP
,
289 AM33XX_DPLL_CLKOUT_DIV_SHIFT
, AM33XX_DPLL_CLKOUT_DIV_WIDTH
,
290 CLK_DIVIDER_ONE_BASED
, NULL
);
293 static struct dpll_data dpll_per_dd
= {
294 .mult_div1_reg
= AM33XX_CM_CLKSEL_DPLL_PERIPH
,
295 .clk_bypass
= &sys_clkin_ck
,
296 .clk_ref
= &sys_clkin_ck
,
297 .control_reg
= AM33XX_CM_CLKMODE_DPLL_PER
,
298 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
299 .idlest_reg
= AM33XX_CM_IDLEST_DPLL_PER
,
300 .mult_mask
= AM33XX_DPLL_MULT_PERIPH_MASK
,
301 .div1_mask
= AM33XX_DPLL_PER_DIV_MASK
,
302 .enable_mask
= AM33XX_DPLL_EN_MASK
,
303 .idlest_mask
= AM33XX_ST_DPLL_CLK_MASK
,
304 .max_multiplier
= 2047,
307 .flags
= DPLL_J_TYPE
,
311 static struct clk dpll_per_ck
;
313 static struct clk_hw_omap dpll_per_ck_hw
= {
317 .dpll_data
= &dpll_per_dd
,
318 .ops
= &clkhwops_omap3_dpll
,
321 DEFINE_STRUCT_CLK(dpll_per_ck
, dpll_core_ck_parents
, dpll_ddr_ck_ops
);
323 /* CLKOUT: fdpll/M2 */
324 DEFINE_CLK_DIVIDER(dpll_per_m2_ck
, "dpll_per_ck", &dpll_per_ck
, 0x0,
325 AM33XX_CM_DIV_M2_DPLL_PER
, AM33XX_DPLL_CLKOUT_DIV_SHIFT
,
326 AM33XX_DPLL_CLKOUT_DIV_WIDTH
, CLK_DIVIDER_ONE_BASED
,
329 DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck
, "dpll_per_m2_ck",
330 &dpll_per_m2_ck
, 0x0, 1, 4);
332 DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck
, "dpll_per_m2_ck",
333 &dpll_per_m2_ck
, 0x0, 1, 4);
335 DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck
, "dpll_core_m4_ck",
336 &dpll_core_m4_ck
, 0x0, 1, 2);
338 DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk
, "dpll_core_m4_ck", &dpll_core_m4_ck
, 0x0,
341 DEFINE_CLK_FIXED_FACTOR(clk_24mhz
, "dpll_per_m2_ck", &dpll_per_m2_ck
, 0x0, 1,
345 * Below clock nodes describes clockdomains derived out
348 static const struct clk_ops clk_ops_null
= {
351 static const char *l3_gclk_parents
[] = {
355 static struct clk l3_gclk
;
356 DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk
, NULL
);
357 DEFINE_STRUCT_CLK(l3_gclk
, l3_gclk_parents
, clk_ops_null
);
359 static struct clk l4hs_gclk
;
360 DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk
, NULL
);
361 DEFINE_STRUCT_CLK(l4hs_gclk
, l3_gclk_parents
, clk_ops_null
);
363 static const char *l3s_gclk_parents
[] = {
364 "dpll_core_m4_div2_ck"
367 static struct clk l3s_gclk
;
368 DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk
, NULL
);
369 DEFINE_STRUCT_CLK(l3s_gclk
, l3s_gclk_parents
, clk_ops_null
);
371 static struct clk l4fw_gclk
;
372 DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk
, NULL
);
373 DEFINE_STRUCT_CLK(l4fw_gclk
, l3s_gclk_parents
, clk_ops_null
);
375 static struct clk l4ls_gclk
;
376 DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk
, NULL
);
377 DEFINE_STRUCT_CLK(l4ls_gclk
, l3s_gclk_parents
, clk_ops_null
);
379 static struct clk sysclk_div_ck
;
380 DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck
, NULL
);
381 DEFINE_STRUCT_CLK(sysclk_div_ck
, l3_gclk_parents
, clk_ops_null
);
384 * In order to match the clock domain with hwmod clockdomain entry,
385 * separate clock nodes is required for the modules which are
386 * directly getting their funtioncal clock from sys_clkin.
388 static struct clk adc_tsc_fck
;
389 DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck
, NULL
);
390 DEFINE_STRUCT_CLK(adc_tsc_fck
, dpll_core_ck_parents
, clk_ops_null
);
392 static struct clk dcan0_fck
;
393 DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck
, NULL
);
394 DEFINE_STRUCT_CLK(dcan0_fck
, dpll_core_ck_parents
, clk_ops_null
);
396 static struct clk dcan1_fck
;
397 DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck
, NULL
);
398 DEFINE_STRUCT_CLK(dcan1_fck
, dpll_core_ck_parents
, clk_ops_null
);
400 static struct clk mcasp0_fck
;
401 DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck
, NULL
);
402 DEFINE_STRUCT_CLK(mcasp0_fck
, dpll_core_ck_parents
, clk_ops_null
);
404 static struct clk mcasp1_fck
;
405 DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck
, NULL
);
406 DEFINE_STRUCT_CLK(mcasp1_fck
, dpll_core_ck_parents
, clk_ops_null
);
408 static struct clk smartreflex0_fck
;
409 DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck
, NULL
);
410 DEFINE_STRUCT_CLK(smartreflex0_fck
, dpll_core_ck_parents
, clk_ops_null
);
412 static struct clk smartreflex1_fck
;
413 DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck
, NULL
);
414 DEFINE_STRUCT_CLK(smartreflex1_fck
, dpll_core_ck_parents
, clk_ops_null
);
416 static struct clk sha0_fck
;
417 DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck
, NULL
);
418 DEFINE_STRUCT_CLK(sha0_fck
, dpll_core_ck_parents
, clk_ops_null
);
420 static struct clk aes0_fck
;
421 DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck
, NULL
);
422 DEFINE_STRUCT_CLK(aes0_fck
, dpll_core_ck_parents
, clk_ops_null
);
425 * Modules clock nodes
427 * The following clock leaf nodes are added for the moment because:
429 * - hwmod data is not present for these modules, either hwmod
430 * control is not required or its not populated.
431 * - Driver code is not yet migrated to use hwmod/runtime pm
432 * - Modules outside kernel access (to disable them by default)
437 * - usbotg_fck (its additional clock and not really a modulemode)
440 DEFINE_CLK_GATE(debugss_ick
, "dpll_core_m4_ck", &dpll_core_m4_ck
, 0x0,
441 AM33XX_CM_WKUP_DEBUGSS_CLKCTRL
, AM33XX_MODULEMODE_SWCTRL_SHIFT
,
444 DEFINE_CLK_GATE(mmu_fck
, "dpll_core_m4_ck", &dpll_core_m4_ck
, 0x0,
445 AM33XX_CM_GFX_MMUDATA_CLKCTRL
, AM33XX_MODULEMODE_SWCTRL_SHIFT
,
448 DEFINE_CLK_GATE(cefuse_fck
, "sys_clkin_ck", &sys_clkin_ck
, 0x0,
449 AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL
, AM33XX_MODULEMODE_SWCTRL_SHIFT
,
453 * clkdiv32 is generated from fixed division of 732.4219
455 DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck
, "clk_24mhz", &clk_24mhz
, 0x0, 1, 732);
457 DEFINE_CLK_GATE(clkdiv32k_ick
, "clkdiv32k_ck", &clkdiv32k_ck
, 0x0,
458 AM33XX_CM_PER_CLKDIV32K_CLKCTRL
, AM33XX_MODULEMODE_SWCTRL_SHIFT
,
461 /* "usbotg_fck" is an additional clock and not really a modulemode */
462 DEFINE_CLK_GATE(usbotg_fck
, "dpll_per_ck", &dpll_per_ck
, 0x0,
463 AM33XX_CM_CLKDCOLDO_DPLL_PER
, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT
,
466 DEFINE_CLK_GATE(ieee5000_fck
, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck
,
467 0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL
,
468 AM33XX_MODULEMODE_SWCTRL_SHIFT
, 0x0, NULL
);
471 static const struct clksel timer1_clkmux_sel
[] = {
472 { .parent
= &sys_clkin_ck
, .rates
= div_1_0_rates
},
473 { .parent
= &clkdiv32k_ick
, .rates
= div_1_1_rates
},
474 { .parent
= &tclkin_ck
, .rates
= div_1_2_rates
},
475 { .parent
= &clk_rc32k_ck
, .rates
= div_1_3_rates
},
476 { .parent
= &clk_32768_ck
, .rates
= div_1_4_rates
},
480 static const char *timer1_ck_parents
[] = {
481 "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
485 static struct clk timer1_fck
;
487 static const struct clk_ops timer1_fck_ops
= {
488 .recalc_rate
= &omap2_clksel_recalc
,
489 .get_parent
= &omap2_clksel_find_parent_index
,
490 .set_parent
= &omap2_clksel_set_parent
,
491 .init
= &omap2_init_clk_clkdm
,
494 static struct clk_hw_omap timer1_fck_hw
= {
498 .clkdm_name
= "l4ls_clkdm",
499 .clksel
= timer1_clkmux_sel
,
500 .clksel_reg
= AM33XX_CLKSEL_TIMER1MS_CLK
,
501 .clksel_mask
= AM33XX_CLKSEL_0_2_MASK
,
504 DEFINE_STRUCT_CLK(timer1_fck
, timer1_ck_parents
, timer1_fck_ops
);
506 static const struct clksel timer2_to_7_clk_sel
[] = {
507 { .parent
= &tclkin_ck
, .rates
= div_1_0_rates
},
508 { .parent
= &sys_clkin_ck
, .rates
= div_1_1_rates
},
509 { .parent
= &clkdiv32k_ick
, .rates
= div_1_2_rates
},
513 static const char *timer2_to_7_ck_parents
[] = {
514 "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
517 static struct clk timer2_fck
;
519 static struct clk_hw_omap timer2_fck_hw
= {
523 .clkdm_name
= "l4ls_clkdm",
524 .clksel
= timer2_to_7_clk_sel
,
525 .clksel_reg
= AM33XX_CLKSEL_TIMER2_CLK
,
526 .clksel_mask
= AM33XX_CLKSEL_0_1_MASK
,
529 DEFINE_STRUCT_CLK(timer2_fck
, timer2_to_7_ck_parents
, timer1_fck_ops
);
531 static struct clk timer3_fck
;
533 static struct clk_hw_omap timer3_fck_hw
= {
537 .clkdm_name
= "l4ls_clkdm",
538 .clksel
= timer2_to_7_clk_sel
,
539 .clksel_reg
= AM33XX_CLKSEL_TIMER3_CLK
,
540 .clksel_mask
= AM33XX_CLKSEL_0_1_MASK
,
543 DEFINE_STRUCT_CLK(timer3_fck
, timer2_to_7_ck_parents
, timer1_fck_ops
);
545 static struct clk timer4_fck
;
547 static struct clk_hw_omap timer4_fck_hw
= {
551 .clkdm_name
= "l4ls_clkdm",
552 .clksel
= timer2_to_7_clk_sel
,
553 .clksel_reg
= AM33XX_CLKSEL_TIMER4_CLK
,
554 .clksel_mask
= AM33XX_CLKSEL_0_1_MASK
,
557 DEFINE_STRUCT_CLK(timer4_fck
, timer2_to_7_ck_parents
, timer1_fck_ops
);
559 static struct clk timer5_fck
;
561 static struct clk_hw_omap timer5_fck_hw
= {
565 .clkdm_name
= "l4ls_clkdm",
566 .clksel
= timer2_to_7_clk_sel
,
567 .clksel_reg
= AM33XX_CLKSEL_TIMER5_CLK
,
568 .clksel_mask
= AM33XX_CLKSEL_0_1_MASK
,
571 DEFINE_STRUCT_CLK(timer5_fck
, timer2_to_7_ck_parents
, timer1_fck_ops
);
573 static struct clk timer6_fck
;
575 static struct clk_hw_omap timer6_fck_hw
= {
579 .clkdm_name
= "l4ls_clkdm",
580 .clksel
= timer2_to_7_clk_sel
,
581 .clksel_reg
= AM33XX_CLKSEL_TIMER6_CLK
,
582 .clksel_mask
= AM33XX_CLKSEL_0_1_MASK
,
585 DEFINE_STRUCT_CLK(timer6_fck
, timer2_to_7_ck_parents
, timer1_fck_ops
);
587 static struct clk timer7_fck
;
589 static struct clk_hw_omap timer7_fck_hw
= {
593 .clkdm_name
= "l4ls_clkdm",
594 .clksel
= timer2_to_7_clk_sel
,
595 .clksel_reg
= AM33XX_CLKSEL_TIMER7_CLK
,
596 .clksel_mask
= AM33XX_CLKSEL_0_1_MASK
,
599 DEFINE_STRUCT_CLK(timer7_fck
, timer2_to_7_ck_parents
, timer1_fck_ops
);
601 DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk
,
607 static const struct clk_ops cpsw_fck_ops
= {
608 .recalc_rate
= &omap2_clksel_recalc
,
609 .get_parent
= &omap2_clksel_find_parent_index
,
610 .set_parent
= &omap2_clksel_set_parent
,
613 static const struct clksel cpsw_cpts_rft_clkmux_sel
[] = {
614 { .parent
= &dpll_core_m5_ck
, .rates
= div_1_0_rates
},
615 { .parent
= &dpll_core_m4_ck
, .rates
= div_1_1_rates
},
619 static const char *cpsw_cpts_rft_ck_parents
[] = {
620 "dpll_core_m5_ck", "dpll_core_m4_ck",
623 static struct clk cpsw_cpts_rft_clk
;
625 static struct clk_hw_omap cpsw_cpts_rft_clk_hw
= {
627 .clk
= &cpsw_cpts_rft_clk
,
629 .clkdm_name
= "cpsw_125mhz_clkdm",
630 .clksel
= cpsw_cpts_rft_clkmux_sel
,
631 .clksel_reg
= AM33XX_CM_CPTS_RFT_CLKSEL
,
632 .clksel_mask
= AM33XX_CLKSEL_0_0_MASK
,
635 DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk
, cpsw_cpts_rft_ck_parents
, cpsw_fck_ops
);
639 static const char *gpio0_ck_parents
[] = {
640 "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
643 static const struct clksel gpio0_dbclk_mux_sel
[] = {
644 { .parent
= &clk_rc32k_ck
, .rates
= div_1_0_rates
},
645 { .parent
= &clk_32768_ck
, .rates
= div_1_1_rates
},
646 { .parent
= &clkdiv32k_ick
, .rates
= div_1_2_rates
},
650 static const struct clk_ops gpio_fck_ops
= {
651 .recalc_rate
= &omap2_clksel_recalc
,
652 .get_parent
= &omap2_clksel_find_parent_index
,
653 .set_parent
= &omap2_clksel_set_parent
,
654 .init
= &omap2_init_clk_clkdm
,
657 static struct clk gpio0_dbclk_mux_ck
;
659 static struct clk_hw_omap gpio0_dbclk_mux_ck_hw
= {
661 .clk
= &gpio0_dbclk_mux_ck
,
663 .clkdm_name
= "l4_wkup_clkdm",
664 .clksel
= gpio0_dbclk_mux_sel
,
665 .clksel_reg
= AM33XX_CLKSEL_GPIO0_DBCLK
,
666 .clksel_mask
= AM33XX_CLKSEL_0_1_MASK
,
669 DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck
, gpio0_ck_parents
, gpio_fck_ops
);
671 DEFINE_CLK_GATE(gpio0_dbclk
, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck
, 0x0,
672 AM33XX_CM_WKUP_GPIO0_CLKCTRL
,
673 AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT
, 0x0, NULL
);
675 DEFINE_CLK_GATE(gpio1_dbclk
, "clkdiv32k_ick", &clkdiv32k_ick
, 0x0,
676 AM33XX_CM_PER_GPIO1_CLKCTRL
,
677 AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT
, 0x0, NULL
);
679 DEFINE_CLK_GATE(gpio2_dbclk
, "clkdiv32k_ick", &clkdiv32k_ick
, 0x0,
680 AM33XX_CM_PER_GPIO2_CLKCTRL
,
681 AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT
, 0x0, NULL
);
683 DEFINE_CLK_GATE(gpio3_dbclk
, "clkdiv32k_ick", &clkdiv32k_ick
, 0x0,
684 AM33XX_CM_PER_GPIO3_CLKCTRL
,
685 AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT
, 0x0, NULL
);
688 static const char *pruss_ck_parents
[] = {
689 "l3_gclk", "dpll_disp_m2_ck",
692 static const struct clksel pruss_ocp_clk_mux_sel
[] = {
693 { .parent
= &l3_gclk
, .rates
= div_1_0_rates
},
694 { .parent
= &dpll_disp_m2_ck
, .rates
= div_1_1_rates
},
698 static struct clk pruss_ocp_gclk
;
700 static struct clk_hw_omap pruss_ocp_gclk_hw
= {
702 .clk
= &pruss_ocp_gclk
,
704 .clkdm_name
= "pruss_ocp_clkdm",
705 .clksel
= pruss_ocp_clk_mux_sel
,
706 .clksel_reg
= AM33XX_CLKSEL_PRUSS_OCP_CLK
,
707 .clksel_mask
= AM33XX_CLKSEL_0_0_MASK
,
710 DEFINE_STRUCT_CLK(pruss_ocp_gclk
, pruss_ck_parents
, gpio_fck_ops
);
712 static const char *lcd_ck_parents
[] = {
713 "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
716 static const struct clksel lcd_clk_mux_sel
[] = {
717 { .parent
= &dpll_disp_m2_ck
, .rates
= div_1_0_rates
},
718 { .parent
= &dpll_core_m5_ck
, .rates
= div_1_1_rates
},
719 { .parent
= &dpll_per_m2_ck
, .rates
= div_1_2_rates
},
723 static struct clk lcd_gclk
;
725 static struct clk_hw_omap lcd_gclk_hw
= {
729 .clkdm_name
= "lcdc_clkdm",
730 .clksel
= lcd_clk_mux_sel
,
731 .clksel_reg
= AM33XX_CLKSEL_LCDC_PIXEL_CLK
,
732 .clksel_mask
= AM33XX_CLKSEL_0_1_MASK
,
735 DEFINE_STRUCT_CLK_FLAGS(lcd_gclk
, lcd_ck_parents
,
736 gpio_fck_ops
, CLK_SET_RATE_PARENT
);
738 DEFINE_CLK_FIXED_FACTOR(mmc_clk
, "dpll_per_m2_ck", &dpll_per_m2_ck
, 0x0, 1, 2);
740 static const char *gfx_ck_parents
[] = {
741 "dpll_core_m4_ck", "dpll_per_m2_ck",
744 static const struct clksel gfx_clksel_sel
[] = {
745 { .parent
= &dpll_core_m4_ck
, .rates
= div_1_0_rates
},
746 { .parent
= &dpll_per_m2_ck
, .rates
= div_1_1_rates
},
750 static struct clk gfx_fclk_clksel_ck
;
752 static struct clk_hw_omap gfx_fclk_clksel_ck_hw
= {
754 .clk
= &gfx_fclk_clksel_ck
,
756 .clksel
= gfx_clksel_sel
,
757 .clksel_reg
= AM33XX_CLKSEL_GFX_FCLK
,
758 .clksel_mask
= AM33XX_CLKSEL_GFX_FCLK_MASK
,
761 DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck
, gfx_ck_parents
, gpio_fck_ops
);
763 static const struct clk_div_table div_1_0_2_1_rates
[] = {
764 { .div
= 1, .val
= 0, },
765 { .div
= 2, .val
= 1, },
769 DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck
, "gfx_fclk_clksel_ck",
770 &gfx_fclk_clksel_ck
, 0x0, AM33XX_CLKSEL_GFX_FCLK
,
771 AM33XX_CLKSEL_0_0_SHIFT
, AM33XX_CLKSEL_0_0_WIDTH
,
772 0x0, div_1_0_2_1_rates
, NULL
);
774 static const char *sysclkout_ck_parents
[] = {
775 "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
779 static const struct clksel sysclkout_pre_sel
[] = {
780 { .parent
= &clk_32768_ck
, .rates
= div_1_0_rates
},
781 { .parent
= &l3_gclk
, .rates
= div_1_1_rates
},
782 { .parent
= &dpll_ddr_m2_ck
, .rates
= div_1_2_rates
},
783 { .parent
= &dpll_per_m2_ck
, .rates
= div_1_3_rates
},
784 { .parent
= &lcd_gclk
, .rates
= div_1_4_rates
},
788 static struct clk sysclkout_pre_ck
;
790 static struct clk_hw_omap sysclkout_pre_ck_hw
= {
792 .clk
= &sysclkout_pre_ck
,
794 .clksel
= sysclkout_pre_sel
,
795 .clksel_reg
= AM33XX_CM_CLKOUT_CTRL
,
796 .clksel_mask
= AM33XX_CLKOUT2SOURCE_MASK
,
799 DEFINE_STRUCT_CLK(sysclkout_pre_ck
, sysclkout_ck_parents
, gpio_fck_ops
);
801 /* Divide by 8 clock rates with default clock is 1/1*/
802 static const struct clk_div_table div8_rates
[] = {
803 { .div
= 1, .val
= 0, },
804 { .div
= 2, .val
= 1, },
805 { .div
= 3, .val
= 2, },
806 { .div
= 4, .val
= 3, },
807 { .div
= 5, .val
= 4, },
808 { .div
= 6, .val
= 5, },
809 { .div
= 7, .val
= 6, },
810 { .div
= 8, .val
= 7, },
814 DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck
, "sysclkout_pre_ck", &sysclkout_pre_ck
,
815 0x0, AM33XX_CM_CLKOUT_CTRL
, AM33XX_CLKOUT2DIV_SHIFT
,
816 AM33XX_CLKOUT2DIV_WIDTH
, 0x0, div8_rates
, NULL
);
818 DEFINE_CLK_GATE(clkout2_ck
, "clkout2_div_ck", &clkout2_div_ck
, 0x0,
819 AM33XX_CM_CLKOUT_CTRL
, AM33XX_CLKOUT2EN_SHIFT
, 0x0, NULL
);
821 static const char *wdt_ck_parents
[] = {
822 "clk_rc32k_ck", "clkdiv32k_ick",
825 static const struct clksel wdt_clkmux_sel
[] = {
826 { .parent
= &clk_rc32k_ck
, .rates
= div_1_0_rates
},
827 { .parent
= &clkdiv32k_ick
, .rates
= div_1_1_rates
},
831 static struct clk wdt1_fck
;
833 static struct clk_hw_omap wdt1_fck_hw
= {
837 .clkdm_name
= "l4_wkup_clkdm",
838 .clksel
= wdt_clkmux_sel
,
839 .clksel_reg
= AM33XX_CLKSEL_WDT1_CLK
,
840 .clksel_mask
= AM33XX_CLKSEL_0_1_MASK
,
843 DEFINE_STRUCT_CLK(wdt1_fck
, wdt_ck_parents
, gpio_fck_ops
);
848 static struct omap_clk am33xx_clks
[] = {
849 CLK(NULL
, "clk_32768_ck", &clk_32768_ck
),
850 CLK(NULL
, "clk_rc32k_ck", &clk_rc32k_ck
),
851 CLK(NULL
, "virt_19200000_ck", &virt_19200000_ck
),
852 CLK(NULL
, "virt_24000000_ck", &virt_24000000_ck
),
853 CLK(NULL
, "virt_25000000_ck", &virt_25000000_ck
),
854 CLK(NULL
, "virt_26000000_ck", &virt_26000000_ck
),
855 CLK(NULL
, "sys_clkin_ck", &sys_clkin_ck
),
856 CLK(NULL
, "tclkin_ck", &tclkin_ck
),
857 CLK(NULL
, "dpll_core_ck", &dpll_core_ck
),
858 CLK(NULL
, "dpll_core_x2_ck", &dpll_core_x2_ck
),
859 CLK(NULL
, "dpll_core_m4_ck", &dpll_core_m4_ck
),
860 CLK(NULL
, "dpll_core_m5_ck", &dpll_core_m5_ck
),
861 CLK(NULL
, "dpll_core_m6_ck", &dpll_core_m6_ck
),
862 CLK(NULL
, "dpll_mpu_ck", &dpll_mpu_ck
),
863 CLK("cpu0", NULL
, &dpll_mpu_ck
),
864 CLK(NULL
, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck
),
865 CLK(NULL
, "dpll_ddr_ck", &dpll_ddr_ck
),
866 CLK(NULL
, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck
),
867 CLK(NULL
, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck
),
868 CLK(NULL
, "dpll_disp_ck", &dpll_disp_ck
),
869 CLK(NULL
, "dpll_disp_m2_ck", &dpll_disp_m2_ck
),
870 CLK(NULL
, "dpll_per_ck", &dpll_per_ck
),
871 CLK(NULL
, "dpll_per_m2_ck", &dpll_per_m2_ck
),
872 CLK(NULL
, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck
),
873 CLK(NULL
, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck
),
874 CLK(NULL
, "adc_tsc_fck", &adc_tsc_fck
),
875 CLK(NULL
, "cefuse_fck", &cefuse_fck
),
876 CLK(NULL
, "clkdiv32k_ck", &clkdiv32k_ck
),
877 CLK(NULL
, "clkdiv32k_ick", &clkdiv32k_ick
),
878 CLK(NULL
, "dcan0_fck", &dcan0_fck
),
879 CLK("481cc000.d_can", NULL
, &dcan0_fck
),
880 CLK(NULL
, "dcan1_fck", &dcan1_fck
),
881 CLK("481d0000.d_can", NULL
, &dcan1_fck
),
882 CLK(NULL
, "debugss_ick", &debugss_ick
),
883 CLK(NULL
, "pruss_ocp_gclk", &pruss_ocp_gclk
),
884 CLK(NULL
, "mcasp0_fck", &mcasp0_fck
),
885 CLK(NULL
, "mcasp1_fck", &mcasp1_fck
),
886 CLK(NULL
, "mmu_fck", &mmu_fck
),
887 CLK(NULL
, "smartreflex0_fck", &smartreflex0_fck
),
888 CLK(NULL
, "smartreflex1_fck", &smartreflex1_fck
),
889 CLK(NULL
, "sha0_fck", &sha0_fck
),
890 CLK(NULL
, "aes0_fck", &aes0_fck
),
891 CLK(NULL
, "timer1_fck", &timer1_fck
),
892 CLK(NULL
, "timer2_fck", &timer2_fck
),
893 CLK(NULL
, "timer3_fck", &timer3_fck
),
894 CLK(NULL
, "timer4_fck", &timer4_fck
),
895 CLK(NULL
, "timer5_fck", &timer5_fck
),
896 CLK(NULL
, "timer6_fck", &timer6_fck
),
897 CLK(NULL
, "timer7_fck", &timer7_fck
),
898 CLK(NULL
, "usbotg_fck", &usbotg_fck
),
899 CLK(NULL
, "ieee5000_fck", &ieee5000_fck
),
900 CLK(NULL
, "wdt1_fck", &wdt1_fck
),
901 CLK(NULL
, "l4_rtc_gclk", &l4_rtc_gclk
),
902 CLK(NULL
, "l3_gclk", &l3_gclk
),
903 CLK(NULL
, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck
),
904 CLK(NULL
, "l4hs_gclk", &l4hs_gclk
),
905 CLK(NULL
, "l3s_gclk", &l3s_gclk
),
906 CLK(NULL
, "l4fw_gclk", &l4fw_gclk
),
907 CLK(NULL
, "l4ls_gclk", &l4ls_gclk
),
908 CLK(NULL
, "clk_24mhz", &clk_24mhz
),
909 CLK(NULL
, "sysclk_div_ck", &sysclk_div_ck
),
910 CLK(NULL
, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk
),
911 CLK(NULL
, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk
),
912 CLK(NULL
, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck
),
913 CLK(NULL
, "gpio0_dbclk", &gpio0_dbclk
),
914 CLK(NULL
, "gpio1_dbclk", &gpio1_dbclk
),
915 CLK(NULL
, "gpio2_dbclk", &gpio2_dbclk
),
916 CLK(NULL
, "gpio3_dbclk", &gpio3_dbclk
),
917 CLK(NULL
, "lcd_gclk", &lcd_gclk
),
918 CLK(NULL
, "mmc_clk", &mmc_clk
),
919 CLK(NULL
, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck
),
920 CLK(NULL
, "gfx_fck_div_ck", &gfx_fck_div_ck
),
921 CLK(NULL
, "sysclkout_pre_ck", &sysclkout_pre_ck
),
922 CLK(NULL
, "clkout2_div_ck", &clkout2_div_ck
),
923 CLK(NULL
, "timer_32k_ck", &clkdiv32k_ick
),
924 CLK(NULL
, "timer_sys_ck", &sys_clkin_ck
),
928 static const char *enable_init_clks
[] = {
937 int __init
am33xx_clk_init(void)
940 cpu_mask
= RATE_IN_AM33XX
;
942 omap_clocks_register(am33xx_clks
, ARRAY_SIZE(am33xx_clks
));
944 omap2_clk_disable_autoidle_all();
946 omap2_clk_enable_init_clocks(enable_init_clks
,
947 ARRAY_SIZE(enable_init_clks
));
949 /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
950 * physically present, in such a case HWMOD enabling of
951 * clock would be failure with default parent. And timer
952 * probe thinks clock is already enabled, this leads to
953 * crash upon accessing timer 3 & 6 registers in probe.
954 * Fix by setting parent of both these timers to master
958 clk_set_parent(&timer3_fck
, &sys_clkin_ck
);
959 clk_set_parent(&timer6_fck
, &sys_clkin_ck
);