arch/arm/mach-omap2/cclock44xx_data.c

   1 /*
   2  * OMAP4 Clock data
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  * Mike Turquette (mturquette@ti.com)
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  *
  16  * XXX Some of the ES1 clocks have been removed/changed; once support
  17  * is added for discriminating clocks by ES level, these should be added back
  18  * in.
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/list.h>
  23 #include <linux/clk-private.h>
  24 #include <linux/clkdev.h>
  25 #include <linux/io.h>
  26
  27 #include "soc.h"
  28 #include "iomap.h"
  29 #include "clock.h"
  30 #include "clock44xx.h"
  31 #include "cm1_44xx.h"
  32 #include "cm2_44xx.h"
  33 #include "cm-regbits-44xx.h"
  34 #include "prm44xx.h"
  35 #include "prm-regbits-44xx.h"
  36 #include "control.h"
  37 #include "scrm44xx.h"
  38
  39 /* OMAP4 modulemode control */
  40 #define OMAP4430_MODULEMODE_HWCTRL_SHIFT                0
  41 #define OMAP4430_MODULEMODE_SWCTRL_SHIFT                1
  42
  43 /* Root clocks */
  44
  45 DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
  46
  47 DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
  48
  49 DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
  50                 OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT,
  51                 0x0, NULL);
  52
  53 DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
  54
  55 DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
  56
  57 DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
  58
  59 DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
  60                 OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
  61                 0x0, NULL);
  62
  63 DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
  64
  65 DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
  66
  67 DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
  68
  69 DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
  70
  71 DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
  72
  73 DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
  74
  75 DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
  76
  77 DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
  78
  79 static const char *sys_clkin_ck_parents[] = {
  80         "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck",
  81         "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck",
  82         "virt_38400000_ck",
  83 };
  84
  85 DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
  86                OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT,
  87                OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL);
  88
  89 DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0);
  90
  91 DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0);
  92
  93 DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
  94
  95 DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
  96
  97 DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0);
  98
  99 /* Module clocks and DPLL outputs */
 100
 101 static const char *abe_dpll_bypass_clk_mux_ck_parents[] = {
 102         "sys_clkin_ck", "sys_32k_ck",
 103 };
 104
 105 DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents,
 106                NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT,
 107                OMAP4430_CLKSEL_WIDTH, 0x0, NULL);
 108
 109 DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL,
 110                0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
 111                OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
 112
 113 /* DPLL_ABE */
 114 static struct dpll_data dpll_abe_dd = {
 115         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
 116         .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
 117         .clk_ref        = &abe_dpll_refclk_mux_ck,
 118         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
 119         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 120         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
 121         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
 122         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 123         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 124         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 125         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 126         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 127         .max_multiplier = 2047,
 128         .max_divider    = 128,
 129         .min_divider    = 1,
 130 };
 131
 132
 133 static const char *dpll_abe_ck_parents[] = {
 134         "abe_dpll_refclk_mux_ck",
 135 };
 136
 137 static struct clk dpll_abe_ck;
 138
 139 static const struct clk_ops dpll_abe_ck_ops = {
 140         .enable         = &omap3_noncore_dpll_enable,
 141         .disable        = &omap3_noncore_dpll_disable,
 142         .recalc_rate    = &omap4_dpll_regm4xen_recalc,
 143         .round_rate     = &omap4_dpll_regm4xen_round_rate,
 144         .set_rate       = &omap3_noncore_dpll_set_rate,
 145         .get_parent     = &omap2_init_dpll_parent,
 146 };
 147
 148 static struct clk_hw_omap dpll_abe_ck_hw = {
 149         .hw = {
 150                 .clk = &dpll_abe_ck,
 151         },
 152         .dpll_data      = &dpll_abe_dd,
 153         .ops            = &clkhwops_omap3_dpll,
 154 };
 155
 156 DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
 157
 158 static const char *dpll_abe_x2_ck_parents[] = {
 159         "dpll_abe_ck",
 160 };
 161
 162 static struct clk dpll_abe_x2_ck;
 163
 164 static const struct clk_ops dpll_abe_x2_ck_ops = {
 165         .recalc_rate    = &omap3_clkoutx2_recalc,
 166 };
 167
 168 static struct clk_hw_omap dpll_abe_x2_ck_hw = {
 169         .hw = {
 170                 .clk = &dpll_abe_x2_ck,
 171         },
 172         .flags          = CLOCK_CLKOUTX2,
 173         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 174         .ops            = &clkhwops_omap4_dpllmx,
 175 };
 176
 177 DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
 178
 179 static const struct clk_ops omap_hsdivider_ops = {
 180         .set_rate       = &omap2_clksel_set_rate,
 181         .recalc_rate    = &omap2_clksel_recalc,
 182         .round_rate     = &omap2_clksel_round_rate,
 183 };
 184
 185 DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
 186                           0x0, OMAP4430_CM_DIV_M2_DPLL_ABE,
 187                           OMAP4430_DPLL_CLKOUT_DIV_MASK);
 188
 189 DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
 190                         0x0, 1, 8);
 191
 192 DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
 193                    OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT,
 194                    OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
 195
 196 DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
 197                    OMAP4430_CM1_ABE_AESS_CLKCTRL,
 198                    OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
 199                    OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
 200                    0x0, NULL);
 201
 202 DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
 203                           0x0, OMAP4430_CM_DIV_M3_DPLL_ABE,
 204                           OMAP4430_DPLL_CLKOUTHIF_DIV_MASK);
 205
 206 static const char *core_hsd_byp_clk_mux_ck_parents[] = {
 207         "sys_clkin_ck", "dpll_abe_m3x2_ck",
 208 };
 209
 210 DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL,
 211                0x0, OMAP4430_CM_CLKSEL_DPLL_CORE,
 212                OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
 213                0x0, NULL);
 214
 215 /* DPLL_CORE */
 216 static struct dpll_data dpll_core_dd = {
 217         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
 218         .clk_bypass     = &core_hsd_byp_clk_mux_ck,
 219         .clk_ref        = &sys_clkin_ck,
 220         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
 221         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 222         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
 223         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
 224         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 225         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 226         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 227         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 228         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 229         .max_multiplier = 2047,
 230         .max_divider    = 128,
 231         .min_divider    = 1,
 232 };
 233
 234
 235 static const char *dpll_core_ck_parents[] = {
 236         "sys_clkin_ck",
 237 };
 238
 239 static struct clk dpll_core_ck;
 240
 241 static const struct clk_ops dpll_core_ck_ops = {
 242         .recalc_rate    = &omap3_dpll_recalc,
 243         .get_parent     = &omap2_init_dpll_parent,
 244 };
 245
 246 static struct clk_hw_omap dpll_core_ck_hw = {
 247         .hw = {
 248                 .clk = &dpll_core_ck,
 249         },
 250         .dpll_data      = &dpll_core_dd,
 251         .ops            = &clkhwops_omap3_dpll,
 252 };
 253
 254 DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
 255
 256 static const char *dpll_core_x2_ck_parents[] = {
 257         "dpll_core_ck",
 258 };
 259
 260 static struct clk dpll_core_x2_ck;
 261
 262 static struct clk_hw_omap dpll_core_x2_ck_hw = {
 263         .hw = {
 264                 .clk = &dpll_core_x2_ck,
 265         },
 266 };
 267
 268 DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
 269
 270 DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck",
 271                           &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE,
 272                           OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
 273
 274 DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
 275                           OMAP4430_CM_DIV_M2_DPLL_CORE,
 276                           OMAP4430_DPLL_CLKOUT_DIV_MASK);
 277
 278 DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1,
 279                         2);
 280
 281 DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck",
 282                           &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE,
 283                           OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
 284
 285 DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
 286                    OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
 287                    OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
 288
 289 DEFINE_CLK_OMAP_HSDIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck",
 290                           &dpll_core_m5x2_ck, 0x0, OMAP4430_CM_BYPCLK_DPLL_IVA,
 291                           OMAP4430_CLKSEL_0_1_MASK);
 292
 293 DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
 294                    0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
 295                    OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
 296
 297 DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck",
 298                           &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
 299                           OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
 300
 301 DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
 302                         0x0, 1, 2);
 303
 304 DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
 305                    OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
 306                    OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
 307
 308 static const struct clk_ops dmic_fck_ops = {
 309         .enable         = &omap2_dflt_clk_enable,
 310         .disable        = &omap2_dflt_clk_disable,
 311         .is_enabled     = &omap2_dflt_clk_is_enabled,
 312         .recalc_rate    = &omap2_clksel_recalc,
 313         .get_parent     = &omap2_clksel_find_parent_index,
 314         .set_parent     = &omap2_clksel_set_parent,
 315         .init           = &omap2_init_clk_clkdm,
 316 };
 317
 318 static const char *dpll_core_m3x2_ck_parents[] = {
 319         "dpll_core_x2_ck",
 320 };
 321
 322 static const struct clksel dpll_core_m3x2_div[] = {
 323         { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
 324         { .parent = NULL },
 325 };
 326
 327 /* XXX Missing round_rate, set_rate in ops */
 328 DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
 329                          OMAP4430_CM_DIV_M3_DPLL_CORE,
 330                          OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 331                          OMAP4430_CM_DIV_M3_DPLL_CORE,
 332                          OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
 333                          dpll_core_m3x2_ck_parents, dmic_fck_ops);
 334
 335 DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
 336                           &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
 337                           OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
 338
 339 static const char *iva_hsd_byp_clk_mux_ck_parents[] = {
 340         "sys_clkin_ck", "div_iva_hs_clk",
 341 };
 342
 343 DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL,
 344                0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
 345                OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
 346
 347 /* DPLL_IVA */
 348 static struct dpll_data dpll_iva_dd = {
 349         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
 350         .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
 351         .clk_ref        = &sys_clkin_ck,
 352         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
 353         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 354         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
 355         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
 356         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 357         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 358         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 359         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 360         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 361         .max_multiplier = 2047,
 362         .max_divider    = 128,
 363         .min_divider    = 1,
 364 };
 365
 366 static struct clk dpll_iva_ck;
 367
 368 static const struct clk_ops dpll_ck_ops = {
 369         .enable         = &omap3_noncore_dpll_enable,
 370         .disable        = &omap3_noncore_dpll_disable,
 371         .recalc_rate    = &omap3_dpll_recalc,
 372         .round_rate     = &omap2_dpll_round_rate,
 373         .set_rate       = &omap3_noncore_dpll_set_rate,
 374         .get_parent     = &omap2_init_dpll_parent,
 375 };
 376
 377 static struct clk_hw_omap dpll_iva_ck_hw = {
 378         .hw = {
 379                 .clk = &dpll_iva_ck,
 380         },
 381         .dpll_data      = &dpll_iva_dd,
 382         .ops            = &clkhwops_omap3_dpll,
 383 };
 384
 385 DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_core_ck_parents, dpll_ck_ops);
 386
 387 static const char *dpll_iva_x2_ck_parents[] = {
 388         "dpll_iva_ck",
 389 };
 390
 391 static struct clk dpll_iva_x2_ck;
 392
 393 static struct clk_hw_omap dpll_iva_x2_ck_hw = {
 394         .hw = {
 395                 .clk = &dpll_iva_x2_ck,
 396         },
 397 };
 398
 399 DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
 400
 401 DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
 402                           0x0, OMAP4430_CM_DIV_M4_DPLL_IVA,
 403                           OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
 404
 405 DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
 406                           0x0, OMAP4430_CM_DIV_M5_DPLL_IVA,
 407                           OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
 408
 409 /* DPLL_MPU */
 410 static struct dpll_data dpll_mpu_dd = {
 411         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
 412         .clk_bypass     = &div_mpu_hs_clk,
 413         .clk_ref        = &sys_clkin_ck,
 414         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
 415         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 416         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
 417         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
 418         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 419         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 420         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 421         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 422         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 423         .max_multiplier = 2047,
 424         .max_divider    = 128,
 425         .min_divider    = 1,
 426 };
 427
 428 static struct clk dpll_mpu_ck;
 429
 430 static struct clk_hw_omap dpll_mpu_ck_hw = {
 431         .hw = {
 432                 .clk = &dpll_mpu_ck,
 433         },
 434         .dpll_data      = &dpll_mpu_dd,
 435         .ops            = &clkhwops_omap3_dpll,
 436 };
 437
 438 DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_ck_ops);
 439
 440 DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
 441
 442 DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
 443                           OMAP4430_CM_DIV_M2_DPLL_MPU,
 444                           OMAP4430_DPLL_CLKOUT_DIV_MASK);
 445
 446 DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck",
 447                         &dpll_abe_m3x2_ck, 0x0, 1, 2);
 448
 449 static const char *per_hsd_byp_clk_mux_ck_parents[] = {
 450         "sys_clkin_ck", "per_hs_clk_div_ck",
 451 };
 452
 453 DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL,
 454                0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
 455                OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
 456
 457 /* DPLL_PER */
 458 static struct dpll_data dpll_per_dd = {
 459         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
 460         .clk_bypass     = &per_hsd_byp_clk_mux_ck,
 461         .clk_ref        = &sys_clkin_ck,
 462         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
 463         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 464         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
 465         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
 466         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 467         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 468         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 469         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 470         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 471         .max_multiplier = 2047,
 472         .max_divider    = 128,
 473         .min_divider    = 1,
 474 };
 475
 476
 477 static struct clk dpll_per_ck;
 478
 479 static struct clk_hw_omap dpll_per_ck_hw = {
 480         .hw = {
 481                 .clk = &dpll_per_ck,
 482         },
 483         .dpll_data      = &dpll_per_dd,
 484         .ops            = &clkhwops_omap3_dpll,
 485 };
 486
 487 DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ck_ops);
 488
 489 DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
 490                    OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
 491                    OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
 492
 493 static const char *dpll_per_x2_ck_parents[] = {
 494         "dpll_per_ck",
 495 };
 496
 497 static struct clk dpll_per_x2_ck;
 498
 499 static struct clk_hw_omap dpll_per_x2_ck_hw = {
 500         .hw = {
 501                 .clk = &dpll_per_x2_ck,
 502         },
 503         .flags          = CLOCK_CLKOUTX2,
 504         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 505         .ops            = &clkhwops_omap4_dpllmx,
 506 };
 507
 508 DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
 509
 510 DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
 511                           0x0, OMAP4430_CM_DIV_M2_DPLL_PER,
 512                           OMAP4430_DPLL_CLKOUT_DIV_MASK);
 513
 514 static const char *dpll_per_m3x2_ck_parents[] = {
 515         "dpll_per_x2_ck",
 516 };
 517
 518 static const struct clksel dpll_per_m3x2_div[] = {
 519         { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
 520         { .parent = NULL },
 521 };
 522
 523 /* XXX Missing round_rate, set_rate in ops */
 524 DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
 525                          OMAP4430_CM_DIV_M3_DPLL_PER,
 526                          OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 527                          OMAP4430_CM_DIV_M3_DPLL_PER,
 528                          OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
 529                          dpll_per_m3x2_ck_parents, dmic_fck_ops);
 530
 531 DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
 532                           0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
 533                           OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
 534
 535 DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
 536                           0x0, OMAP4430_CM_DIV_M5_DPLL_PER,
 537                           OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
 538
 539 DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
 540                           0x0, OMAP4430_CM_DIV_M6_DPLL_PER,
 541                           OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
 542
 543 DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
 544                           0x0, OMAP4430_CM_DIV_M7_DPLL_PER,
 545                           OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
 546
 547 DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck",
 548                         &dpll_abe_m3x2_ck, 0x0, 1, 3);
 549
 550 /* DPLL_USB */
 551 static struct dpll_data dpll_usb_dd = {
 552         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
 553         .clk_bypass     = &usb_hs_clk_div_ck,
 554         .flags          = DPLL_J_TYPE,
 555         .clk_ref        = &sys_clkin_ck,
 556         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
 557         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 558         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
 559         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
 560         .mult_mask      = OMAP4430_DPLL_MULT_USB_MASK,
 561         .div1_mask      = OMAP4430_DPLL_DIV_0_7_MASK,
 562         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 563         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 564         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 565         .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
 566         .max_multiplier = 4095,
 567         .max_divider    = 256,
 568         .min_divider    = 1,
 569 };
 570
 571 static struct clk dpll_usb_ck;
 572
 573 static struct clk_hw_omap dpll_usb_ck_hw = {
 574         .hw = {
 575                 .clk = &dpll_usb_ck,
 576         },
 577         .dpll_data      = &dpll_usb_dd,
 578         .ops            = &clkhwops_omap3_dpll,
 579 };
 580
 581 DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_core_ck_parents, dpll_ck_ops);
 582
 583 static const char *dpll_usb_clkdcoldo_ck_parents[] = {
 584         "dpll_usb_ck",
 585 };
 586
 587 static struct clk dpll_usb_clkdcoldo_ck;
 588
 589 static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = {
 590 };
 591
 592 static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = {
 593         .hw = {
 594                 .clk = &dpll_usb_clkdcoldo_ck,
 595         },
 596         .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
 597         .ops            = &clkhwops_omap4_dpllmx,
 598 };
 599
 600 DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents,
 601                   dpll_usb_clkdcoldo_ck_ops);
 602
 603 DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
 604                           OMAP4430_CM_DIV_M2_DPLL_USB,
 605                           OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK);
 606
 607 static const char *ducati_clk_mux_ck_parents[] = {
 608         "div_core_ck", "dpll_per_m6x2_ck",
 609 };
 610
 611 DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0,
 612                OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT,
 613                OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
 614
 615 DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
 616                         0x0, 1, 16);
 617
 618 DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0,
 619                         1, 4);
 620
 621 DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
 622                         0x0, 1, 8);
 623
 624 static const struct clk_div_table func_48m_fclk_rates[] = {
 625         { .div = 4, .val = 0 },
 626         { .div = 8, .val = 1 },
 627         { .div = 0 },
 628 };
 629 DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
 630                          0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
 631                          OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates,
 632                          NULL);
 633
 634 DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
 635                         0x0, 1, 4);
 636
 637 static const struct clk_div_table func_64m_fclk_rates[] = {
 638         { .div = 2, .val = 0 },
 639         { .div = 4, .val = 1 },
 640         { .div = 0 },
 641 };
 642 DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
 643                          0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
 644                          OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates,
 645                          NULL);
 646
 647 static const struct clk_div_table func_96m_fclk_rates[] = {
 648         { .div = 2, .val = 0 },
 649         { .div = 4, .val = 1 },
 650         { .div = 0 },
 651 };
 652 DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
 653                          0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
 654                          OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates,
 655                          NULL);
 656
 657 static const struct clk_div_table init_60m_fclk_rates[] = {
 658         { .div = 1, .val = 0 },
 659         { .div = 8, .val = 1 },
 660         { .div = 0 },
 661 };
 662 DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
 663                          0x0, OMAP4430_CM_CLKSEL_USB_60MHZ,
 664                          OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH,
 665                          0x0, init_60m_fclk_rates, NULL);
 666
 667 DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0,
 668                    OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT,
 669                    OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL);
 670
 671 DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0,
 672                    OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT,
 673                    OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL);
 674
 675 DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
 676                         0x0, 1, 16);
 677
 678 static const char *l4_wkup_clk_mux_ck_parents[] = {
 679         "sys_clkin_ck", "lp_clk_div_ck",
 680 };
 681
 682 DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0,
 683                OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
 684                OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
 685
 686 static const struct clk_div_table ocp_abe_iclk_rates[] = {
 687         { .div = 2, .val = 0 },
 688         { .div = 1, .val = 1 },
 689         { .div = 0 },
 690 };
 691 DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0,
 692                          OMAP4430_CM1_ABE_AESS_CLKCTRL,
 693                          OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
 694                          OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
 695                          0x0, ocp_abe_iclk_rates, NULL);
 696
 697 DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
 698                         0x0, 1, 4);
 699
 700 DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
 701                    OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
 702                    OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL);
 703
 704 DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
 705                    OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
 706                    OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
 707
 708 static struct clk dbgclk_mux_ck;
 709 DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
 710 DEFINE_STRUCT_CLK(dbgclk_mux_ck, dpll_core_ck_parents,
 711                   dpll_usb_clkdcoldo_ck_ops);
 712
 713 /* Leaf clocks controlled by modules */
 714
 715 DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0,
 716                 OMAP4430_CM_L4SEC_AES1_CLKCTRL,
 717                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 718
 719 DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
 720                 OMAP4430_CM_L4SEC_AES2_CLKCTRL,
 721                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 722
 723 DEFINE_CLK_GATE(aess_fck, "aess_fclk", &aess_fclk, 0x0,
 724                 OMAP4430_CM1_ABE_AESS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
 725                 0x0, NULL);
 726
 727 DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
 728                 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
 729                 OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
 730
 731 static const struct clk_div_table div_ts_ck_rates[] = {
 732         { .div = 8, .val = 0 },
 733         { .div = 16, .val = 1 },
 734         { .div = 32, .val = 2 },
 735         { .div = 0 },
 736 };
 737 DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
 738                          0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
 739                          OMAP4430_CLKSEL_24_25_SHIFT,
 740                          OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates,
 741                          NULL);
 742
 743 DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
 744                 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
 745                 OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
 746                 0x0, NULL);
 747
 748 DEFINE_CLK_GATE(des3des_fck, "l4_div_ck", &l4_div_ck, 0x0,
 749                 OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
 750                 OMAP4430_MODULEMODE_SWCTRL_SHIFT,
 751                 0x0, NULL);
 752
 753 static const char *dmic_sync_mux_ck_parents[] = {
 754         "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
 755 };
 756
 757 DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL,
 758                0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL,
 759                OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
 760                OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
 761
 762 static const struct clksel func_dmic_abe_gfclk_sel[] = {
 763         { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
 764         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
 765         { .parent = &slimbus_clk, .rates = div_1_2_rates },
 766         { .parent = NULL },
 767 };
 768
 769 static const char *dmic_fck_parents[] = {
 770         "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
 771 };
 772
 773 /* Merged func_dmic_abe_gfclk into dmic */
 774 static struct clk dmic_fck;
 775
 776 DEFINE_CLK_OMAP_MUX_GATE(dmic_fck, "abe_clkdm", func_dmic_abe_gfclk_sel,
 777                          OMAP4430_CM1_ABE_DMIC_CLKCTRL,
 778                          OMAP4430_CLKSEL_SOURCE_MASK,
 779                          OMAP4430_CM1_ABE_DMIC_CLKCTRL,
 780                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
 781                          dmic_fck_parents, dmic_fck_ops);
 782
 783 DEFINE_CLK_GATE(dsp_fck, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, 0x0,
 784                 OMAP4430_CM_TESLA_TESLA_CLKCTRL,
 785                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 786
 787 DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
 788                 OMAP4430_CM_DSS_DSS_CLKCTRL,
 789                 OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
 790
 791 DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
 792                 OMAP4430_CM_DSS_DSS_CLKCTRL,
 793                 OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
 794
 795 DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
 796                 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
 797                 0x0, NULL);
 798
 799 DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
 800                 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
 801                 0x0, NULL);
 802
 803 DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
 804                 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
 805                 0x0, NULL);
 806
 807 DEFINE_CLK_GATE(efuse_ctrl_cust_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
 808                 OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
 809                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 810
 811 DEFINE_CLK_GATE(emif1_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
 812                 OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
 813                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 814
 815 DEFINE_CLK_GATE(emif2_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
 816                 OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
 817                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 818
 819 DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
 820                    OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
 821                    OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
 822
 823 DEFINE_CLK_GATE(fpka_fck, "l4_div_ck", &l4_div_ck, 0x0,
 824                 OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
 825                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 826
 827 DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
 828                 OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
 829                 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
 830
 831 DEFINE_CLK_GATE(gpio1_ick, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 0x0,
 832                 OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
 833                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 834
 835 DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
 836                 OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
 837                 0x0, NULL);
 838
 839 DEFINE_CLK_GATE(gpio2_ick, "l4_div_ck", &l4_div_ck, 0x0,
 840                 OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
 841                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 842
 843 DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
 844                 OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
 845                 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
 846
 847 DEFINE_CLK_GATE(gpio3_ick, "l4_div_ck", &l4_div_ck, 0x0,
 848                 OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
 849                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 850
 851 DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
 852                 OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
 853                 0x0, NULL);
 854
 855 DEFINE_CLK_GATE(gpio4_ick, "l4_div_ck", &l4_div_ck, 0x0,
 856                 OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
 857                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 858
 859 DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
 860                 OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
 861                 0x0, NULL);
 862
 863 DEFINE_CLK_GATE(gpio5_ick, "l4_div_ck", &l4_div_ck, 0x0,
 864                 OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
 865                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 866
 867 DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
 868                 OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
 869                 0x0, NULL);
 870
 871 DEFINE_CLK_GATE(gpio6_ick, "l4_div_ck", &l4_div_ck, 0x0,
 872                 OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
 873                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 874
 875 DEFINE_CLK_GATE(gpmc_ick, "l3_div_ck", &l3_div_ck, 0x0,
 876                 OMAP4430_CM_L3_2_GPMC_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
 877                 0x0, NULL);
 878
 879 static const struct clksel sgx_clk_mux_sel[] = {
 880         { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
 881         { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
 882         { .parent = NULL },
 883 };
 884
 885 static const char *gpu_fck_parents[] = {
 886         "dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
 887 };
 888
 889 /* Merged sgx_clk_mux into gpu */
 890 DEFINE_CLK_OMAP_MUX_GATE(gpu_fck, "l3_gfx_clkdm", sgx_clk_mux_sel,
 891                          OMAP4430_CM_GFX_GFX_CLKCTRL,
 892                          OMAP4430_CLKSEL_SGX_FCLK_MASK,
 893                          OMAP4430_CM_GFX_GFX_CLKCTRL,
 894                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
 895                          gpu_fck_parents, dmic_fck_ops);
 896
 897 DEFINE_CLK_GATE(hdq1w_fck, "func_12m_fclk", &func_12m_fclk, 0x0,
 898                 OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
 899                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 900
 901 DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
 902                    OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
 903                    OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
 904                    NULL);
 905
 906 DEFINE_CLK_GATE(i2c1_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
 907                 OMAP4430_CM_L4PER_I2C1_CLKCTRL,
 908                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 909
 910 DEFINE_CLK_GATE(i2c2_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
 911                 OMAP4430_CM_L4PER_I2C2_CLKCTRL,
 912                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 913
 914 DEFINE_CLK_GATE(i2c3_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
 915                 OMAP4430_CM_L4PER_I2C3_CLKCTRL,
 916                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 917
 918 DEFINE_CLK_GATE(i2c4_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
 919                 OMAP4430_CM_L4PER_I2C4_CLKCTRL,
 920                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 921
 922 DEFINE_CLK_GATE(ipu_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
 923                 OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
 924                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 925
 926 DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
 927                 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
 928                 0x0, NULL);
 929
 930 DEFINE_CLK_GATE(iss_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
 931                 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
 932                 0x0, NULL);
 933
 934 DEFINE_CLK_GATE(iva_fck, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
 935                 OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
 936                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 937
 938 DEFINE_CLK_GATE(kbd_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
 939                 OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
 940                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 941
 942 static struct clk l3_instr_ick;
 943
 944 static const char *l3_instr_ick_parent_names[] = {
 945         "l3_div_ck",
 946 };
 947
 948 static const struct clk_ops l3_instr_ick_ops = {
 949         .enable         = &omap2_dflt_clk_enable,
 950         .disable        = &omap2_dflt_clk_disable,
 951         .is_enabled     = &omap2_dflt_clk_is_enabled,
 952         .init           = &omap2_init_clk_clkdm,
 953 };
 954
 955 static struct clk_hw_omap l3_instr_ick_hw = {
 956         .hw = {
 957                 .clk = &l3_instr_ick,
 958         },
 959         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
 960         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
 961         .clkdm_name     = "l3_instr_clkdm",
 962 };
 963
 964 DEFINE_STRUCT_CLK(l3_instr_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
 965
 966 static struct clk l3_main_3_ick;
 967 static struct clk_hw_omap l3_main_3_ick_hw = {
 968         .hw = {
 969                 .clk = &l3_main_3_ick,
 970         },
 971         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
 972         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
 973         .clkdm_name     = "l3_instr_clkdm",
 974 };
 975
 976 DEFINE_STRUCT_CLK(l3_main_3_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
 977
 978 DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
 979                OMAP4430_CM1_ABE_MCASP_CLKCTRL,
 980                OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
 981                OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
 982
 983 static const struct clksel func_mcasp_abe_gfclk_sel[] = {
 984         { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
 985         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
 986         { .parent = &slimbus_clk, .rates = div_1_2_rates },
 987         { .parent = NULL },
 988 };
 989
 990 static const char *mcasp_fck_parents[] = {
 991         "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
 992 };
 993
 994 /* Merged func_mcasp_abe_gfclk into mcasp */
 995 DEFINE_CLK_OMAP_MUX_GATE(mcasp_fck, "abe_clkdm", func_mcasp_abe_gfclk_sel,
 996                          OMAP4430_CM1_ABE_MCASP_CLKCTRL,
 997                          OMAP4430_CLKSEL_SOURCE_MASK,
 998                          OMAP4430_CM1_ABE_MCASP_CLKCTRL,
 999                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1000                          mcasp_fck_parents, dmic_fck_ops);
1001
1002 DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1003                OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1004                OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
1005                OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
1006
1007 static const struct clksel func_mcbsp1_gfclk_sel[] = {
1008         { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1009         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1010         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1011         { .parent = NULL },
1012 };
1013
1014 static const char *mcbsp1_fck_parents[] = {
1015         "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1016 };
1017
1018 /* Merged func_mcbsp1_gfclk into mcbsp1 */
1019 DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "abe_clkdm", func_mcbsp1_gfclk_sel,
1020                          OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1021                          OMAP4430_CLKSEL_SOURCE_MASK,
1022                          OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1023                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1024                          mcbsp1_fck_parents, dmic_fck_ops);
1025
1026 DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1027                OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1028                OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
1029                OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
1030
1031 static const struct clksel func_mcbsp2_gfclk_sel[] = {
1032         { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1033         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1034         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1035         { .parent = NULL },
1036 };
1037
1038 static const char *mcbsp2_fck_parents[] = {
1039         "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1040 };
1041
1042 /* Merged func_mcbsp2_gfclk into mcbsp2 */
1043 DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "abe_clkdm", func_mcbsp2_gfclk_sel,
1044                          OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1045                          OMAP4430_CLKSEL_SOURCE_MASK,
1046                          OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1047                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1048                          mcbsp2_fck_parents, dmic_fck_ops);
1049
1050 DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1051                OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1052                OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
1053                OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
1054
1055 static const struct clksel func_mcbsp3_gfclk_sel[] = {
1056         { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1057         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1058         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1059         { .parent = NULL },
1060 };
1061
1062 static const char *mcbsp3_fck_parents[] = {
1063         "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1064 };
1065
1066 /* Merged func_mcbsp3_gfclk into mcbsp3 */
1067 DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "abe_clkdm", func_mcbsp3_gfclk_sel,
1068                          OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1069                          OMAP4430_CLKSEL_SOURCE_MASK,
1070                          OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1071                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1072                          mcbsp3_fck_parents, dmic_fck_ops);
1073
1074 static const char *mcbsp4_sync_mux_ck_parents[] = {
1075         "func_96m_fclk", "per_abe_nc_fclk",
1076 };
1077
1078 DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0,
1079                OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1080                OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
1081                OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
1082
1083 static const struct clksel per_mcbsp4_gfclk_sel[] = {
1084         { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1085         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1086         { .parent = NULL },
1087 };
1088
1089 static const char *mcbsp4_fck_parents[] = {
1090         "mcbsp4_sync_mux_ck", "pad_clks_ck",
1091 };
1092
1093 /* Merged per_mcbsp4_gfclk into mcbsp4 */
1094 DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
1095                          OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1096                          OMAP4430_CLKSEL_SOURCE_24_24_MASK,
1097                          OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1098                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1099                          mcbsp4_fck_parents, dmic_fck_ops);
1100
1101 DEFINE_CLK_GATE(mcpdm_fck, "pad_clks_ck", &pad_clks_ck, 0x0,
1102                 OMAP4430_CM1_ABE_PDM_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1103                 0x0, NULL);
1104
1105 DEFINE_CLK_GATE(mcspi1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1106                 OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
1107                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1108
1109 DEFINE_CLK_GATE(mcspi2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1110                 OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
1111                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1112
1113 DEFINE_CLK_GATE(mcspi3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1114                 OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
1115                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1116
1117 DEFINE_CLK_GATE(mcspi4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1118                 OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
1119                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1120
1121 static const struct clksel hsmmc1_fclk_sel[] = {
1122         { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1123         { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1124         { .parent = NULL },
1125 };
1126
1127 static const char *mmc1_fck_parents[] = {
1128         "func_64m_fclk", "func_96m_fclk",
1129 };
1130
1131 /* Merged hsmmc1_fclk into mmc1 */
1132 DEFINE_CLK_OMAP_MUX_GATE(mmc1_fck, "l3_init_clkdm", hsmmc1_fclk_sel,
1133                          OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
1134                          OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
1135                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1136                          mmc1_fck_parents, dmic_fck_ops);
1137
1138 /* Merged hsmmc2_fclk into mmc2 */
1139 DEFINE_CLK_OMAP_MUX_GATE(mmc2_fck, "l3_init_clkdm", hsmmc1_fclk_sel,
1140                          OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
1141                          OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
1142                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1143                          mmc1_fck_parents, dmic_fck_ops);
1144
1145 DEFINE_CLK_GATE(mmc3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1146                 OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
1147                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1148
1149 DEFINE_CLK_GATE(mmc4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1150                 OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
1151                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1152
1153 DEFINE_CLK_GATE(mmc5_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1154                 OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
1155                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1156
1157 DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
1158                 OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1159                 OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
1160
1161 DEFINE_CLK_GATE(ocp2scp_usb_phy_ick, "l4_div_ck", &l4_div_ck, 0x0,
1162                 OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1163                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1164
1165 static struct clk ocp_wp_noc_ick;
1166
1167 static struct clk_hw_omap ocp_wp_noc_ick_hw = {
1168         .hw = {
1169                 .clk = &ocp_wp_noc_ick,
1170         },
1171         .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
1172         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1173         .clkdm_name     = "l3_instr_clkdm",
1174 };
1175
1176 DEFINE_STRUCT_CLK(ocp_wp_noc_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
1177
1178 DEFINE_CLK_GATE(rng_ick, "l4_div_ck", &l4_div_ck, 0x0,
1179                 OMAP4430_CM_L4SEC_RNG_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1180                 0x0, NULL);
1181
1182 DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
1183                 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
1184                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1185
1186 DEFINE_CLK_GATE(sl2if_ick, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
1187                 OMAP4430_CM_IVAHD_SL2_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1188                 0x0, NULL);
1189
1190 DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
1191                 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1192                 OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
1193
1194 DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0,
1195                 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1196                 OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL);
1197
1198 DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0,
1199                 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1200                 OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL);
1201
1202 DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
1203                 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1204                 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
1205
1206 DEFINE_CLK_GATE(slimbus1_fck, "ocp_abe_iclk", &ocp_abe_iclk, 0x0,
1207                 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1208                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1209
1210 DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
1211                 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1212                 OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
1213
1214 DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0,
1215                 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1216                 OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL);
1217
1218 DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
1219                 &pad_slimbus_core_clks_ck, 0x0,
1220                 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1221                 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
1222
1223 DEFINE_CLK_GATE(slimbus2_fck, "l4_div_ck", &l4_div_ck, 0x0,
1224                 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1225                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1226
1227 DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1228                 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
1229                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1230
1231 DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1232                 0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
1233                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1234
1235 DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1236                 0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
1237                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1238
1239 static const struct clksel dmt1_clk_mux_sel[] = {
1240         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1241         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1242         { .parent = NULL },
1243 };
1244
1245 /* Merged dmt1_clk_mux into timer1 */
1246 DEFINE_CLK_OMAP_MUX_GATE(timer1_fck, "l4_wkup_clkdm", dmt1_clk_mux_sel,
1247                          OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
1248                          OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1249                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1250                          abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1251
1252 /* Merged cm2_dm10_mux into timer10 */
1253 DEFINE_CLK_OMAP_MUX_GATE(timer10_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1254                          OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1255                          OMAP4430_CLKSEL_MASK,
1256                          OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1257                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1258                          abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1259
1260 /* Merged cm2_dm11_mux into timer11 */
1261 DEFINE_CLK_OMAP_MUX_GATE(timer11_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1262                          OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1263                          OMAP4430_CLKSEL_MASK,
1264                          OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1265                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1266                          abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1267
1268 /* Merged cm2_dm2_mux into timer2 */
1269 DEFINE_CLK_OMAP_MUX_GATE(timer2_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1270                          OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1271                          OMAP4430_CLKSEL_MASK,
1272                          OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1273                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1274                          abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1275
1276 /* Merged cm2_dm3_mux into timer3 */
1277 DEFINE_CLK_OMAP_MUX_GATE(timer3_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1278                          OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1279                          OMAP4430_CLKSEL_MASK,
1280                          OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1281                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1282                          abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1283
1284 /* Merged cm2_dm4_mux into timer4 */
1285 DEFINE_CLK_OMAP_MUX_GATE(timer4_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1286                          OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1287                          OMAP4430_CLKSEL_MASK,
1288                          OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1289                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1290                          abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1291
1292 static const struct clksel timer5_sync_mux_sel[] = {
1293         { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
1294         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1295         { .parent = NULL },
1296 };
1297
1298 static const char *timer5_fck_parents[] = {
1299         "syc_clk_div_ck", "sys_32k_ck",
1300 };
1301
1302 /* Merged timer5_sync_mux into timer5 */
1303 DEFINE_CLK_OMAP_MUX_GATE(timer5_fck, "abe_clkdm", timer5_sync_mux_sel,
1304                          OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
1305                          OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1306                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1307                          timer5_fck_parents, dmic_fck_ops);
1308
1309 /* Merged timer6_sync_mux into timer6 */
1310 DEFINE_CLK_OMAP_MUX_GATE(timer6_fck, "abe_clkdm", timer5_sync_mux_sel,
1311                          OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
1312                          OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1313                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1314                          timer5_fck_parents, dmic_fck_ops);
1315
1316 /* Merged timer7_sync_mux into timer7 */
1317 DEFINE_CLK_OMAP_MUX_GATE(timer7_fck, "abe_clkdm", timer5_sync_mux_sel,
1318                          OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
1319                          OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1320                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1321                          timer5_fck_parents, dmic_fck_ops);
1322
1323 /* Merged timer8_sync_mux into timer8 */
1324 DEFINE_CLK_OMAP_MUX_GATE(timer8_fck, "abe_clkdm", timer5_sync_mux_sel,
1325                          OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
1326                          OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1327                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1328                          timer5_fck_parents, dmic_fck_ops);
1329
1330 /* Merged cm2_dm9_mux into timer9 */
1331 DEFINE_CLK_OMAP_MUX_GATE(timer9_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1332                          OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1333                          OMAP4430_CLKSEL_MASK,
1334                          OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1335                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1336                          abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1337
1338 DEFINE_CLK_GATE(uart1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1339                 OMAP4430_CM_L4PER_UART1_CLKCTRL,
1340                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1341
1342 DEFINE_CLK_GATE(uart2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1343                 OMAP4430_CM_L4PER_UART2_CLKCTRL,
1344                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1345
1346 DEFINE_CLK_GATE(uart3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1347                 OMAP4430_CM_L4PER_UART3_CLKCTRL,
1348                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1349
1350 DEFINE_CLK_GATE(uart4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1351                 OMAP4430_CM_L4PER_UART4_CLKCTRL,
1352                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1353
1354 static struct clk usb_host_fs_fck;
1355
1356 static const char *usb_host_fs_fck_parent_names[] = {
1357         "func_48mc_fclk",
1358 };
1359
1360 static const struct clk_ops usb_host_fs_fck_ops = {
1361         .enable         = &omap2_dflt_clk_enable,
1362         .disable        = &omap2_dflt_clk_disable,
1363         .is_enabled     = &omap2_dflt_clk_is_enabled,
1364 };
1365
1366 static struct clk_hw_omap usb_host_fs_fck_hw = {
1367         .hw = {
1368                 .clk = &usb_host_fs_fck,
1369         },
1370         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
1371         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1372         .clkdm_name     = "l3_init_clkdm",
1373 };
1374
1375 DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names,
1376                   usb_host_fs_fck_ops);
1377
1378 static const char *utmi_p1_gfclk_parents[] = {
1379         "init_60m_fclk", "xclk60mhsp1_ck",
1380 };
1381
1382 DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
1383                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1384                OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH,
1385                0x0, NULL);
1386
1387 DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0,
1388                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1389                 OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL);
1390
1391 static const char *utmi_p2_gfclk_parents[] = {
1392         "init_60m_fclk", "xclk60mhsp2_ck",
1393 };
1394
1395 DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
1396                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1397                OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH,
1398                0x0, NULL);
1399
1400 DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0,
1401                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1402                 OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL);
1403
1404 DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1405                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1406                 OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL);
1407
1408 DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck",
1409                 &dpll_usb_m2_ck, 0x0,
1410                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1411                 OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL);
1412
1413 DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk",
1414                 &init_60m_fclk, 0x0,
1415                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1416                 OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL);
1417
1418 DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk",
1419                 &init_60m_fclk, 0x0,
1420                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1421                 OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL);
1422
1423 DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck",
1424                 &dpll_usb_m2_ck, 0x0,
1425                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1426                 OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL);
1427
1428 DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
1429                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1430                 OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL);
1431
1432 DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0,
1433                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1434                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1435
1436 static const char *otg_60m_gfclk_parents[] = {
1437         "utmi_phy_clkout_ck", "xclk60motg_ck",
1438 };
1439
1440 DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0,
1441                OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT,
1442                OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL);
1443
1444 DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0,
1445                 OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
1446                 OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL);
1447
1448 DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0,
1449                 OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
1450                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1451
1452 DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
1453                 OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
1454                 OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
1455
1456 DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1457                 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1458                 OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL);
1459
1460 DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1461                 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1462                 OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL);
1463
1464 DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1465                 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1466                 OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL);
1467
1468 DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0,
1469                 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1470                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1471
1472 static const struct clk_div_table usim_ck_rates[] = {
1473         { .div = 14, .val = 0 },
1474         { .div = 18, .val = 1 },
1475         { .div = 0 },
1476 };
1477 DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
1478                          OMAP4430_CM_WKUP_USIM_CLKCTRL,
1479                          OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH,
1480                          0x0, usim_ck_rates, NULL);
1481
1482 DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
1483                 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
1484                 0x0, NULL);
1485
1486 DEFINE_CLK_GATE(usim_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1487                 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1488                 0x0, NULL);
1489
1490 DEFINE_CLK_GATE(wd_timer2_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1491                 OMAP4430_CM_WKUP_WDT2_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1492                 0x0, NULL);
1493
1494 DEFINE_CLK_GATE(wd_timer3_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1495                 OMAP4430_CM1_ABE_WDT3_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1496                 0x0, NULL);
1497
1498 /* Remaining optional clocks */
1499 static const char *pmd_stm_clock_mux_ck_parents[] = {
1500         "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
1501 };
1502
1503 DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
1504                OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT,
1505                OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL);
1506
1507 DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
1508                OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1509                OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT,
1510                OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL);
1511
1512 DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck",
1513                    &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1514                    OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT,
1515                    OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
1516                    NULL);
1517
1518 static const char *trace_clk_div_ck_parents[] = {
1519         "pmd_trace_clk_mux_ck",
1520 };
1521
1522 static const struct clksel trace_clk_div_div[] = {
1523         { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
1524         { .parent = NULL },
1525 };
1526
1527 static struct clk trace_clk_div_ck;
1528
1529 static const struct clk_ops trace_clk_div_ck_ops = {
1530         .recalc_rate    = &omap2_clksel_recalc,
1531         .set_rate       = &omap2_clksel_set_rate,
1532         .round_rate     = &omap2_clksel_round_rate,
1533         .init           = &omap2_init_clk_clkdm,
1534         .enable         = &omap2_clkops_enable_clkdm,
1535         .disable        = &omap2_clkops_disable_clkdm,
1536 };
1537
1538 static struct clk_hw_omap trace_clk_div_ck_hw = {
1539         .hw = {
1540                 .clk = &trace_clk_div_ck,
1541         },
1542         .clkdm_name     = "emu_sys_clkdm",
1543         .clksel         = trace_clk_div_div,
1544         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1545         .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
1546 };
1547
1548 DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents,
1549                   trace_clk_div_ck_ops);
1550
1551 /* SCRM aux clk nodes */
1552
1553 static const struct clksel auxclk_src_sel[] = {
1554         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1555         { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
1556         { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
1557         { .parent = NULL },
1558 };
1559
1560 static const char *auxclk_src_ck_parents[] = {
1561         "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
1562 };
1563
1564 static const struct clk_ops auxclk_src_ck_ops = {
1565         .enable         = &omap2_dflt_clk_enable,
1566         .disable        = &omap2_dflt_clk_disable,
1567         .is_enabled     = &omap2_dflt_clk_is_enabled,
1568         .recalc_rate    = &omap2_clksel_recalc,
1569         .get_parent     = &omap2_clksel_find_parent_index,
1570 };
1571
1572 DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
1573                          OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK,
1574                          OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL,
1575                          auxclk_src_ck_parents, auxclk_src_ck_ops);
1576
1577 DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
1578                    OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1579                    0x0, NULL);
1580
1581 DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
1582                          OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK,
1583                          OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL,
1584                          auxclk_src_ck_parents, auxclk_src_ck_ops);
1585
1586 DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
1587                    OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1588                    0x0, NULL);
1589
1590 DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
1591                          OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK,
1592                          OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL,
1593                          auxclk_src_ck_parents, auxclk_src_ck_ops);
1594
1595 DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
1596                    OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1597                    0x0, NULL);
1598
1599 DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
1600                          OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK,
1601                          OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL,
1602                          auxclk_src_ck_parents, auxclk_src_ck_ops);
1603
1604 DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
1605                    OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1606                    0x0, NULL);
1607
1608 DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
1609                          OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK,
1610                          OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL,
1611                          auxclk_src_ck_parents, auxclk_src_ck_ops);
1612
1613 DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0,
1614                    OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1615                    0x0, NULL);
1616
1617 DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
1618                          OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK,
1619                          OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL,
1620                          auxclk_src_ck_parents, auxclk_src_ck_ops);
1621
1622 DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0,
1623                    OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1624                    0x0, NULL);
1625
1626 static const char *auxclkreq_ck_parents[] = {
1627         "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
1628         "auxclk5_ck",
1629 };
1630
1631 DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
1632                OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1633                0x0, NULL);
1634
1635 DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
1636                OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1637                0x0, NULL);
1638
1639 DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
1640                OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1641                0x0, NULL);
1642
1643 DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
1644                OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1645                0x0, NULL);
1646
1647 DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0,
1648                OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1649                0x0, NULL);
1650
1651 DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
1652                OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1653                0x0, NULL);
1654
1655 /*
1656  * clkdev
1657  */
1658
1659 static struct omap_clk omap44xx_clks[] = {
1660         CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
1661         CLK(NULL,       "pad_clks_src_ck",              &pad_clks_src_ck,       CK_443X),
1662         CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
1663         CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
1664         CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
1665         CLK(NULL,       "slimbus_src_clk",              &slimbus_src_clk,       CK_443X),
1666         CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
1667         CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
1668         CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
1669         CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
1670         CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
1671         CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
1672         CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
1673         CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
1674         CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
1675         CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
1676         CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
1677         CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
1678         CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
1679         CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
1680         CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
1681         CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
1682         CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
1683         CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
1684         CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
1685         CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
1686         CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
1687         CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
1688         CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
1689         CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
1690         CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
1691         CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
1692         CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
1693         CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
1694         CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
1695         CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
1696         CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
1697         CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
1698         CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
1699         CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
1700         CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
1701         CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
1702         CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
1703         CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
1704         CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
1705         CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
1706         CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
1707         CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
1708         CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
1709         CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
1710         CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
1711         CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
1712         CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
1713         CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
1714         CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
1715         CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
1716         CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
1717         CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
1718         CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
1719         CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
1720         CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
1721         CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
1722         CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
1723         CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
1724         CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
1725         CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
1726         CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
1727         CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
1728         CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
1729         CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
1730         CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
1731         CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
1732         CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
1733         CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
1734         CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
1735         CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
1736         CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
1737         CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
1738         CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
1739         CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
1740         CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
1741         CLK("smp_twd",  NULL,                           &mpu_periphclk, CK_443X),
1742         CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
1743         CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
1744         CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
1745         CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
1746         CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
1747         CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
1748         CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
1749         CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
1750         CLK(NULL,       "div_ts_ck",                    &div_ts_ck,     CK_446X),
1751         CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk,       CK_446X),
1752         CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
1753         CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
1754         CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
1755         CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
1756         CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
1757         CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
1758         CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
1759         CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
1760         CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
1761         CLK("omapdss_dss",      "ick",                  &dss_fck,       CK_443X),
1762         CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
1763         CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
1764         CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
1765         CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
1766         CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
1767         CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
1768         CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
1769         CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
1770         CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
1771         CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
1772         CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
1773         CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
1774         CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
1775         CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
1776         CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
1777         CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
1778         CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
1779         CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
1780         CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
1781         CLK(NULL,       "hdq1w_fck",                    &hdq1w_fck,     CK_443X),
1782         CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
1783         CLK(NULL,       "i2c1_fck",                     &i2c1_fck,      CK_443X),
1784         CLK(NULL,       "i2c2_fck",                     &i2c2_fck,      CK_443X),
1785         CLK(NULL,       "i2c3_fck",                     &i2c3_fck,      CK_443X),
1786         CLK(NULL,       "i2c4_fck",                     &i2c4_fck,      CK_443X),
1787         CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
1788         CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
1789         CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
1790         CLK(NULL,       "iva_fck",                      &iva_fck,       CK_443X),
1791         CLK(NULL,       "kbd_fck",                      &kbd_fck,       CK_443X),
1792         CLK(NULL,       "l3_instr_ick",                 &l3_instr_ick,  CK_443X),
1793         CLK(NULL,       "l3_main_3_ick",                &l3_main_3_ick, CK_443X),
1794         CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
1795         CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
1796         CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
1797         CLK(NULL,       "mcbsp1_fck",                   &mcbsp1_fck,    CK_443X),
1798         CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
1799         CLK(NULL,       "mcbsp2_fck",                   &mcbsp2_fck,    CK_443X),
1800         CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
1801         CLK(NULL,       "mcbsp3_fck",                   &mcbsp3_fck,    CK_443X),
1802         CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
1803         CLK(NULL,       "mcbsp4_fck",                   &mcbsp4_fck,    CK_443X),
1804         CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
1805         CLK(NULL,       "mcspi1_fck",                   &mcspi1_fck,    CK_443X),
1806         CLK(NULL,       "mcspi2_fck",                   &mcspi2_fck,    CK_443X),
1807         CLK(NULL,       "mcspi3_fck",                   &mcspi3_fck,    CK_443X),
1808         CLK(NULL,       "mcspi4_fck",                   &mcspi4_fck,    CK_443X),
1809         CLK(NULL,       "mmc1_fck",                     &mmc1_fck,      CK_443X),
1810         CLK(NULL,       "mmc2_fck",                     &mmc2_fck,      CK_443X),
1811         CLK(NULL,       "mmc3_fck",                     &mmc3_fck,      CK_443X),
1812         CLK(NULL,       "mmc4_fck",                     &mmc4_fck,      CK_443X),
1813         CLK(NULL,       "mmc5_fck",                     &mmc5_fck,      CK_443X),
1814         CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
1815         CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
1816         CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
1817         CLK(NULL,       "rng_ick",                      &rng_ick,       CK_443X),
1818         CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
1819         CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
1820         CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
1821         CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
1822         CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
1823         CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
1824         CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
1825         CLK(NULL,       "slimbus1_fck",                 &slimbus1_fck,  CK_443X),
1826         CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
1827         CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
1828         CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
1829         CLK(NULL,       "slimbus2_fck",                 &slimbus2_fck,  CK_443X),
1830         CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
1831         CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
1832         CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
1833         CLK(NULL,       "timer1_fck",                   &timer1_fck,    CK_443X),
1834         CLK(NULL,       "timer10_fck",                  &timer10_fck,   CK_443X),
1835         CLK(NULL,       "timer11_fck",                  &timer11_fck,   CK_443X),
1836         CLK(NULL,       "timer2_fck",                   &timer2_fck,    CK_443X),
1837         CLK(NULL,       "timer3_fck",                   &timer3_fck,    CK_443X),
1838         CLK(NULL,       "timer4_fck",                   &timer4_fck,    CK_443X),
1839         CLK(NULL,       "timer5_fck",                   &timer5_fck,    CK_443X),
1840         CLK(NULL,       "timer6_fck",                   &timer6_fck,    CK_443X),
1841         CLK(NULL,       "timer7_fck",                   &timer7_fck,    CK_443X),
1842         CLK(NULL,       "timer8_fck",                   &timer8_fck,    CK_443X),
1843         CLK(NULL,       "timer9_fck",                   &timer9_fck,    CK_443X),
1844         CLK(NULL,       "uart1_fck",                    &uart1_fck,     CK_443X),
1845         CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
1846         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
1847         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
1848         CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
1849         CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck,       CK_443X),
1850         CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
1851         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
1852         CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
1853         CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
1854         CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
1855         CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
1856         CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
1857         CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
1858         CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
1859         CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
1860         CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
1861         CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck,       CK_443X),
1862         CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
1863         CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
1864         CLK(NULL,       "usb_otg_hs_ick",               &usb_otg_hs_ick,        CK_443X),
1865         CLK("musb-omap2430",    "ick",                  &usb_otg_hs_ick,        CK_443X),
1866         CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
1867         CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
1868         CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
1869         CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
1870         CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
1871         CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
1872         CLK("usbhs_tll",        "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
1873         CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
1874         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
1875         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
1876         CLK(NULL,       "wd_timer2_fck",                &wd_timer2_fck, CK_443X),
1877         CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
1878         CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
1879         CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
1880         CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
1881         CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
1882         CLK(NULL,       "auxclk0_src_ck",               &auxclk0_src_ck,        CK_443X),
1883         CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
1884         CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
1885         CLK(NULL,       "auxclk1_src_ck",               &auxclk1_src_ck,        CK_443X),
1886         CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
1887         CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
1888         CLK(NULL,       "auxclk2_src_ck",               &auxclk2_src_ck,        CK_443X),
1889         CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
1890         CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
1891         CLK(NULL,       "auxclk3_src_ck",               &auxclk3_src_ck,        CK_443X),
1892         CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
1893         CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
1894         CLK(NULL,       "auxclk4_src_ck",               &auxclk4_src_ck,        CK_443X),
1895         CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
1896         CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
1897         CLK(NULL,       "auxclk5_src_ck",               &auxclk5_src_ck,        CK_443X),
1898         CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
1899         CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
1900         CLK("omap-gpmc",        "fck",                  &dummy_ck,      CK_443X),
1901         CLK("omap_i2c.1",       "ick",                  &dummy_ck,      CK_443X),
1902         CLK("omap_i2c.2",       "ick",                  &dummy_ck,      CK_443X),
1903         CLK("omap_i2c.3",       "ick",                  &dummy_ck,      CK_443X),
1904         CLK("omap_i2c.4",       "ick",                  &dummy_ck,      CK_443X),
1905         CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
1906         CLK("omap_hsmmc.0",     "ick",                  &dummy_ck,      CK_443X),
1907         CLK("omap_hsmmc.1",     "ick",                  &dummy_ck,      CK_443X),
1908         CLK("omap_hsmmc.2",     "ick",                  &dummy_ck,      CK_443X),
1909         CLK("omap_hsmmc.3",     "ick",                  &dummy_ck,      CK_443X),
1910         CLK("omap_hsmmc.4",     "ick",                  &dummy_ck,      CK_443X),
1911         CLK("omap-mcbsp.1",     "ick",                  &dummy_ck,      CK_443X),
1912         CLK("omap-mcbsp.2",     "ick",                  &dummy_ck,      CK_443X),
1913         CLK("omap-mcbsp.3",     "ick",                  &dummy_ck,      CK_443X),
1914         CLK("omap-mcbsp.4",     "ick",                  &dummy_ck,      CK_443X),
1915         CLK("omap2_mcspi.1",    "ick",                  &dummy_ck,      CK_443X),
1916         CLK("omap2_mcspi.2",    "ick",                  &dummy_ck,      CK_443X),
1917         CLK("omap2_mcspi.3",    "ick",                  &dummy_ck,      CK_443X),
1918         CLK("omap2_mcspi.4",    "ick",                  &dummy_ck,      CK_443X),
1919         CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
1920         CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
1921         CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
1922         CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
1923         CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck,              CK_443X),
1924         CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck,      CK_443X),
1925         CLK("usbhs_tll",        "usbtll_fck",           &dummy_ck,      CK_443X),
1926         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
1927         CLK(NULL,       "timer_32k_ck", &sys_32k_ck,    CK_443X),
1928         /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
1929         CLK("omap_timer.1",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1930         CLK("omap_timer.2",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1931         CLK("omap_timer.3",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1932         CLK("omap_timer.4",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1933         CLK("omap_timer.9",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1934         CLK("omap_timer.10",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1935         CLK("omap_timer.11",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1936         CLK("omap_timer.5",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1937         CLK("omap_timer.6",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1938         CLK("omap_timer.7",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1939         CLK("omap_timer.8",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1940         CLK("4a318000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1941         CLK("48032000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1942         CLK("48034000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1943         CLK("48036000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1944         CLK("4803e000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1945         CLK("48086000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1946         CLK("48088000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1947         CLK("40138000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1948         CLK("4013a000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1949         CLK("4013c000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1950         CLK("4013e000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1951         CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck,   CK_443X),
1952 };
1953
1954 static const char *enable_init_clks[] = {
1955         "emif1_fck",
1956         "emif2_fck",
1957         "gpmc_ick",
1958         "l3_instr_ick",
1959         "l3_main_3_ick",
1960         "ocp_wp_noc_ick",
1961 };
1962
1963 int __init omap4xxx_clk_init(void)
1964 {
1965         u32 cpu_clkflg;
1966         struct omap_clk *c;
1967
1968         if (cpu_is_omap443x()) {
1969                 cpu_mask = RATE_IN_4430;
1970                 cpu_clkflg = CK_443X;
1971         } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
1972                 cpu_mask = RATE_IN_4460 | RATE_IN_4430;
1973                 cpu_clkflg = CK_446X | CK_443X;
1974
1975                 if (cpu_is_omap447x())
1976                         pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
1977         } else {
1978                 return 0;
1979         }
1980
1981         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
1982                                                                         c++) {
1983                 if (c->cpu & cpu_clkflg) {
1984                         clkdev_add(&c->lk);
1985                         if (!__clk_init(NULL, c->lk.clk))
1986                                 omap2_init_clk_hw_omap_clocks(c->lk.clk);
1987                 }
1988         }
1989
1990         omap2_clk_disable_autoidle_all();
1991
1992         omap2_clk_enable_init_clocks(enable_init_clks,
1993                                      ARRAY_SIZE(enable_init_clks));
1994
1995         return 0;
1996 }