arch/arm/mach-omap2/clkt2xxx_apll.c

   1 /*
   2  * OMAP2xxx APLL clock control functions
   3  *
   4  * Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2010 Nokia Corporation
   6  *
   7  * Contacts:
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Paul Walmsley
  10  *
  11  * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
  12  * Gordon McNutt and RidgeRun, Inc.
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18 #undef DEBUG
  19
  20 #include <linux/kernel.h>
  21 #include <linux/clk.h>
  22 #include <linux/io.h>
  23
  24 #include <plat/prcm.h>
  25
  26 #include "clock.h"
  27 #include "clock2xxx.h"
  28 #include "cm2xxx_3xxx.h"
  29 #include "cm-regbits-24xx.h"
  30
  31 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
  32 #define EN_APLL_STOPPED                 0
  33 #define EN_APLL_LOCKED                  3
  34
  35 /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
  36 #define APLLS_CLKIN_19_2MHZ             0
  37 #define APLLS_CLKIN_13MHZ               2
  38 #define APLLS_CLKIN_12MHZ               3
  39
  40 void __iomem *cm_idlest_pll;
  41
  42 /* Private functions */
  43
  44 /* Enable an APLL if off */
  45 static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
  46 {
  47         u32 cval, apll_mask;
  48
  49         apll_mask = EN_APLL_LOCKED << clk->enable_bit;
  50
  51         cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
  52
  53         if ((cval & apll_mask) == apll_mask)
  54                 return 0;   /* apll already enabled */
  55
  56         cval &= ~apll_mask;
  57         cval |= apll_mask;
  58         omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
  59
  60         omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
  61                              OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));
  62
  63         /*
  64          * REVISIT: Should we return an error code if omap2_wait_clock_ready()
  65          * fails?
  66          */
  67         return 0;
  68 }
  69
  70 static int omap2_clk_apll96_enable(struct clk *clk)
  71 {
  72         return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL_MASK);
  73 }
  74
  75 static int omap2_clk_apll54_enable(struct clk *clk)
  76 {
  77         return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK);
  78 }
  79
  80 static void _apll96_allow_idle(struct clk *clk)
  81 {
  82         omap2xxx_cm_set_apll96_auto_low_power_stop();
  83 }
  84
  85 static void _apll96_deny_idle(struct clk *clk)
  86 {
  87         omap2xxx_cm_set_apll96_disable_autoidle();
  88 }
  89
  90 static void _apll54_allow_idle(struct clk *clk)
  91 {
  92         omap2xxx_cm_set_apll54_auto_low_power_stop();
  93 }
  94
  95 static void _apll54_deny_idle(struct clk *clk)
  96 {
  97         omap2xxx_cm_set_apll54_disable_autoidle();
  98 }
  99
 100 /* Stop APLL */
 101 static void omap2_clk_apll_disable(struct clk *clk)
 102 {
 103         u32 cval;
 104
 105         cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 106         cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
 107         omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 108 }
 109
 110 /* Public data */
 111
 112 const struct clkops clkops_apll96 = {
 113         .enable         = omap2_clk_apll96_enable,
 114         .disable        = omap2_clk_apll_disable,
 115         .allow_idle     = _apll96_allow_idle,
 116         .deny_idle      = _apll96_deny_idle,
 117 };
 118
 119 const struct clkops clkops_apll54 = {
 120         .enable         = omap2_clk_apll54_enable,
 121         .disable        = omap2_clk_apll_disable,
 122         .allow_idle     = _apll54_allow_idle,
 123         .deny_idle      = _apll54_deny_idle,
 124 };
 125
 126 /* Public functions */
 127
 128 u32 omap2xxx_get_apll_clkin(void)
 129 {
 130         u32 aplls, srate = 0;
 131
 132         aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
 133         aplls &= OMAP24XX_APLLS_CLKIN_MASK;
 134         aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
 135
 136         if (aplls == APLLS_CLKIN_19_2MHZ)
 137                 srate = 19200000;
 138         else if (aplls == APLLS_CLKIN_13MHZ)
 139                 srate = 13000000;
 140         else if (aplls == APLLS_CLKIN_12MHZ)
 141                 srate = 12000000;
 142
 143         return srate;
 144 }
 145