2 * DPLL + CORE_CLK composite clock functions
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12 * Gordon McNutt and RidgeRun, Inc.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
18 * XXX The DPLL and CORE clocks should be split into two separate clock
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
25 #include <linux/clk.h>
29 #include "clock2xxx.h"
31 #include "cm2xxx_3xxx.h"
32 #include "cm-regbits-24xx.h"
36 /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
39 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
40 * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
42 * Returns the CORE_CLK rate. CORE_CLK can have one of three rate
43 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
44 * (the latter is unusual). This currently should be called with
45 * struct clk *dpll_ck, which is a composite clock of dpll_ck and
48 unsigned long omap2xxx_clk_get_core_rate(struct clk
*clk
)
53 core_clk
= omap2_get_dpll_rate(clk
);
55 v
= omap2_cm_read_mod_reg(PLL_MOD
, CM_CLKSEL2
);
56 v
&= OMAP24XX_CORE_CLK_SRC_MASK
;
58 if (v
== CORE_CLK_SRC_32K
)
67 * Uses the current prcm set to tell if a rate is valid.
68 * You can go slower, but not faster within a given rate set.
70 static long omap2_dpllcore_round_rate(unsigned long target_rate
)
72 u32 high
, low
, core_clk_src
;
74 core_clk_src
= omap2_cm_read_mod_reg(PLL_MOD
, CM_CLKSEL2
);
75 core_clk_src
&= OMAP24XX_CORE_CLK_SRC_MASK
;
77 if (core_clk_src
== CORE_CLK_SRC_DPLL
) { /* DPLL clockout */
78 high
= curr_prcm_set
->dpll_speed
* 2;
79 low
= curr_prcm_set
->dpll_speed
;
80 } else { /* DPLL clockout x 2 */
81 high
= curr_prcm_set
->dpll_speed
;
82 low
= curr_prcm_set
->dpll_speed
/ 2;
85 #ifdef DOWN_VARIABLE_DPLL
86 if (target_rate
> high
)
91 if (target_rate
> low
)
99 unsigned long omap2_dpllcore_recalc(struct clk
*clk
)
101 return omap2xxx_clk_get_core_rate(clk
);
104 int omap2_reprogram_dpllcore(struct clk
*clk
, unsigned long rate
)
106 u32 cur_rate
, low
, mult
, div
, valid_rate
, done_rate
;
108 struct prcm_config tmpset
;
109 const struct dpll_data
*dd
;
111 cur_rate
= omap2xxx_clk_get_core_rate(dclk
);
112 mult
= omap2_cm_read_mod_reg(PLL_MOD
, CM_CLKSEL2
);
113 mult
&= OMAP24XX_CORE_CLK_SRC_MASK
;
115 if ((rate
== (cur_rate
/ 2)) && (mult
== 2)) {
116 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL
, 1);
117 } else if ((rate
== (cur_rate
* 2)) && (mult
== 1)) {
118 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2
, 1);
119 } else if (rate
!= cur_rate
) {
120 valid_rate
= omap2_dpllcore_round_rate(rate
);
121 if (valid_rate
!= rate
)
125 low
= curr_prcm_set
->dpll_speed
;
127 low
= curr_prcm_set
->dpll_speed
/ 2;
133 tmpset
.cm_clksel1_pll
= __raw_readl(dd
->mult_div1_reg
);
134 tmpset
.cm_clksel1_pll
&= ~(dd
->mult_mask
|
136 div
= ((curr_prcm_set
->xtal_speed
/ 1000000) - 1);
137 tmpset
.cm_clksel2_pll
= omap2_cm_read_mod_reg(PLL_MOD
, CM_CLKSEL2
);
138 tmpset
.cm_clksel2_pll
&= ~OMAP24XX_CORE_CLK_SRC_MASK
;
140 tmpset
.cm_clksel2_pll
|= CORE_CLK_SRC_DPLL_X2
;
141 mult
= ((rate
/ 2) / 1000000);
142 done_rate
= CORE_CLK_SRC_DPLL_X2
;
144 tmpset
.cm_clksel2_pll
|= CORE_CLK_SRC_DPLL
;
145 mult
= (rate
/ 1000000);
146 done_rate
= CORE_CLK_SRC_DPLL
;
148 tmpset
.cm_clksel1_pll
|= (div
<< __ffs(dd
->mult_mask
));
149 tmpset
.cm_clksel1_pll
|= (mult
<< __ffs(dd
->div1_mask
));
152 tmpset
.base_sdrc_rfr
= SDRC_RFR_CTRL_BYPASS
;
154 if (rate
== curr_prcm_set
->xtal_speed
) /* If asking for 1-1 */
157 /* For omap2xxx_sdrc_init_params() */
158 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2
, 1);
160 /* Force dll lock mode */
161 omap2_set_prcm(tmpset
.cm_clksel1_pll
, tmpset
.base_sdrc_rfr
,
164 /* Errata: ret dll entry state */
165 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
166 omap2xxx_sdrc_reprogram(done_rate
, 0);