2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <asm/bitops.h>
28 #include <asm/arch/clock.h>
29 #include <asm/arch/sram.h>
30 #include <asm/arch/cpu.h>
31 #include <asm/div64.h>
37 #include "prm-regbits-24xx.h"
39 #include "cm-regbits-24xx.h"
40 #include "cm-regbits-34xx.h"
42 #define MAX_CLOCK_ENABLE_WAIT 100000
44 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
45 #define DPLL_MIN_MULTIPLIER 1
46 #define DPLL_MIN_DIVIDER 1
48 /* Possible error results from _dpll_test_mult */
49 #define DPLL_MULT_UNDERFLOW (1 << 0)
52 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
53 * The higher the scale factor, the greater the risk of arithmetic overflow,
54 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
55 * must be a power of DPLL_SCALE_BASE.
57 #define DPLL_SCALE_FACTOR 64
58 #define DPLL_SCALE_BASE 2
59 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
60 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
64 /*-------------------------------------------------------------------------
65 * Omap2 specific clock functions
66 *-------------------------------------------------------------------------*/
69 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
70 * @clk: OMAP clock struct ptr to use
72 * Given a pointer to a source-selectable struct clk, read the hardware
73 * register and determine what its parent is currently set to. Update the
74 * clk->parent field with the appropriate clk ptr.
76 void omap2_init_clksel_parent(struct clk
*clk
)
78 const struct clksel
*clks
;
79 const struct clksel_rate
*clkr
;
85 r
= __raw_readl(clk
->clksel_reg
) & clk
->clksel_mask
;
86 r
>>= __ffs(clk
->clksel_mask
);
88 for (clks
= clk
->clksel
; clks
->parent
&& !found
; clks
++) {
89 for (clkr
= clks
->rates
; clkr
->div
&& !found
; clkr
++) {
90 if ((clkr
->flags
& cpu_mask
) && (clkr
->val
== r
)) {
91 if (clk
->parent
!= clks
->parent
) {
92 pr_debug("clock: inited %s parent "
94 clk
->name
, clks
->parent
->name
,
96 clk
->parent
->name
: "NULL"));
97 clk
->parent
= clks
->parent
;
105 printk(KERN_ERR
"clock: init parent: could not find "
106 "regval %0x for clock %s\n", r
, clk
->name
);
111 /* Returns the DPLL rate */
112 u32
omap2_get_dpll_rate(struct clk
*clk
)
115 u32 dpll_mult
, dpll_div
, dpll
;
116 struct dpll_data
*dd
;
119 /* REVISIT: What do we return on error? */
123 dpll
= __raw_readl(dd
->mult_div1_reg
);
124 dpll_mult
= dpll
& dd
->mult_mask
;
125 dpll_mult
>>= __ffs(dd
->mult_mask
);
126 dpll_div
= dpll
& dd
->div1_mask
;
127 dpll_div
>>= __ffs(dd
->div1_mask
);
129 dpll_clk
= (long long)clk
->parent
->rate
* dpll_mult
;
130 do_div(dpll_clk
, dpll_div
+ 1);
136 * Used for clocks that have the same value as the parent clock,
137 * divided by some factor
139 void omap2_fixed_divisor_recalc(struct clk
*clk
)
141 WARN_ON(!clk
->fixed_div
);
143 clk
->rate
= clk
->parent
->rate
/ clk
->fixed_div
;
145 if (clk
->flags
& RATE_PROPAGATES
)
150 * omap2_wait_clock_ready - wait for clock to enable
151 * @reg: physical address of clock IDLEST register
152 * @mask: value to mask against to determine if the clock is active
153 * @name: name of the clock (for printk)
155 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
156 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
158 int omap2_wait_clock_ready(void __iomem
*reg
, u32 mask
, const char *name
)
164 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
165 * 34xx reverses this, just to keep us on our toes
167 if (cpu_mask
& (RATE_IN_242X
| RATE_IN_243X
)) {
169 } else if (cpu_mask
& RATE_IN_343X
) {
174 while (((__raw_readl(reg
) & mask
) != ena
) &&
175 (i
++ < MAX_CLOCK_ENABLE_WAIT
)) {
179 if (i
< MAX_CLOCK_ENABLE_WAIT
)
180 pr_debug("Clock %s stable after %d loops\n", name
, i
);
182 printk(KERN_ERR
"Clock %s didn't enable in %d tries\n",
183 name
, MAX_CLOCK_ENABLE_WAIT
);
186 return (i
< MAX_CLOCK_ENABLE_WAIT
) ? 1 : 0;
191 * Note: We don't need special code here for INVERT_ENABLE
192 * for the time being since INVERT_ENABLE only applies to clocks enabled by
195 static void omap2_clk_wait_ready(struct clk
*clk
)
197 void __iomem
*reg
, *other_reg
, *st_reg
;
201 * REVISIT: This code is pretty ugly. It would be nice to generalize
202 * it and pull it into struct clk itself somehow.
204 reg
= clk
->enable_reg
;
205 if ((((u32
)reg
& 0xff) >= CM_FCLKEN1
) &&
206 (((u32
)reg
& 0xff) <= OMAP24XX_CM_FCLKEN2
))
207 other_reg
= (void __iomem
*)(((u32
)reg
& ~0xf0) | 0x10); /* CM_ICLKEN* */
208 else if ((((u32
)reg
& 0xff) >= CM_ICLKEN1
) &&
209 (((u32
)reg
& 0xff) <= OMAP24XX_CM_ICLKEN4
))
210 other_reg
= (void __iomem
*)(((u32
)reg
& ~0xf0) | 0x00); /* CM_FCLKEN* */
214 /* REVISIT: What are the appropriate exclusions for 34XX? */
215 /* No check for DSS or cam clocks */
216 if (cpu_is_omap24xx() && ((u32
)reg
& 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
217 if (clk
->enable_bit
== OMAP24XX_EN_DSS2_SHIFT
||
218 clk
->enable_bit
== OMAP24XX_EN_DSS1_SHIFT
||
219 clk
->enable_bit
== OMAP24XX_EN_CAM_SHIFT
)
223 /* REVISIT: What are the appropriate exclusions for 34XX? */
224 /* OMAP3: ignore DSS-mod clocks */
225 if (cpu_is_omap34xx() &&
226 (((u32
)reg
& ~0xff) == (u32
)OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, 0) ||
227 ((((u32
)reg
& ~0xff) == (u32
)OMAP_CM_REGADDR(CORE_MOD
, 0)) &&
228 clk
->enable_bit
== OMAP3430_EN_SSI_SHIFT
)))
231 /* Check if both functional and interface clocks
233 bit
= 1 << clk
->enable_bit
;
234 if (!(__raw_readl(other_reg
) & bit
))
236 st_reg
= (void __iomem
*)(((u32
)other_reg
& ~0xf0) | 0x20); /* CM_IDLEST* */
238 omap2_wait_clock_ready(st_reg
, bit
, clk
->name
);
241 /* Enables clock without considering parent dependencies or use count
242 * REVISIT: Maybe change this to use clk->enable like on omap1?
244 int _omap2_clk_enable(struct clk
*clk
)
248 if (clk
->flags
& (ALWAYS_ENABLED
| PARENT_CONTROLS_CLOCK
))
252 return clk
->enable(clk
);
254 if (unlikely(clk
->enable_reg
== 0)) {
255 printk(KERN_ERR
"clock.c: Enable for %s without enable code\n",
257 return 0; /* REVISIT: -EINVAL */
260 regval32
= __raw_readl(clk
->enable_reg
);
261 if (clk
->flags
& INVERT_ENABLE
)
262 regval32
&= ~(1 << clk
->enable_bit
);
264 regval32
|= (1 << clk
->enable_bit
);
265 __raw_writel(regval32
, clk
->enable_reg
);
268 omap2_clk_wait_ready(clk
);
273 /* Disables clock without considering parent dependencies or use count */
274 void _omap2_clk_disable(struct clk
*clk
)
278 if (clk
->flags
& (ALWAYS_ENABLED
| PARENT_CONTROLS_CLOCK
))
286 if (clk
->enable_reg
== 0) {
288 * 'Independent' here refers to a clock which is not
289 * controlled by its parent.
291 printk(KERN_ERR
"clock: clk_disable called on independent "
292 "clock %s which has no enable_reg\n", clk
->name
);
296 regval32
= __raw_readl(clk
->enable_reg
);
297 if (clk
->flags
& INVERT_ENABLE
)
298 regval32
|= (1 << clk
->enable_bit
);
300 regval32
&= ~(1 << clk
->enable_bit
);
301 __raw_writel(regval32
, clk
->enable_reg
);
305 void omap2_clk_disable(struct clk
*clk
)
307 if (clk
->usecount
> 0 && !(--clk
->usecount
)) {
308 _omap2_clk_disable(clk
);
309 if (likely((u32
)clk
->parent
))
310 omap2_clk_disable(clk
->parent
);
314 int omap2_clk_enable(struct clk
*clk
)
318 if (clk
->usecount
++ == 0) {
319 if (likely((u32
)clk
->parent
))
320 ret
= omap2_clk_enable(clk
->parent
);
322 if (unlikely(ret
!= 0)) {
327 ret
= _omap2_clk_enable(clk
);
329 if (unlikely(ret
!= 0) && clk
->parent
) {
330 omap2_clk_disable(clk
->parent
);
339 * Used for clocks that are part of CLKSEL_xyz governed clocks.
340 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
342 void omap2_clksel_recalc(struct clk
*clk
)
346 pr_debug("clock: recalc'ing clksel clk %s\n", clk
->name
);
348 div
= omap2_clksel_get_divisor(clk
);
352 if (unlikely(clk
->rate
== clk
->parent
->rate
/ div
))
354 clk
->rate
= clk
->parent
->rate
/ div
;
356 pr_debug("clock: new clock rate is %ld (div %d)\n", clk
->rate
, div
);
358 if (unlikely(clk
->flags
& RATE_PROPAGATES
))
363 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
364 * @clk: OMAP struct clk ptr to inspect
365 * @src_clk: OMAP struct clk ptr of the parent clk to search for
367 * Scan the struct clksel array associated with the clock to find
368 * the element associated with the supplied parent clock address.
369 * Returns a pointer to the struct clksel on success or NULL on error.
371 const struct clksel
*omap2_get_clksel_by_parent(struct clk
*clk
,
374 const struct clksel
*clks
;
379 for (clks
= clk
->clksel
; clks
->parent
; clks
++) {
380 if (clks
->parent
== src_clk
)
381 break; /* Found the requested parent */
385 printk(KERN_ERR
"clock: Could not find parent clock %s in "
386 "clksel array of clock %s\n", src_clk
->name
,
395 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
396 * @clk: OMAP struct clk to use
397 * @target_rate: desired clock rate
398 * @new_div: ptr to where we should store the divisor
400 * Finds 'best' divider value in an array based on the source and target
401 * rates. The divider array must be sorted with smallest divider first.
402 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
403 * they are only settable as part of virtual_prcm set.
405 * Returns the rounded clock rate or returns 0xffffffff on error.
407 u32
omap2_clksel_round_rate_div(struct clk
*clk
, unsigned long target_rate
,
410 unsigned long test_rate
;
411 const struct clksel
*clks
;
412 const struct clksel_rate
*clkr
;
415 printk(KERN_INFO
"clock: clksel_round_rate_div: %s target_rate %ld\n",
416 clk
->name
, target_rate
);
420 clks
= omap2_get_clksel_by_parent(clk
, clk
->parent
);
424 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
425 if (!(clkr
->flags
& cpu_mask
))
429 if (clkr
->div
<= last_div
)
430 printk(KERN_ERR
"clock: clksel_rate table not sorted "
431 "for clock %s", clk
->name
);
433 last_div
= clkr
->div
;
435 test_rate
= clk
->parent
->rate
/ clkr
->div
;
437 if (test_rate
<= target_rate
)
438 break; /* found it */
442 printk(KERN_ERR
"clock: Could not find divisor for target "
443 "rate %ld for clock %s parent %s\n", target_rate
,
444 clk
->name
, clk
->parent
->name
);
448 *new_div
= clkr
->div
;
450 printk(KERN_INFO
"clock: new_div = %d, new_rate = %ld\n", *new_div
,
451 (clk
->parent
->rate
/ clkr
->div
));
453 return (clk
->parent
->rate
/ clkr
->div
);
457 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
458 * @clk: OMAP struct clk to use
459 * @target_rate: desired clock rate
461 * Compatibility wrapper for OMAP clock framework
462 * Finds best target rate based on the source clock and possible dividers.
463 * rates. The divider array must be sorted with smallest divider first.
464 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
465 * they are only settable as part of virtual_prcm set.
467 * Returns the rounded clock rate or returns 0xffffffff on error.
469 long omap2_clksel_round_rate(struct clk
*clk
, unsigned long target_rate
)
473 return omap2_clksel_round_rate_div(clk
, target_rate
, &new_div
);
477 /* Given a clock and a rate apply a clock specific rounding function */
478 long omap2_clk_round_rate(struct clk
*clk
, unsigned long rate
)
480 if (clk
->round_rate
!= 0)
481 return clk
->round_rate(clk
, rate
);
483 if (clk
->flags
& RATE_FIXED
)
484 printk(KERN_ERR
"clock: generic omap2_clk_round_rate called "
485 "on fixed-rate clock %s\n", clk
->name
);
491 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
492 * @clk: OMAP struct clk to use
493 * @field_val: register field value to find
495 * Given a struct clk of a rate-selectable clksel clock, and a register field
496 * value to search for, find the corresponding clock divisor. The register
497 * field value should be pre-masked and shifted down so the LSB is at bit 0
498 * before calling. Returns 0 on error
500 u32
omap2_clksel_to_divisor(struct clk
*clk
, u32 field_val
)
502 const struct clksel
*clks
;
503 const struct clksel_rate
*clkr
;
505 clks
= omap2_get_clksel_by_parent(clk
, clk
->parent
);
509 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
510 if ((clkr
->flags
& cpu_mask
) && (clkr
->val
== field_val
))
515 printk(KERN_ERR
"clock: Could not find fieldval %d for "
516 "clock %s parent %s\n", field_val
, clk
->name
,
525 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
526 * @clk: OMAP struct clk to use
527 * @div: integer divisor to search for
529 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
530 * find the corresponding register field value. The return register value is
531 * the value before left-shifting. Returns 0xffffffff on error
533 u32
omap2_divisor_to_clksel(struct clk
*clk
, u32 div
)
535 const struct clksel
*clks
;
536 const struct clksel_rate
*clkr
;
538 /* should never happen */
541 clks
= omap2_get_clksel_by_parent(clk
, clk
->parent
);
545 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
546 if ((clkr
->flags
& cpu_mask
) && (clkr
->div
== div
))
551 printk(KERN_ERR
"clock: Could not find divisor %d for "
552 "clock %s parent %s\n", div
, clk
->name
,
561 * omap2_get_clksel - find clksel register addr & field mask for a clk
562 * @clk: struct clk to use
563 * @field_mask: ptr to u32 to store the register field mask
565 * Returns the address of the clksel register upon success or NULL on error.
567 void __iomem
*omap2_get_clksel(struct clk
*clk
, u32
*field_mask
)
569 if (unlikely((clk
->clksel_reg
== 0) || (clk
->clksel_mask
== 0)))
572 *field_mask
= clk
->clksel_mask
;
574 return clk
->clksel_reg
;
578 * omap2_clksel_get_divisor - get current divider applied to parent clock.
579 * @clk: OMAP struct clk to use.
581 * Returns the integer divisor upon success or 0 on error.
583 u32
omap2_clksel_get_divisor(struct clk
*clk
)
585 u32 field_mask
, field_val
;
586 void __iomem
*div_addr
;
588 div_addr
= omap2_get_clksel(clk
, &field_mask
);
592 field_val
= __raw_readl(div_addr
) & field_mask
;
593 field_val
>>= __ffs(field_mask
);
595 return omap2_clksel_to_divisor(clk
, field_val
);
598 int omap2_clksel_set_rate(struct clk
*clk
, unsigned long rate
)
600 u32 field_mask
, field_val
, reg_val
, validrate
, new_div
= 0;
601 void __iomem
*div_addr
;
603 validrate
= omap2_clksel_round_rate_div(clk
, rate
, &new_div
);
604 if (validrate
!= rate
)
607 div_addr
= omap2_get_clksel(clk
, &field_mask
);
611 field_val
= omap2_divisor_to_clksel(clk
, new_div
);
615 reg_val
= __raw_readl(div_addr
);
616 reg_val
&= ~field_mask
;
617 reg_val
|= (field_val
<< __ffs(field_mask
));
618 __raw_writel(reg_val
, div_addr
);
621 clk
->rate
= clk
->parent
->rate
/ new_div
;
623 if (clk
->flags
& DELAYED_APP
&& cpu_is_omap24xx()) {
624 prm_write_mod_reg(OMAP24XX_VALID_CONFIG
,
625 OMAP24XX_GR_MOD
, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET
);
633 /* Set the clock rate for a clock source */
634 int omap2_clk_set_rate(struct clk
*clk
, unsigned long rate
)
638 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk
->name
, rate
);
640 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
641 rate table mechanism, driven by mpu_speed */
642 if (clk
->flags
& CONFIG_PARTICIPANT
)
645 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
646 if (clk
->set_rate
!= 0)
647 ret
= clk
->set_rate(clk
, rate
);
649 if (unlikely(ret
== 0 && (clk
->flags
& RATE_PROPAGATES
)))
656 * Converts encoded control register address into a full address
657 * On error, *src_addr will be returned as 0.
659 static u32
omap2_clksel_get_src_field(void __iomem
**src_addr
,
660 struct clk
*src_clk
, u32
*field_mask
,
661 struct clk
*clk
, u32
*parent_div
)
663 const struct clksel
*clks
;
664 const struct clksel_rate
*clkr
;
669 clks
= omap2_get_clksel_by_parent(clk
, src_clk
);
673 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
674 if (clkr
->flags
& (cpu_mask
| DEFAULT_RATE
))
675 break; /* Found the default rate for this platform */
679 printk(KERN_ERR
"clock: Could not find default rate for "
680 "clock %s parent %s\n", clk
->name
,
681 src_clk
->parent
->name
);
685 /* Should never happen. Add a clksel mask to the struct clk. */
686 WARN_ON(clk
->clksel_mask
== 0);
688 *field_mask
= clk
->clksel_mask
;
689 *src_addr
= clk
->clksel_reg
;
690 *parent_div
= clkr
->div
;
695 int omap2_clk_set_parent(struct clk
*clk
, struct clk
*new_parent
)
697 void __iomem
*src_addr
;
698 u32 field_val
, field_mask
, reg_val
, parent_div
;
700 if (unlikely(clk
->flags
& CONFIG_PARTICIPANT
))
706 field_val
= omap2_clksel_get_src_field(&src_addr
, new_parent
,
707 &field_mask
, clk
, &parent_div
);
711 if (clk
->usecount
> 0)
712 _omap2_clk_disable(clk
);
714 /* Set new source value (previous dividers if any in effect) */
715 reg_val
= __raw_readl(src_addr
) & ~field_mask
;
716 reg_val
|= (field_val
<< __ffs(field_mask
));
717 __raw_writel(reg_val
, src_addr
);
720 if (clk
->flags
& DELAYED_APP
&& cpu_is_omap24xx()) {
721 __raw_writel(OMAP24XX_VALID_CONFIG
, OMAP24XX_PRCM_CLKCFG_CTRL
);
725 if (clk
->usecount
> 0)
726 _omap2_clk_enable(clk
);
728 clk
->parent
= new_parent
;
730 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
731 clk
->rate
= new_parent
->rate
;
734 clk
->rate
/= parent_div
;
736 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
737 clk
->name
, clk
->parent
->name
, clk
->rate
);
739 if (unlikely(clk
->flags
& RATE_PROPAGATES
))
745 /* DPLL rate rounding code */
748 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
749 * @clk: struct clk * of the DPLL
750 * @tolerance: maximum rate error tolerance
752 * Set the maximum DPLL rate error tolerance for the rate rounding
753 * algorithm. The rate tolerance is an attempt to balance DPLL power
754 * saving (the least divider value "n") vs. rate fidelity (the least
755 * difference between the desired DPLL target rate and the rounded
756 * rate out of the algorithm). So, increasing the tolerance is likely
757 * to decrease DPLL power consumption and increase DPLL rate error.
758 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
759 * DPLL; or 0 upon success.
761 int omap2_dpll_set_rate_tolerance(struct clk
*clk
, unsigned int tolerance
)
763 if (!clk
|| !clk
->dpll_data
)
766 clk
->dpll_data
->rate_tolerance
= tolerance
;
771 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate
, unsigned int m
, unsigned int n
)
773 unsigned long long num
;
775 num
= (unsigned long long)parent_rate
* m
;
781 * _dpll_test_mult - test a DPLL multiplier value
782 * @m: pointer to the DPLL m (multiplier) value under test
783 * @n: current DPLL n (divider) value under test
784 * @new_rate: pointer to storage for the resulting rounded rate
785 * @target_rate: the desired DPLL rate
786 * @parent_rate: the DPLL's parent clock rate
788 * This code tests a DPLL multiplier value, ensuring that the
789 * resulting rate will not be higher than the target_rate, and that
790 * the multiplier value itself is valid for the DPLL. Initially, the
791 * integer pointed to by the m argument should be prescaled by
792 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
793 * a non-scaled m upon return. This non-scaled m will result in a
794 * new_rate as close as possible to target_rate (but not greater than
795 * target_rate) given the current (parent_rate, n, prescaled m)
796 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
797 * non-scaled m attempted to underflow, which can allow the calling
798 * function to bail out early; or 0 upon success.
800 static int _dpll_test_mult(int *m
, int n
, unsigned long *new_rate
,
801 unsigned long target_rate
,
802 unsigned long parent_rate
)
804 int flags
= 0, carry
= 0;
806 /* Unscale m and round if necessary */
807 if (*m
% DPLL_SCALE_FACTOR
>= DPLL_ROUNDING_VAL
)
809 *m
= (*m
/ DPLL_SCALE_FACTOR
) + carry
;
812 * The new rate must be <= the target rate to avoid programming
813 * a rate that is impossible for the hardware to handle
815 *new_rate
= _dpll_compute_new_rate(parent_rate
, *m
, n
);
816 if (*new_rate
> target_rate
) {
821 /* Guard against m underflow */
822 if (*m
< DPLL_MIN_MULTIPLIER
) {
823 *m
= DPLL_MIN_MULTIPLIER
;
825 flags
= DPLL_MULT_UNDERFLOW
;
829 *new_rate
= _dpll_compute_new_rate(parent_rate
, *m
, n
);
835 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
836 * @clk: struct clk * for a DPLL
837 * @target_rate: desired DPLL clock rate
839 * Given a DPLL, a desired target rate, and a rate tolerance, round
840 * the target rate to a possible, programmable rate for this DPLL.
841 * Rate tolerance is assumed to be set by the caller before this
842 * function is called. Attempts to select the minimum possible n
843 * within the tolerance to reduce power consumption. Stores the
844 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
845 * will not need to call this (expensive) function again. Returns ~0
846 * if the target rate cannot be rounded, either because the rate is
847 * too low or because the rate tolerance is set too tightly; or the
848 * rounded rate upon success.
850 long omap2_dpll_round_rate(struct clk
*clk
, unsigned long target_rate
)
852 int m
, n
, r
, e
, scaled_max_m
;
853 unsigned long scaled_rt_rp
, new_rate
;
854 int min_e
= -1, min_e_m
= -1, min_e_n
= -1;
856 if (!clk
|| !clk
->dpll_data
)
859 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
860 "%ld\n", clk
->name
, target_rate
);
862 scaled_rt_rp
= target_rate
/ (clk
->parent
->rate
/ DPLL_SCALE_FACTOR
);
863 scaled_max_m
= clk
->dpll_data
->max_multiplier
* DPLL_SCALE_FACTOR
;
865 clk
->dpll_data
->last_rounded_rate
= 0;
867 for (n
= clk
->dpll_data
->max_divider
; n
>= DPLL_MIN_DIVIDER
; n
--) {
869 /* Compute the scaled DPLL multiplier, based on the divider */
870 m
= scaled_rt_rp
* n
;
873 * Since we're counting n down, a m overflow means we can
874 * can immediately skip to the next n
876 if (m
> scaled_max_m
)
879 r
= _dpll_test_mult(&m
, n
, &new_rate
, target_rate
,
882 e
= target_rate
- new_rate
;
883 pr_debug("clock: n = %d: m = %d: rate error is %d "
884 "(new_rate = %ld)\n", n
, m
, e
, new_rate
);
887 min_e
>= (int)(abs(e
) - clk
->dpll_data
->rate_tolerance
)) {
892 pr_debug("clock: found new least error %d\n", min_e
);
896 * Since we're counting n down, a m underflow means we
897 * can bail out completely (since as n decreases in
898 * the next iteration, there's no way that m can
899 * increase beyond the current m)
901 if (r
& DPLL_MULT_UNDERFLOW
)
906 pr_debug("clock: error: target rate or tolerance too low\n");
910 clk
->dpll_data
->last_rounded_m
= min_e_m
;
911 clk
->dpll_data
->last_rounded_n
= min_e_n
;
912 clk
->dpll_data
->last_rounded_rate
=
913 _dpll_compute_new_rate(clk
->parent
->rate
, min_e_m
, min_e_n
);
915 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
916 min_e
, min_e_m
, min_e_n
);
917 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
918 clk
->dpll_data
->last_rounded_rate
, target_rate
);
920 return clk
->dpll_data
->last_rounded_rate
;
923 /*-------------------------------------------------------------------------
924 * Omap2 clock reset and init functions
925 *-------------------------------------------------------------------------*/
927 #ifdef CONFIG_OMAP_RESET_CLOCKS
928 void omap2_clk_disable_unused(struct clk
*clk
)
932 v
= (clk
->flags
& INVERT_ENABLE
) ? (1 << clk
->enable_bit
) : 0;
934 regval32
= __raw_readl(clk
->enable_reg
);
935 if ((regval32
& (1 << clk
->enable_bit
)) == v
)
938 printk(KERN_INFO
"Disabling unused clock \"%s\"\n", clk
->name
);
939 _omap2_clk_disable(clk
);