2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/list.h>
19 #include <linux/errno.h>
20 #include <linux/err.h>
21 #include <linux/delay.h>
22 #include <linux/clk.h>
24 #include <linux/bitops.h>
28 #include <plat/clock.h>
29 #include <plat/prcm.h>
31 #include <trace/events/power.h>
34 #include "clockdomain.h"
36 #include "cm2xxx_3xxx.h"
37 #include "cm-regbits-24xx.h"
38 #include "cm-regbits-34xx.h"
43 * clkdm_control: if true, then when a clock is enabled in the
44 * hardware, its clockdomain will first be enabled; and when a clock
45 * is disabled in the hardware, its clockdomain will be disabled
48 static bool clkdm_control
= true;
51 * OMAP2+ specific clock functions
54 /* Private functions */
57 * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE
58 * @clk: struct clk * belonging to the module
60 * If the necessary clocks for the OMAP hardware IP block that
61 * corresponds to clock @clk are enabled, then wait for the module to
62 * indicate readiness (i.e., to leave IDLE). This code does not
63 * belong in the clock code and will be moved in the medium term to
64 * module-dependent code. No return value.
66 static void _omap2_module_wait_ready(struct clk
*clk
)
68 void __iomem
*companion_reg
, *idlest_reg
;
69 u8 other_bit
, idlest_bit
, idlest_val
;
71 /* Not all modules have multiple clocks that their IDLEST depends on */
72 if (clk
->ops
->find_companion
) {
73 clk
->ops
->find_companion(clk
, &companion_reg
, &other_bit
);
74 if (!(__raw_readl(companion_reg
) & (1 << other_bit
)))
78 clk
->ops
->find_idlest(clk
, &idlest_reg
, &idlest_bit
, &idlest_val
);
80 omap2_cm_wait_idlest(idlest_reg
, (1 << idlest_bit
), idlest_val
,
84 /* Public functions */
87 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
88 * @clk: OMAP clock struct ptr to use
90 * Convert a clockdomain name stored in a struct clk 'clk' into a
91 * clockdomain pointer, and save it into the struct clk. Intended to be
92 * called during clk_register(). No return value.
94 void omap2_init_clk_clkdm(struct clk
*clk
)
96 struct clockdomain
*clkdm
;
102 clk_name
= __clk_get_name(clk
);
104 clkdm
= clkdm_lookup(clk
->clkdm_name
);
106 pr_debug("clock: associated clk %s to clkdm %s\n",
107 clk_name
, clk
->clkdm_name
);
110 pr_debug("clock: could not associate clk %s to clkdm %s\n",
111 clk_name
, clk
->clkdm_name
);
116 * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable
118 * Prevent the OMAP clock code from calling into the clockdomain code
119 * when a hardware clock in that clockdomain is enabled or disabled.
120 * Intended to be called at init time from omap*_clk_init(). No
123 void __init
omap2_clk_disable_clkdm_control(void)
125 clkdm_control
= false;
129 * omap2_clk_dflt_find_companion - find companion clock to @clk
130 * @clk: struct clk * to find the companion clock of
131 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
132 * @other_bit: u8 ** to return the companion clock bit shift in
134 * Note: We don't need special code here for INVERT_ENABLE for the
135 * time being since INVERT_ENABLE only applies to clocks enabled by
138 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's
139 * just a matter of XORing the bits.
141 * Some clocks don't have companion clocks. For example, modules with
142 * only an interface clock (such as MAILBOXES) don't have a companion
143 * clock. Right now, this code relies on the hardware exporting a bit
144 * in the correct companion register that indicates that the
145 * nonexistent 'companion clock' is active. Future patches will
146 * associate this type of code with per-module data structures to
147 * avoid this issue, and remove the casts. No return value.
149 void omap2_clk_dflt_find_companion(struct clk
*clk
, void __iomem
**other_reg
,
155 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
156 * it's just a matter of XORing the bits.
158 r
= ((__force u32
)clk
->enable_reg
^ (CM_FCLKEN
^ CM_ICLKEN
));
160 *other_reg
= (__force
void __iomem
*)r
;
161 *other_bit
= clk
->enable_bit
;
165 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
166 * @clk: struct clk * to find IDLEST info for
167 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in
168 * @idlest_bit: u8 * to return the CM_IDLEST bit shift in
169 * @idlest_val: u8 * to return the idle status indicator
171 * Return the CM_IDLEST register address and bit shift corresponding
172 * to the module that "owns" this clock. This default code assumes
173 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
174 * the IDLEST register address ID corresponds to the CM_*CLKEN
175 * register address ID (e.g., that CM_FCLKEN2 corresponds to
176 * CM_IDLEST2). This is not true for all modules. No return value.
178 void omap2_clk_dflt_find_idlest(struct clk
*clk
, void __iomem
**idlest_reg
,
179 u8
*idlest_bit
, u8
*idlest_val
)
183 r
= (((__force u32
)clk
->enable_reg
& ~0xf0) | 0x20);
184 *idlest_reg
= (__force
void __iomem
*)r
;
185 *idlest_bit
= clk
->enable_bit
;
188 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
189 * 34xx reverses this, just to keep us on our toes
190 * AM35xx uses both, depending on the module.
192 if (cpu_is_omap24xx())
193 *idlest_val
= OMAP24XX_CM_IDLEST_VAL
;
194 else if (cpu_is_omap34xx())
195 *idlest_val
= OMAP34XX_CM_IDLEST_VAL
;
201 int omap2_dflt_clk_enable(struct clk
*clk
)
205 if (unlikely(clk
->enable_reg
== NULL
)) {
206 pr_err("clock.c: Enable for %s without enable code\n",
208 return 0; /* REVISIT: -EINVAL */
211 v
= __raw_readl(clk
->enable_reg
);
212 if (clk
->flags
& INVERT_ENABLE
)
213 v
&= ~(1 << clk
->enable_bit
);
215 v
|= (1 << clk
->enable_bit
);
216 __raw_writel(v
, clk
->enable_reg
);
217 v
= __raw_readl(clk
->enable_reg
); /* OCP barrier */
219 if (clk
->ops
->find_idlest
)
220 _omap2_module_wait_ready(clk
);
225 void omap2_dflt_clk_disable(struct clk
*clk
)
229 if (!clk
->enable_reg
) {
231 * 'Independent' here refers to a clock which is not
232 * controlled by its parent.
234 pr_err("clock: clk_disable called on independent clock %s which has no enable_reg\n", clk
->name
);
238 v
= __raw_readl(clk
->enable_reg
);
239 if (clk
->flags
& INVERT_ENABLE
)
240 v
|= (1 << clk
->enable_bit
);
242 v
&= ~(1 << clk
->enable_bit
);
243 __raw_writel(v
, clk
->enable_reg
);
244 /* No OCP barrier needed here since it is a disable operation */
247 const struct clkops clkops_omap2_dflt_wait
= {
248 .enable
= omap2_dflt_clk_enable
,
249 .disable
= omap2_dflt_clk_disable
,
250 .find_companion
= omap2_clk_dflt_find_companion
,
251 .find_idlest
= omap2_clk_dflt_find_idlest
,
254 const struct clkops clkops_omap2_dflt
= {
255 .enable
= omap2_dflt_clk_enable
,
256 .disable
= omap2_dflt_clk_disable
,
260 * omap2_clk_disable - disable a clock, if the system is not using it
261 * @clk: struct clk * to disable
263 * Decrements the usecount on struct clk @clk. If there are no users
264 * left, call the clkops-specific clock disable function to disable it
265 * in hardware. If the clock is part of a clockdomain (which they all
266 * should be), request that the clockdomain be disabled. (It too has
267 * a usecount, and so will not be disabled in the hardware until it no
268 * longer has any users.) If the clock has a parent clock (most of
269 * them do), then call ourselves, recursing on the parent clock. This
270 * can cause an entire branch of the clock tree to be powered off by
271 * simply disabling one clock. Intended to be called with the clockfw_lock
272 * spinlock held. No return value.
274 void omap2_clk_disable(struct clk
*clk
)
276 if (clk
->usecount
== 0) {
277 WARN(1, "clock: %s: omap2_clk_disable() called, but usecount already 0?", clk
->name
);
281 pr_debug("clock: %s: decrementing usecount\n", clk
->name
);
285 if (clk
->usecount
> 0)
288 pr_debug("clock: %s: disabling in hardware\n", clk
->name
);
290 if (clk
->ops
&& clk
->ops
->disable
) {
291 trace_clock_disable(clk
->name
, 0, smp_processor_id());
292 clk
->ops
->disable(clk
);
295 if (clkdm_control
&& clk
->clkdm
)
296 clkdm_clk_disable(clk
->clkdm
, clk
);
299 omap2_clk_disable(clk
->parent
);
303 * omap2_clk_enable - request that the system enable a clock
304 * @clk: struct clk * to enable
306 * Increments the usecount on struct clk @clk. If there were no users
307 * previously, then recurse up the clock tree, enabling all of the
308 * clock's parents and all of the parent clockdomains, and finally,
309 * enabling @clk's clockdomain, and @clk itself. Intended to be
310 * called with the clockfw_lock spinlock held. Returns 0 upon success
311 * or a negative error code upon failure.
313 int omap2_clk_enable(struct clk
*clk
)
317 pr_debug("clock: %s: incrementing usecount\n", clk
->name
);
321 if (clk
->usecount
> 1)
324 pr_debug("clock: %s: enabling in hardware\n", clk
->name
);
327 ret
= omap2_clk_enable(clk
->parent
);
329 WARN(1, "clock: %s: could not enable parent %s: %d\n",
330 clk
->name
, clk
->parent
->name
, ret
);
335 if (clkdm_control
&& clk
->clkdm
) {
336 ret
= clkdm_clk_enable(clk
->clkdm
, clk
);
338 WARN(1, "clock: %s: could not enable clockdomain %s: %d\n",
339 clk
->name
, clk
->clkdm
->name
, ret
);
344 if (clk
->ops
&& clk
->ops
->enable
) {
345 trace_clock_enable(clk
->name
, 1, smp_processor_id());
346 ret
= clk
->ops
->enable(clk
);
348 WARN(1, "clock: %s: could not enable: %d\n",
357 if (clkdm_control
&& clk
->clkdm
)
358 clkdm_clk_disable(clk
->clkdm
, clk
);
361 omap2_clk_disable(clk
->parent
);
368 /* Given a clock and a rate apply a clock specific rounding function */
369 long omap2_clk_round_rate(struct clk
*clk
, unsigned long rate
)
372 return clk
->round_rate(clk
, rate
);
377 /* Set the clock rate for a clock source */
378 int omap2_clk_set_rate(struct clk
*clk
, unsigned long rate
)
382 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk
->name
, rate
);
384 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
386 trace_clock_set_rate(clk
->name
, rate
, smp_processor_id());
387 ret
= clk
->set_rate(clk
, rate
);
393 int omap2_clk_set_parent(struct clk
*clk
, struct clk
*new_parent
)
398 if (clk
->parent
== new_parent
)
401 return omap2_clksel_set_parent(clk
, new_parent
);
405 * OMAP2+ clock reset and init functions
408 #ifdef CONFIG_OMAP_RESET_CLOCKS
409 void omap2_clk_disable_unused(struct clk
*clk
)
413 v
= (clk
->flags
& INVERT_ENABLE
) ? (1 << clk
->enable_bit
) : 0;
415 regval32
= __raw_readl(clk
->enable_reg
);
416 if ((regval32
& (1 << clk
->enable_bit
)) == v
)
419 pr_debug("Disabling unused clock \"%s\"\n", clk
->name
);
420 if (cpu_is_omap34xx()) {
421 omap2_clk_enable(clk
);
422 omap2_clk_disable(clk
);
424 clk
->ops
->disable(clk
);
426 if (clk
->clkdm
!= NULL
)
427 pwrdm_state_switch(clk
->clkdm
->pwrdm
.ptr
);
432 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
433 * @mpurate_ck_name: clk name of the clock to change rate
435 * Change the ARM MPU clock rate to the rate specified on the command
436 * line, if one was specified. @mpurate_ck_name should be
437 * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx.
438 * XXX Does not handle voltage scaling - on OMAP2xxx this is currently
439 * handled by the virt_prcm_set clock, but this should be handled by
440 * the OPP layer. XXX This is intended to be handled by the OPP layer
441 * code in the near future and should be removed from the clock code.
442 * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects
443 * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name
444 * cannot be found, or 0 upon success.
446 int __init
omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name
)
448 struct clk
*mpurate_ck
;
454 mpurate_ck
= clk_get(NULL
, mpurate_ck_name
);
455 if (WARN(IS_ERR(mpurate_ck
), "Failed to get %s.\n", mpurate_ck_name
))
458 r
= clk_set_rate(mpurate_ck
, mpurate
);
459 if (IS_ERR_VALUE(r
)) {
460 WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
461 mpurate_ck
->name
, mpurate
, r
);
467 recalculate_root_clocks();
475 * omap2_clk_print_new_rates - print summary of current clock tree rates
476 * @hfclkin_ck_name: clk name for the off-chip HF oscillator
477 * @core_ck_name: clk name for the on-chip CORE_CLK
478 * @mpu_ck_name: clk name for the ARM MPU clock
480 * Prints a short message to the console with the HFCLKIN oscillator
481 * rate, the rate of the CORE clock, and the rate of the ARM MPU clock.
482 * Called by the boot-time MPU rate switching code. XXX This is intended
483 * to be handled by the OPP layer code in the near future and should be
484 * removed from the clock code. No return value.
486 void __init
omap2_clk_print_new_rates(const char *hfclkin_ck_name
,
487 const char *core_ck_name
,
488 const char *mpu_ck_name
)
490 struct clk
*hfclkin_ck
, *core_ck
, *mpu_ck
;
491 unsigned long hfclkin_rate
;
493 mpu_ck
= clk_get(NULL
, mpu_ck_name
);
494 if (WARN(IS_ERR(mpu_ck
), "clock: failed to get %s.\n", mpu_ck_name
))
497 core_ck
= clk_get(NULL
, core_ck_name
);
498 if (WARN(IS_ERR(core_ck
), "clock: failed to get %s.\n", core_ck_name
))
501 hfclkin_ck
= clk_get(NULL
, hfclkin_ck_name
);
502 if (WARN(IS_ERR(hfclkin_ck
), "Failed to get %s.\n", hfclkin_ck_name
))
505 hfclkin_rate
= clk_get_rate(hfclkin_ck
);
507 pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
508 (hfclkin_rate
/ 1000000), ((hfclkin_rate
/ 100000) % 10),
509 (clk_get_rate(core_ck
) / 1000000),
510 (clk_get_rate(mpu_ck
) / 1000000));
515 struct clk_functions omap2_clk_functions
= {
516 .clk_enable
= omap2_clk_enable
,
517 .clk_disable
= omap2_clk_disable
,
518 .clk_round_rate
= omap2_clk_round_rate
,
519 .clk_set_rate
= omap2_clk_set_rate
,
520 .clk_set_parent
= omap2_clk_set_parent
,
521 .clk_disable_unused
= omap2_clk_disable_unused
,