2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
25 #include <linux/bitops.h>
27 #include <mach/clock.h>
28 #include <mach/clockdomain.h>
29 #include <mach/sram.h>
31 #include <asm/div64.h>
37 #include "prm-regbits-24xx.h"
39 #include "cm-regbits-24xx.h"
40 #include "cm-regbits-34xx.h"
42 #define MAX_CLOCK_ENABLE_WAIT 100000
44 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
45 #define DPLL_MIN_MULTIPLIER 1
46 #define DPLL_MIN_DIVIDER 1
48 /* Possible error results from _dpll_test_mult */
49 #define DPLL_MULT_UNDERFLOW (1 << 0)
52 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
53 * The higher the scale factor, the greater the risk of arithmetic overflow,
54 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
55 * must be a power of DPLL_SCALE_BASE.
57 #define DPLL_SCALE_FACTOR 64
58 #define DPLL_SCALE_BASE 2
59 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
60 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
64 /*-------------------------------------------------------------------------
65 * OMAP2/3 specific clock functions
66 *-------------------------------------------------------------------------*/
69 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
70 * @clk: OMAP clock struct ptr to use
72 * Convert a clockdomain name stored in a struct clk 'clk' into a
73 * clockdomain pointer, and save it into the struct clk. Intended to be
74 * called during clk_register(). No return value.
76 void omap2_init_clk_clkdm(struct clk
*clk
)
78 struct clockdomain
*clkdm
;
83 clkdm
= clkdm_lookup(clk
->clkdm_name
);
85 pr_debug("clock: associated clk %s to clkdm %s\n",
86 clk
->name
, clk
->clkdm_name
);
89 pr_debug("clock: could not associate clk %s to "
90 "clkdm %s\n", clk
->name
, clk
->clkdm_name
);
95 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
96 * @clk: OMAP clock struct ptr to use
98 * Given a pointer to a source-selectable struct clk, read the hardware
99 * register and determine what its parent is currently set to. Update the
100 * clk->parent field with the appropriate clk ptr.
102 void omap2_init_clksel_parent(struct clk
*clk
)
104 const struct clksel
*clks
;
105 const struct clksel_rate
*clkr
;
111 r
= __raw_readl(clk
->clksel_reg
) & clk
->clksel_mask
;
112 r
>>= __ffs(clk
->clksel_mask
);
114 for (clks
= clk
->clksel
; clks
->parent
&& !found
; clks
++) {
115 for (clkr
= clks
->rates
; clkr
->div
&& !found
; clkr
++) {
116 if ((clkr
->flags
& cpu_mask
) && (clkr
->val
== r
)) {
117 if (clk
->parent
!= clks
->parent
) {
118 pr_debug("clock: inited %s parent "
120 clk
->name
, clks
->parent
->name
,
122 clk
->parent
->name
: "NULL"));
123 clk
->parent
= clks
->parent
;
131 printk(KERN_ERR
"clock: init parent: could not find "
132 "regval %0x for clock %s\n", r
, clk
->name
);
137 /* Returns the DPLL rate */
138 u32
omap2_get_dpll_rate(struct clk
*clk
)
141 u32 dpll_mult
, dpll_div
, dpll
;
142 struct dpll_data
*dd
;
145 /* REVISIT: What do we return on error? */
149 dpll
= __raw_readl(dd
->mult_div1_reg
);
150 dpll_mult
= dpll
& dd
->mult_mask
;
151 dpll_mult
>>= __ffs(dd
->mult_mask
);
152 dpll_div
= dpll
& dd
->div1_mask
;
153 dpll_div
>>= __ffs(dd
->div1_mask
);
155 dpll_clk
= (long long)clk
->parent
->rate
* dpll_mult
;
156 do_div(dpll_clk
, dpll_div
+ 1);
162 * Used for clocks that have the same value as the parent clock,
163 * divided by some factor
165 void omap2_fixed_divisor_recalc(struct clk
*clk
)
167 WARN_ON(!clk
->fixed_div
);
169 clk
->rate
= clk
->parent
->rate
/ clk
->fixed_div
;
171 if (clk
->flags
& RATE_PROPAGATES
)
176 * omap2_wait_clock_ready - wait for clock to enable
177 * @reg: physical address of clock IDLEST register
178 * @mask: value to mask against to determine if the clock is active
179 * @name: name of the clock (for printk)
181 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
182 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
184 int omap2_wait_clock_ready(void __iomem
*reg
, u32 mask
, const char *name
)
190 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
191 * 34xx reverses this, just to keep us on our toes
193 if (cpu_mask
& (RATE_IN_242X
| RATE_IN_243X
)) {
195 } else if (cpu_mask
& RATE_IN_343X
) {
200 while (((__raw_readl(reg
) & mask
) != ena
) &&
201 (i
++ < MAX_CLOCK_ENABLE_WAIT
)) {
205 if (i
< MAX_CLOCK_ENABLE_WAIT
)
206 pr_debug("Clock %s stable after %d loops\n", name
, i
);
208 printk(KERN_ERR
"Clock %s didn't enable in %d tries\n",
209 name
, MAX_CLOCK_ENABLE_WAIT
);
212 return (i
< MAX_CLOCK_ENABLE_WAIT
) ? 1 : 0;
217 * Note: We don't need special code here for INVERT_ENABLE
218 * for the time being since INVERT_ENABLE only applies to clocks enabled by
221 static void omap2_clk_wait_ready(struct clk
*clk
)
223 void __iomem
*reg
, *other_reg
, *st_reg
;
227 * REVISIT: This code is pretty ugly. It would be nice to generalize
228 * it and pull it into struct clk itself somehow.
230 reg
= clk
->enable_reg
;
231 if ((((u32
)reg
& 0xff) >= CM_FCLKEN1
) &&
232 (((u32
)reg
& 0xff) <= OMAP24XX_CM_FCLKEN2
))
233 other_reg
= (void __iomem
*)(((u32
)reg
& ~0xf0) | 0x10); /* CM_ICLKEN* */
234 else if ((((u32
)reg
& 0xff) >= CM_ICLKEN1
) &&
235 (((u32
)reg
& 0xff) <= OMAP24XX_CM_ICLKEN4
))
236 other_reg
= (void __iomem
*)(((u32
)reg
& ~0xf0) | 0x00); /* CM_FCLKEN* */
240 /* REVISIT: What are the appropriate exclusions for 34XX? */
241 /* No check for DSS or cam clocks */
242 if (cpu_is_omap24xx() && ((u32
)reg
& 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
243 if (clk
->enable_bit
== OMAP24XX_EN_DSS2_SHIFT
||
244 clk
->enable_bit
== OMAP24XX_EN_DSS1_SHIFT
||
245 clk
->enable_bit
== OMAP24XX_EN_CAM_SHIFT
)
249 /* REVISIT: What are the appropriate exclusions for 34XX? */
250 /* OMAP3: ignore DSS-mod clocks */
251 if (cpu_is_omap34xx() &&
252 (((u32
)reg
& ~0xff) == (u32
)OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, 0) ||
253 ((((u32
)reg
& ~0xff) == (u32
)OMAP_CM_REGADDR(CORE_MOD
, 0)) &&
254 clk
->enable_bit
== OMAP3430_EN_SSI_SHIFT
)))
257 /* Check if both functional and interface clocks
259 bit
= 1 << clk
->enable_bit
;
260 if (!(__raw_readl(other_reg
) & bit
))
262 st_reg
= (void __iomem
*)(((u32
)other_reg
& ~0xf0) | 0x20); /* CM_IDLEST* */
264 omap2_wait_clock_ready(st_reg
, bit
, clk
->name
);
267 /* Enables clock without considering parent dependencies or use count
268 * REVISIT: Maybe change this to use clk->enable like on omap1?
270 int _omap2_clk_enable(struct clk
*clk
)
274 if (clk
->ops
&& clk
->ops
->enable
)
275 return clk
->ops
->enable(clk
);
277 if (unlikely(clk
->enable_reg
== NULL
)) {
278 printk(KERN_ERR
"clock.c: Enable for %s without enable code\n",
280 return 0; /* REVISIT: -EINVAL */
283 regval32
= __raw_readl(clk
->enable_reg
);
284 if (clk
->flags
& INVERT_ENABLE
)
285 regval32
&= ~(1 << clk
->enable_bit
);
287 regval32
|= (1 << clk
->enable_bit
);
288 __raw_writel(regval32
, clk
->enable_reg
);
291 omap2_clk_wait_ready(clk
);
296 /* Disables clock without considering parent dependencies or use count */
297 void _omap2_clk_disable(struct clk
*clk
)
301 if (clk
->ops
&& clk
->ops
->disable
) {
302 clk
->ops
->disable(clk
);
306 if (clk
->enable_reg
== NULL
) {
308 * 'Independent' here refers to a clock which is not
309 * controlled by its parent.
311 printk(KERN_ERR
"clock: clk_disable called on independent "
312 "clock %s which has no enable_reg\n", clk
->name
);
316 regval32
= __raw_readl(clk
->enable_reg
);
317 if (clk
->flags
& INVERT_ENABLE
)
318 regval32
|= (1 << clk
->enable_bit
);
320 regval32
&= ~(1 << clk
->enable_bit
);
321 __raw_writel(regval32
, clk
->enable_reg
);
325 void omap2_clk_disable(struct clk
*clk
)
327 if (clk
->usecount
> 0 && !(--clk
->usecount
)) {
328 _omap2_clk_disable(clk
);
329 if (likely((u32
)clk
->parent
))
330 omap2_clk_disable(clk
->parent
);
332 omap2_clkdm_clk_disable(clk
->clkdm
, clk
);
337 int omap2_clk_enable(struct clk
*clk
)
341 if (clk
->usecount
++ == 0) {
342 if (likely((u32
)clk
->parent
))
343 ret
= omap2_clk_enable(clk
->parent
);
345 if (unlikely(ret
!= 0)) {
351 omap2_clkdm_clk_enable(clk
->clkdm
, clk
);
353 ret
= _omap2_clk_enable(clk
);
355 if (unlikely(ret
!= 0)) {
357 omap2_clkdm_clk_disable(clk
->clkdm
, clk
);
360 omap2_clk_disable(clk
->parent
);
370 * Used for clocks that are part of CLKSEL_xyz governed clocks.
371 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
373 void omap2_clksel_recalc(struct clk
*clk
)
377 pr_debug("clock: recalc'ing clksel clk %s\n", clk
->name
);
379 div
= omap2_clksel_get_divisor(clk
);
383 if (unlikely(clk
->rate
== clk
->parent
->rate
/ div
))
385 clk
->rate
= clk
->parent
->rate
/ div
;
387 pr_debug("clock: new clock rate is %ld (div %d)\n", clk
->rate
, div
);
389 if (unlikely(clk
->flags
& RATE_PROPAGATES
))
394 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
395 * @clk: OMAP struct clk ptr to inspect
396 * @src_clk: OMAP struct clk ptr of the parent clk to search for
398 * Scan the struct clksel array associated with the clock to find
399 * the element associated with the supplied parent clock address.
400 * Returns a pointer to the struct clksel on success or NULL on error.
402 const struct clksel
*omap2_get_clksel_by_parent(struct clk
*clk
,
405 const struct clksel
*clks
;
410 for (clks
= clk
->clksel
; clks
->parent
; clks
++) {
411 if (clks
->parent
== src_clk
)
412 break; /* Found the requested parent */
416 printk(KERN_ERR
"clock: Could not find parent clock %s in "
417 "clksel array of clock %s\n", src_clk
->name
,
426 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
427 * @clk: OMAP struct clk to use
428 * @target_rate: desired clock rate
429 * @new_div: ptr to where we should store the divisor
431 * Finds 'best' divider value in an array based on the source and target
432 * rates. The divider array must be sorted with smallest divider first.
433 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
434 * they are only settable as part of virtual_prcm set.
436 * Returns the rounded clock rate or returns 0xffffffff on error.
438 u32
omap2_clksel_round_rate_div(struct clk
*clk
, unsigned long target_rate
,
441 unsigned long test_rate
;
442 const struct clksel
*clks
;
443 const struct clksel_rate
*clkr
;
446 printk(KERN_INFO
"clock: clksel_round_rate_div: %s target_rate %ld\n",
447 clk
->name
, target_rate
);
451 clks
= omap2_get_clksel_by_parent(clk
, clk
->parent
);
455 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
456 if (!(clkr
->flags
& cpu_mask
))
460 if (clkr
->div
<= last_div
)
461 printk(KERN_ERR
"clock: clksel_rate table not sorted "
462 "for clock %s", clk
->name
);
464 last_div
= clkr
->div
;
466 test_rate
= clk
->parent
->rate
/ clkr
->div
;
468 if (test_rate
<= target_rate
)
469 break; /* found it */
473 printk(KERN_ERR
"clock: Could not find divisor for target "
474 "rate %ld for clock %s parent %s\n", target_rate
,
475 clk
->name
, clk
->parent
->name
);
479 *new_div
= clkr
->div
;
481 printk(KERN_INFO
"clock: new_div = %d, new_rate = %ld\n", *new_div
,
482 (clk
->parent
->rate
/ clkr
->div
));
484 return (clk
->parent
->rate
/ clkr
->div
);
488 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
489 * @clk: OMAP struct clk to use
490 * @target_rate: desired clock rate
492 * Compatibility wrapper for OMAP clock framework
493 * Finds best target rate based on the source clock and possible dividers.
494 * rates. The divider array must be sorted with smallest divider first.
495 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
496 * they are only settable as part of virtual_prcm set.
498 * Returns the rounded clock rate or returns 0xffffffff on error.
500 long omap2_clksel_round_rate(struct clk
*clk
, unsigned long target_rate
)
504 return omap2_clksel_round_rate_div(clk
, target_rate
, &new_div
);
508 /* Given a clock and a rate apply a clock specific rounding function */
509 long omap2_clk_round_rate(struct clk
*clk
, unsigned long rate
)
511 if (clk
->round_rate
!= NULL
)
512 return clk
->round_rate(clk
, rate
);
514 if (clk
->flags
& RATE_FIXED
)
515 printk(KERN_ERR
"clock: generic omap2_clk_round_rate called "
516 "on fixed-rate clock %s\n", clk
->name
);
522 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
523 * @clk: OMAP struct clk to use
524 * @field_val: register field value to find
526 * Given a struct clk of a rate-selectable clksel clock, and a register field
527 * value to search for, find the corresponding clock divisor. The register
528 * field value should be pre-masked and shifted down so the LSB is at bit 0
529 * before calling. Returns 0 on error
531 u32
omap2_clksel_to_divisor(struct clk
*clk
, u32 field_val
)
533 const struct clksel
*clks
;
534 const struct clksel_rate
*clkr
;
536 clks
= omap2_get_clksel_by_parent(clk
, clk
->parent
);
540 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
541 if ((clkr
->flags
& cpu_mask
) && (clkr
->val
== field_val
))
546 printk(KERN_ERR
"clock: Could not find fieldval %d for "
547 "clock %s parent %s\n", field_val
, clk
->name
,
556 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
557 * @clk: OMAP struct clk to use
558 * @div: integer divisor to search for
560 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
561 * find the corresponding register field value. The return register value is
562 * the value before left-shifting. Returns 0xffffffff on error
564 u32
omap2_divisor_to_clksel(struct clk
*clk
, u32 div
)
566 const struct clksel
*clks
;
567 const struct clksel_rate
*clkr
;
569 /* should never happen */
572 clks
= omap2_get_clksel_by_parent(clk
, clk
->parent
);
576 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
577 if ((clkr
->flags
& cpu_mask
) && (clkr
->div
== div
))
582 printk(KERN_ERR
"clock: Could not find divisor %d for "
583 "clock %s parent %s\n", div
, clk
->name
,
592 * omap2_get_clksel - find clksel register addr & field mask for a clk
593 * @clk: struct clk to use
594 * @field_mask: ptr to u32 to store the register field mask
596 * Returns the address of the clksel register upon success or NULL on error.
598 void __iomem
*omap2_get_clksel(struct clk
*clk
, u32
*field_mask
)
600 if (unlikely((clk
->clksel_reg
== NULL
) || (clk
->clksel_mask
== NULL
)))
603 *field_mask
= clk
->clksel_mask
;
605 return clk
->clksel_reg
;
609 * omap2_clksel_get_divisor - get current divider applied to parent clock.
610 * @clk: OMAP struct clk to use.
612 * Returns the integer divisor upon success or 0 on error.
614 u32
omap2_clksel_get_divisor(struct clk
*clk
)
616 u32 field_mask
, field_val
;
617 void __iomem
*div_addr
;
619 div_addr
= omap2_get_clksel(clk
, &field_mask
);
620 if (div_addr
== NULL
)
623 field_val
= __raw_readl(div_addr
) & field_mask
;
624 field_val
>>= __ffs(field_mask
);
626 return omap2_clksel_to_divisor(clk
, field_val
);
629 int omap2_clksel_set_rate(struct clk
*clk
, unsigned long rate
)
631 u32 field_mask
, field_val
, reg_val
, validrate
, new_div
= 0;
632 void __iomem
*div_addr
;
634 validrate
= omap2_clksel_round_rate_div(clk
, rate
, &new_div
);
635 if (validrate
!= rate
)
638 div_addr
= omap2_get_clksel(clk
, &field_mask
);
639 if (div_addr
== NULL
)
642 field_val
= omap2_divisor_to_clksel(clk
, new_div
);
646 reg_val
= __raw_readl(div_addr
);
647 reg_val
&= ~field_mask
;
648 reg_val
|= (field_val
<< __ffs(field_mask
));
649 __raw_writel(reg_val
, div_addr
);
652 clk
->rate
= clk
->parent
->rate
/ new_div
;
654 if (clk
->flags
& DELAYED_APP
&& cpu_is_omap24xx()) {
655 prm_write_mod_reg(OMAP24XX_VALID_CONFIG
,
656 OMAP24XX_GR_MOD
, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET
);
664 /* Set the clock rate for a clock source */
665 int omap2_clk_set_rate(struct clk
*clk
, unsigned long rate
)
669 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk
->name
, rate
);
671 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
672 rate table mechanism, driven by mpu_speed */
673 if (clk
->flags
& CONFIG_PARTICIPANT
)
676 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
677 if (clk
->set_rate
!= NULL
)
678 ret
= clk
->set_rate(clk
, rate
);
680 if (unlikely(ret
== 0 && (clk
->flags
& RATE_PROPAGATES
)))
687 * Converts encoded control register address into a full address
688 * On error, *src_addr will be returned as 0.
690 static u32
omap2_clksel_get_src_field(void __iomem
**src_addr
,
691 struct clk
*src_clk
, u32
*field_mask
,
692 struct clk
*clk
, u32
*parent_div
)
694 const struct clksel
*clks
;
695 const struct clksel_rate
*clkr
;
700 clks
= omap2_get_clksel_by_parent(clk
, src_clk
);
704 for (clkr
= clks
->rates
; clkr
->div
; clkr
++) {
705 if (clkr
->flags
& (cpu_mask
| DEFAULT_RATE
))
706 break; /* Found the default rate for this platform */
710 printk(KERN_ERR
"clock: Could not find default rate for "
711 "clock %s parent %s\n", clk
->name
,
712 src_clk
->parent
->name
);
716 /* Should never happen. Add a clksel mask to the struct clk. */
717 WARN_ON(clk
->clksel_mask
== 0);
719 *field_mask
= clk
->clksel_mask
;
720 *src_addr
= clk
->clksel_reg
;
721 *parent_div
= clkr
->div
;
726 int omap2_clk_set_parent(struct clk
*clk
, struct clk
*new_parent
)
728 void __iomem
*src_addr
;
729 u32 field_val
, field_mask
, reg_val
, parent_div
;
731 if (unlikely(clk
->flags
& CONFIG_PARTICIPANT
))
737 field_val
= omap2_clksel_get_src_field(&src_addr
, new_parent
,
738 &field_mask
, clk
, &parent_div
);
739 if (src_addr
== NULL
)
742 if (clk
->usecount
> 0)
743 _omap2_clk_disable(clk
);
745 /* Set new source value (previous dividers if any in effect) */
746 reg_val
= __raw_readl(src_addr
) & ~field_mask
;
747 reg_val
|= (field_val
<< __ffs(field_mask
));
748 __raw_writel(reg_val
, src_addr
);
751 if (clk
->flags
& DELAYED_APP
&& cpu_is_omap24xx()) {
752 __raw_writel(OMAP24XX_VALID_CONFIG
, OMAP24XX_PRCM_CLKCFG_CTRL
);
756 if (clk
->usecount
> 0)
757 _omap2_clk_enable(clk
);
759 clk
->parent
= new_parent
;
761 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
762 clk
->rate
= new_parent
->rate
;
765 clk
->rate
/= parent_div
;
767 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
768 clk
->name
, clk
->parent
->name
, clk
->rate
);
770 if (unlikely(clk
->flags
& RATE_PROPAGATES
))
776 /* DPLL rate rounding code */
779 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
780 * @clk: struct clk * of the DPLL
781 * @tolerance: maximum rate error tolerance
783 * Set the maximum DPLL rate error tolerance for the rate rounding
784 * algorithm. The rate tolerance is an attempt to balance DPLL power
785 * saving (the least divider value "n") vs. rate fidelity (the least
786 * difference between the desired DPLL target rate and the rounded
787 * rate out of the algorithm). So, increasing the tolerance is likely
788 * to decrease DPLL power consumption and increase DPLL rate error.
789 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
790 * DPLL; or 0 upon success.
792 int omap2_dpll_set_rate_tolerance(struct clk
*clk
, unsigned int tolerance
)
794 if (!clk
|| !clk
->dpll_data
)
797 clk
->dpll_data
->rate_tolerance
= tolerance
;
802 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate
, unsigned int m
, unsigned int n
)
804 unsigned long long num
;
806 num
= (unsigned long long)parent_rate
* m
;
812 * _dpll_test_mult - test a DPLL multiplier value
813 * @m: pointer to the DPLL m (multiplier) value under test
814 * @n: current DPLL n (divider) value under test
815 * @new_rate: pointer to storage for the resulting rounded rate
816 * @target_rate: the desired DPLL rate
817 * @parent_rate: the DPLL's parent clock rate
819 * This code tests a DPLL multiplier value, ensuring that the
820 * resulting rate will not be higher than the target_rate, and that
821 * the multiplier value itself is valid for the DPLL. Initially, the
822 * integer pointed to by the m argument should be prescaled by
823 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
824 * a non-scaled m upon return. This non-scaled m will result in a
825 * new_rate as close as possible to target_rate (but not greater than
826 * target_rate) given the current (parent_rate, n, prescaled m)
827 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
828 * non-scaled m attempted to underflow, which can allow the calling
829 * function to bail out early; or 0 upon success.
831 static int _dpll_test_mult(int *m
, int n
, unsigned long *new_rate
,
832 unsigned long target_rate
,
833 unsigned long parent_rate
)
835 int flags
= 0, carry
= 0;
837 /* Unscale m and round if necessary */
838 if (*m
% DPLL_SCALE_FACTOR
>= DPLL_ROUNDING_VAL
)
840 *m
= (*m
/ DPLL_SCALE_FACTOR
) + carry
;
843 * The new rate must be <= the target rate to avoid programming
844 * a rate that is impossible for the hardware to handle
846 *new_rate
= _dpll_compute_new_rate(parent_rate
, *m
, n
);
847 if (*new_rate
> target_rate
) {
852 /* Guard against m underflow */
853 if (*m
< DPLL_MIN_MULTIPLIER
) {
854 *m
= DPLL_MIN_MULTIPLIER
;
856 flags
= DPLL_MULT_UNDERFLOW
;
860 *new_rate
= _dpll_compute_new_rate(parent_rate
, *m
, n
);
866 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
867 * @clk: struct clk * for a DPLL
868 * @target_rate: desired DPLL clock rate
870 * Given a DPLL, a desired target rate, and a rate tolerance, round
871 * the target rate to a possible, programmable rate for this DPLL.
872 * Rate tolerance is assumed to be set by the caller before this
873 * function is called. Attempts to select the minimum possible n
874 * within the tolerance to reduce power consumption. Stores the
875 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
876 * will not need to call this (expensive) function again. Returns ~0
877 * if the target rate cannot be rounded, either because the rate is
878 * too low or because the rate tolerance is set too tightly; or the
879 * rounded rate upon success.
881 long omap2_dpll_round_rate(struct clk
*clk
, unsigned long target_rate
)
883 int m
, n
, r
, e
, scaled_max_m
;
884 unsigned long scaled_rt_rp
, new_rate
;
885 int min_e
= -1, min_e_m
= -1, min_e_n
= -1;
887 if (!clk
|| !clk
->dpll_data
)
890 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
891 "%ld\n", clk
->name
, target_rate
);
893 scaled_rt_rp
= target_rate
/ (clk
->parent
->rate
/ DPLL_SCALE_FACTOR
);
894 scaled_max_m
= clk
->dpll_data
->max_multiplier
* DPLL_SCALE_FACTOR
;
896 clk
->dpll_data
->last_rounded_rate
= 0;
898 for (n
= clk
->dpll_data
->max_divider
; n
>= DPLL_MIN_DIVIDER
; n
--) {
900 /* Compute the scaled DPLL multiplier, based on the divider */
901 m
= scaled_rt_rp
* n
;
904 * Since we're counting n down, a m overflow means we can
905 * can immediately skip to the next n
907 if (m
> scaled_max_m
)
910 r
= _dpll_test_mult(&m
, n
, &new_rate
, target_rate
,
913 e
= target_rate
- new_rate
;
914 pr_debug("clock: n = %d: m = %d: rate error is %d "
915 "(new_rate = %ld)\n", n
, m
, e
, new_rate
);
918 min_e
>= (int)(abs(e
) - clk
->dpll_data
->rate_tolerance
)) {
923 pr_debug("clock: found new least error %d\n", min_e
);
927 * Since we're counting n down, a m underflow means we
928 * can bail out completely (since as n decreases in
929 * the next iteration, there's no way that m can
930 * increase beyond the current m)
932 if (r
& DPLL_MULT_UNDERFLOW
)
937 pr_debug("clock: error: target rate or tolerance too low\n");
941 clk
->dpll_data
->last_rounded_m
= min_e_m
;
942 clk
->dpll_data
->last_rounded_n
= min_e_n
;
943 clk
->dpll_data
->last_rounded_rate
=
944 _dpll_compute_new_rate(clk
->parent
->rate
, min_e_m
, min_e_n
);
946 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
947 min_e
, min_e_m
, min_e_n
);
948 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
949 clk
->dpll_data
->last_rounded_rate
, target_rate
);
951 return clk
->dpll_data
->last_rounded_rate
;
954 /*-------------------------------------------------------------------------
955 * Omap2 clock reset and init functions
956 *-------------------------------------------------------------------------*/
958 #ifdef CONFIG_OMAP_RESET_CLOCKS
959 void omap2_clk_disable_unused(struct clk
*clk
)
963 v
= (clk
->flags
& INVERT_ENABLE
) ? (1 << clk
->enable_bit
) : 0;
965 regval32
= __raw_readl(clk
->enable_reg
);
966 if ((regval32
& (1 << clk
->enable_bit
)) == v
)
969 printk(KERN_INFO
"Disabling unused clock \"%s\"\n", clk
->name
);
970 _omap2_clk_disable(clk
);