2 * linux/arch/arm/mach-omap2/clock.h
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
17 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
19 #include <linux/kernel.h>
20 #include <linux/list.h>
22 #include <linux/clkdev.h>
23 #include <linux/clk-provider.h>
30 #define CLK(dev, con, ck, cp) \
40 /* Platform flags for the clkdev-OMAP integration code */
41 #define CK_242X (1 << 0)
42 #define CK_243X (1 << 1) /* 243x, 253x */
43 #define CK_3430ES1 (1 << 2) /* 34xxES1 only */
44 #define CK_3430ES2PLUS (1 << 3) /* 34xxES2, ES3, non-Sitara 35xx only */
45 #define CK_AM35XX (1 << 4) /* Sitara AM35xx */
46 #define CK_36XX (1 << 5) /* 36xx/37xx-specific clocks */
47 #define CK_443X (1 << 6)
48 #define CK_TI816X (1 << 7)
49 #define CK_446X (1 << 8)
50 #define CK_AM33XX (1 << 9) /* AM33xx specific clocks */
53 #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
54 #define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX)
57 #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
59 #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
60 static struct clk _name = { \
62 .hw = &_name##_hw.hw, \
63 .parent_names = _parent_array_name, \
64 .num_parents = ARRAY_SIZE(_parent_array_name), \
65 .ops = &_clkops_name, \
68 #define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
69 static struct clk_hw_omap _name##_hw = { \
73 .clkdm_name = _clkdm_name, \
76 #define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \
77 _clksel_reg, _clksel_mask, \
78 _parent_names, _ops) \
79 static struct clk _name; \
80 static struct clk_hw_omap _name##_hw = { \
85 .clksel_reg = _clksel_reg, \
86 .clksel_mask = _clksel_mask, \
87 .clkdm_name = _clkdm_name, \
89 DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
91 #define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \
92 _clksel_reg, _clksel_mask, \
93 _enable_reg, _enable_bit, \
94 _hwops, _parent_names, _ops) \
95 static struct clk _name; \
96 static struct clk_hw_omap _name##_hw = { \
101 .enable_reg = _enable_reg, \
102 .enable_bit = _enable_bit, \
104 .clksel_reg = _clksel_reg, \
105 .clksel_mask = _clksel_mask, \
106 .clkdm_name = _clkdm_name, \
108 DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
110 #define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \
111 _parent_ptr, _flags, \
112 _clksel_reg, _clksel_mask) \
113 static const struct clksel _name##_div[] = { \
115 .parent = _parent_ptr, \
116 .rates = div31_1to31_rates \
118 { .parent = NULL }, \
120 static struct clk _name; \
121 static const char *_name##_parent_names[] = { \
124 static struct clk_hw_omap _name##_hw = { \
128 .clksel = _name##_div, \
129 .clksel_reg = _clksel_reg, \
130 .clksel_mask = _clksel_mask, \
131 .ops = &clkhwops_omap4_dpllmx, \
133 DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops);
135 /* struct clksel_rate.flags possibilities */
136 #define RATE_IN_242X (1 << 0)
137 #define RATE_IN_243X (1 << 1)
138 #define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
139 #define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
140 #define RATE_IN_36XX (1 << 4)
141 #define RATE_IN_4430 (1 << 5)
142 #define RATE_IN_TI816X (1 << 6)
143 #define RATE_IN_4460 (1 << 7)
144 #define RATE_IN_AM33XX (1 << 8)
145 #define RATE_IN_TI814X (1 << 9)
147 #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
148 #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
149 #define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
150 #define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
152 /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
153 #define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
157 * struct clksel_rate - register bitfield values corresponding to clk divisors
158 * @val: register bitfield value (shifted to bit 0)
159 * @div: clock divisor corresponding to @val
160 * @flags: (see "struct clksel_rate.flags possibilities" above)
162 * @val should match the value of a read from struct clk.clksel_reg
163 * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
165 * @div is the divisor that should be applied to the parent clock's rate
166 * to produce the current clock's rate.
175 * struct clksel - available parent clocks, and a pointer to their divisors
176 * @parent: struct clk * to a possible parent clock
177 * @rates: available divisors for this parent clock
179 * A struct clksel is always associated with one or more struct clks
180 * and one or more struct clksel_rates.
184 const struct clksel_rate
*rates
;
188 * struct dpll_data - DPLL registers and integration data
189 * @mult_div1_reg: register containing the DPLL M and N bitfields
190 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
191 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
192 * @clk_bypass: struct clk pointer to the clock's bypass clock input
193 * @clk_ref: struct clk pointer to the clock's reference clock input
194 * @control_reg: register containing the DPLL mode bitfield
195 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
196 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
197 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
198 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
199 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
200 * @min_divider: minimum valid non-bypass divider value (actual)
201 * @max_divider: maximum valid non-bypass divider value (actual)
202 * @modes: possible values of @enable_mask
203 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
204 * @idlest_reg: register containing the DPLL idle status bitfield
205 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
206 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
207 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
208 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
209 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
210 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
211 * @flags: DPLL type/features (see below)
213 * Possible values for @flags:
214 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
216 * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
218 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
219 * correct to only have one @clk_bypass pointer.
221 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
222 * @last_rounded_n) should be separated from the runtime-fixed fields
223 * and placed into a different structure, so that the runtime-fixed data
224 * can be placed into read-only space.
227 void __iomem
*mult_div1_reg
;
230 struct clk
*clk_bypass
;
232 void __iomem
*control_reg
;
234 unsigned long last_rounded_rate
;
241 void __iomem
*autoidle_reg
;
242 void __iomem
*idlest_reg
;
255 * struct clk.flags possibilities
257 * XXX document the rest of the clock flags here
259 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
260 * bits share the same register. This flag allows the
261 * omap4_dpllmx*() code to determine which GATE_CTRL bit field
262 * should be used. This is a temporary solution - a better approach
263 * would be to associate clock type-specific data with the clock,
264 * similar to the struct dpll_data approach.
266 #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
267 #define CLOCK_IDLE_CONTROL (1 << 1)
268 #define CLOCK_NO_IDLE_PARENT (1 << 2)
269 #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
270 #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
271 #define CLOCK_CLKOUTX2 (1 << 5)
274 * struct clk_hw_omap - OMAP struct clk
275 * @node: list_head connecting this clock into the full clock list
276 * @enable_reg: register to write to enable the clock (see @enable_bit)
277 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
278 * @flags: see "struct clk.flags possibilities" above
279 * @clksel_reg: for clksel clks, register va containing src/divisor select
280 * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
281 * @clksel: for clksel clks, pointer to struct clksel for this clock
282 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
283 * @clkdm_name: clockdomain name that this clock is contained in
284 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
285 * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
286 * @src_offset: bitshift for source selection bitfield (OMAP1 only)
288 * XXX @rate_offset, @src_offset should probably be removed and OMAP1
289 * clock code converted to use clksel.
293 struct clk_hw_omap_ops
;
297 struct list_head node
;
298 unsigned long fixed_rate
;
300 void __iomem
*enable_reg
;
303 void __iomem
*clksel_reg
;
305 const struct clksel
*clksel
;
306 struct dpll_data
*dpll_data
;
307 const char *clkdm_name
;
308 struct clockdomain
*clkdm
;
309 const struct clk_hw_omap_ops
*ops
;
312 struct clk_hw_omap_ops
{
313 void (*find_idlest
)(struct clk_hw_omap
*oclk
,
314 void __iomem
**idlest_reg
,
315 u8
*idlest_bit
, u8
*idlest_val
);
316 void (*find_companion
)(struct clk_hw_omap
*oclk
,
317 void __iomem
**other_reg
,
319 void (*allow_idle
)(struct clk_hw_omap
*oclk
);
320 void (*deny_idle
)(struct clk_hw_omap
*oclk
);
323 unsigned long omap_fixed_divisor_recalc(struct clk_hw
*hw
,
324 unsigned long parent_rate
);
326 /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
327 #define CORE_CLK_SRC_32K 0x0
328 #define CORE_CLK_SRC_DPLL 0x1
329 #define CORE_CLK_SRC_DPLL_X2 0x2
331 /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
332 #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
333 #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
334 #define OMAP2XXX_EN_DPLL_LOCKED 0x3
336 /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
337 #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
338 #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
339 #define OMAP3XXX_EN_DPLL_LOCKED 0x7
341 /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
342 #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
343 #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
344 #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
345 #define OMAP4XXX_EN_DPLL_LOCKED 0x7
347 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
348 #define DPLL_LOW_POWER_STOP 0x1
349 #define DPLL_LOW_POWER_BYPASS 0x5
350 #define DPLL_LOCKED 0x7
352 /* DPLL Type and DCO Selection Flags */
353 #define DPLL_J_TYPE 0x1
355 long omap2_dpll_round_rate(struct clk_hw
*hw
, unsigned long target_rate
,
356 unsigned long *parent_rate
);
357 unsigned long omap3_dpll_recalc(struct clk_hw
*hw
, unsigned long parent_rate
);
358 int omap3_noncore_dpll_enable(struct clk_hw
*hw
);
359 void omap3_noncore_dpll_disable(struct clk_hw
*hw
);
360 int omap3_noncore_dpll_set_rate(struct clk_hw
*hw
, unsigned long rate
,
361 unsigned long parent_rate
);
362 u32
omap3_dpll_autoidle_read(struct clk_hw_omap
*clk
);
363 void omap3_dpll_allow_idle(struct clk_hw_omap
*clk
);
364 void omap3_dpll_deny_idle(struct clk_hw_omap
*clk
);
365 unsigned long omap3_clkoutx2_recalc(struct clk_hw
*hw
,
366 unsigned long parent_rate
);
367 int omap4_dpllmx_gatectrl_read(struct clk_hw_omap
*clk
);
368 void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap
*clk
);
369 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap
*clk
);
370 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw
*hw
,
371 unsigned long parent_rate
);
372 long omap4_dpll_regm4xen_round_rate(struct clk_hw
*hw
,
373 unsigned long target_rate
,
374 unsigned long *parent_rate
);
376 void omap2_init_clk_clkdm(struct clk_hw
*clk
);
377 void __init
omap2_clk_disable_clkdm_control(void);
379 /* clkt_clksel.c public functions */
380 u32
omap2_clksel_round_rate_div(struct clk_hw_omap
*clk
,
381 unsigned long target_rate
,
383 u8
omap2_clksel_find_parent_index(struct clk_hw
*hw
);
384 unsigned long omap2_clksel_recalc(struct clk_hw
*hw
, unsigned long parent_rate
);
385 long omap2_clksel_round_rate(struct clk_hw
*hw
, unsigned long target_rate
,
386 unsigned long *parent_rate
);
387 int omap2_clksel_set_rate(struct clk_hw
*hw
, unsigned long rate
,
388 unsigned long parent_rate
);
389 int omap2_clksel_set_parent(struct clk_hw
*hw
, u8 field_val
);
391 /* clkt_iclk.c public functions */
392 extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap
*clk
);
393 extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap
*clk
);
395 u8
omap2_init_dpll_parent(struct clk_hw
*hw
);
396 unsigned long omap2_get_dpll_rate(struct clk_hw_omap
*clk
);
398 int omap2_dflt_clk_enable(struct clk_hw
*hw
);
399 void omap2_dflt_clk_disable(struct clk_hw
*hw
);
400 int omap2_dflt_clk_is_enabled(struct clk_hw
*hw
);
401 void omap2_clk_dflt_find_companion(struct clk_hw_omap
*clk
,
402 void __iomem
**other_reg
,
404 void omap2_clk_dflt_find_idlest(struct clk_hw_omap
*clk
,
405 void __iomem
**idlest_reg
,
406 u8
*idlest_bit
, u8
*idlest_val
);
407 void omap2_init_clk_hw_omap_clocks(struct clk
*clk
);
408 int omap2_clk_enable_autoidle_all(void);
409 int omap2_clk_disable_autoidle_all(void);
410 void omap2_clk_enable_init_clocks(const char **clk_names
, u8 num_clocks
);
411 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name
);
412 void omap2_clk_print_new_rates(const char *hfclkin_ck_name
,
413 const char *core_ck_name
,
414 const char *mpu_ck_name
);
418 extern const struct clkops clkops_omap2_dflt_wait
;
419 extern const struct clkops clkops_dummy
;
420 extern const struct clkops clkops_omap2_dflt
;
422 extern struct clk_functions omap2_clk_functions
;
424 extern const struct clksel_rate gpt_32k_rates
[];
425 extern const struct clksel_rate gpt_sys_rates
[];
426 extern const struct clksel_rate gfx_l3_rates
[];
427 extern const struct clksel_rate dsp_ick_rates
[];
428 extern struct clk dummy_ck
;
430 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll
;
431 extern const struct clk_hw_omap_ops clkhwops_iclk_wait
;
432 extern const struct clk_hw_omap_ops clkhwops_wait
;
433 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx
;
434 extern const struct clk_hw_omap_ops clkhwops_iclk
;
435 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait
;
436 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait
;
437 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait
;
438 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait
;
439 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait
;
440 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait
;
441 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait
;
442 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait
;
443 extern const struct clk_hw_omap_ops clkhwops_apll54
;
444 extern const struct clk_hw_omap_ops clkhwops_apll96
;
445 extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll
;
446 extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait
;
448 /* clksel_rate blocks shared between OMAP44xx and AM33xx */
449 extern const struct clksel_rate div_1_0_rates
[];
450 extern const struct clksel_rate div3_1to4_rates
[];
451 extern const struct clksel_rate div_1_1_rates
[];
452 extern const struct clksel_rate div_1_2_rates
[];
453 extern const struct clksel_rate div_1_3_rates
[];
454 extern const struct clksel_rate div_1_4_rates
[];
455 extern const struct clksel_rate div31_1to31_rates
[];
457 extern int am33xx_clk_init(void);
459 extern int omap2_clkops_enable_clkdm(struct clk_hw
*hw
);
460 extern void omap2_clkops_disable_clkdm(struct clk_hw
*hw
);