arch/arm/mach-omap2/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock.h
   3  *
   4  *  Copyright (C) 2005-2009 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2011 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
  17 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
  18
  19 #include <linux/kernel.h>
  20 #include <linux/list.h>
  21
  22 #include <linux/clkdev.h>
  23
  24 struct omap_clk {
  25         u16                             cpu;
  26         struct clk_lookup               lk;
  27 };
  28
  29 #define CLK(dev, con, ck, cp)           \
  30         {                               \
  31                  .cpu = cp,             \
  32                 .lk = {                 \
  33                         .dev_id = dev,  \
  34                         .con_id = con,  \
  35                         .clk = ck,      \
  36                 },                      \
  37         }
  38
  39 /* Platform flags for the clkdev-OMAP integration code */
  40 #define CK_242X         (1 << 0)
  41 #define CK_243X         (1 << 1)        /* 243x, 253x */
  42 #define CK_3430ES1      (1 << 2)        /* 34xxES1 only */
  43 #define CK_3430ES2PLUS  (1 << 3)        /* 34xxES2, ES3, non-Sitara 35xx only */
  44 #define CK_AM35XX       (1 << 4)        /* Sitara AM35xx */
  45 #define CK_36XX         (1 << 5)        /* 36xx/37xx-specific clocks */
  46 #define CK_443X         (1 << 6)
  47 #define CK_TI816X       (1 << 7)
  48 #define CK_446X         (1 << 8)
  49 #define CK_AM33XX       (1 << 9)        /* AM33xx specific clocks */
  50
  51
  52 #define CK_34XX         (CK_3430ES1 | CK_3430ES2PLUS)
  53 #define CK_3XXX         (CK_34XX | CK_AM35XX | CK_36XX)
  54
  55 struct module;
  56 struct clk;
  57 struct clockdomain;
  58
  59 /* Temporary, needed during the common clock framework conversion */
  60 #define __clk_get_name(clk)     (clk->name)
  61 #define __clk_get_parent(clk)   (clk->parent)
  62 #define __clk_get_rate(clk)     (clk->rate)
  63
  64 /**
  65  * struct clkops - some clock function pointers
  66  * @enable: fn ptr that enables the current clock in hardware
  67  * @disable: fn ptr that enables the current clock in hardware
  68  * @find_idlest: function returning the IDLEST register for the clock's IP blk
  69  * @find_companion: function returning the "companion" clk reg for the clock
  70  * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
  71  * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
  72  *
  73  * A "companion" clk is an accompanying clock to the one being queried
  74  * that must be enabled for the IP module connected to the clock to
  75  * become accessible by the hardware.  Neither @find_idlest nor
  76  * @find_companion should be needed; that information is IP
  77  * block-specific; the hwmod code has been created to handle this, but
  78  * until hwmod data is ready and drivers have been converted to use PM
  79  * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
  80  * @find_companion must, unfortunately, remain.
  81  */
  82 struct clkops {
  83         int                     (*enable)(struct clk *);
  84         void                    (*disable)(struct clk *);
  85         void                    (*find_idlest)(struct clk *, void __iomem **,
  86                                                u8 *, u8 *);
  87         void                    (*find_companion)(struct clk *, void __iomem **,
  88                                                   u8 *);
  89         void                    (*allow_idle)(struct clk *);
  90         void                    (*deny_idle)(struct clk *);
  91 };
  92
  93 /* struct clksel_rate.flags possibilities */
  94 #define RATE_IN_242X            (1 << 0)
  95 #define RATE_IN_243X            (1 << 1)
  96 #define RATE_IN_3430ES1         (1 << 2)        /* 3430ES1 rates only */
  97 #define RATE_IN_3430ES2PLUS     (1 << 3)        /* 3430 ES >= 2 rates only */
  98 #define RATE_IN_36XX            (1 << 4)
  99 #define RATE_IN_4430            (1 << 5)
 100 #define RATE_IN_TI816X          (1 << 6)
 101 #define RATE_IN_4460            (1 << 7)
 102 #define RATE_IN_AM33XX          (1 << 8)
 103 #define RATE_IN_TI814X          (1 << 9)
 104
 105 #define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
 106 #define RATE_IN_34XX            (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
 107 #define RATE_IN_3XXX            (RATE_IN_34XX | RATE_IN_36XX)
 108 #define RATE_IN_44XX            (RATE_IN_4430 | RATE_IN_4460)
 109
 110 /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
 111 #define RATE_IN_3430ES2PLUS_36XX        (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
 112
 113
 114 /**
 115  * struct clksel_rate - register bitfield values corresponding to clk divisors
 116  * @val: register bitfield value (shifted to bit 0)
 117  * @div: clock divisor corresponding to @val
 118  * @flags: (see "struct clksel_rate.flags possibilities" above)
 119  *
 120  * @val should match the value of a read from struct clk.clksel_reg
 121  * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
 122  *
 123  * @div is the divisor that should be applied to the parent clock's rate
 124  * to produce the current clock's rate.
 125  */
 126 struct clksel_rate {
 127         u32                     val;
 128         u8                      div;
 129         u16                     flags;
 130 };
 131
 132 /**
 133  * struct clksel - available parent clocks, and a pointer to their divisors
 134  * @parent: struct clk * to a possible parent clock
 135  * @rates: available divisors for this parent clock
 136  *
 137  * A struct clksel is always associated with one or more struct clks
 138  * and one or more struct clksel_rates.
 139  */
 140 struct clksel {
 141         struct clk               *parent;
 142         const struct clksel_rate *rates;
 143 };
 144
 145 /**
 146  * struct dpll_data - DPLL registers and integration data
 147  * @mult_div1_reg: register containing the DPLL M and N bitfields
 148  * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
 149  * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
 150  * @clk_bypass: struct clk pointer to the clock's bypass clock input
 151  * @clk_ref: struct clk pointer to the clock's reference clock input
 152  * @control_reg: register containing the DPLL mode bitfield
 153  * @enable_mask: mask of the DPLL mode bitfield in @control_reg
 154  * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
 155  * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
 156  * @max_multiplier: maximum valid non-bypass multiplier value (actual)
 157  * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
 158  * @min_divider: minimum valid non-bypass divider value (actual)
 159  * @max_divider: maximum valid non-bypass divider value (actual)
 160  * @modes: possible values of @enable_mask
 161  * @autoidle_reg: register containing the DPLL autoidle mode bitfield
 162  * @idlest_reg: register containing the DPLL idle status bitfield
 163  * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
 164  * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
 165  * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
 166  * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
 167  * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
 168  * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
 169  * @flags: DPLL type/features (see below)
 170  *
 171  * Possible values for @flags:
 172  * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
 173  *
 174  * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
 175  *
 176  * XXX Some DPLLs have multiple bypass inputs, so it's not technically
 177  * correct to only have one @clk_bypass pointer.
 178  *
 179  * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
 180  * @last_rounded_n) should be separated from the runtime-fixed fields
 181  * and placed into a different structure, so that the runtime-fixed data
 182  * can be placed into read-only space.
 183  */
 184 struct dpll_data {
 185         void __iomem            *mult_div1_reg;
 186         u32                     mult_mask;
 187         u32                     div1_mask;
 188         struct clk              *clk_bypass;
 189         struct clk              *clk_ref;
 190         void __iomem            *control_reg;
 191         u32                     enable_mask;
 192         unsigned long           last_rounded_rate;
 193         u16                     last_rounded_m;
 194         u16                     max_multiplier;
 195         u8                      last_rounded_n;
 196         u8                      min_divider;
 197         u16                     max_divider;
 198         u8                      modes;
 199         void __iomem            *autoidle_reg;
 200         void __iomem            *idlest_reg;
 201         u32                     autoidle_mask;
 202         u32                     freqsel_mask;
 203         u32                     idlest_mask;
 204         u32                     dco_mask;
 205         u32                     sddiv_mask;
 206         u8                      auto_recal_bit;
 207         u8                      recal_en_bit;
 208         u8                      recal_st_bit;
 209         u8                      flags;
 210 };
 211
 212 /*
 213  * struct clk.flags possibilities
 214  *
 215  * XXX document the rest of the clock flags here
 216  *
 217  * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
 218  *     bits share the same register.  This flag allows the
 219  *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
 220  *     should be used.  This is a temporary solution - a better approach
 221  *     would be to associate clock type-specific data with the clock,
 222  *     similar to the struct dpll_data approach.
 223  */
 224 #define ENABLE_REG_32BIT        (1 << 0)        /* Use 32-bit access */
 225 #define CLOCK_IDLE_CONTROL      (1 << 1)
 226 #define CLOCK_NO_IDLE_PARENT    (1 << 2)
 227 #define ENABLE_ON_INIT          (1 << 3)        /* Enable upon framework init */
 228 #define INVERT_ENABLE           (1 << 4)        /* 0 enables, 1 disables */
 229 #define CLOCK_CLKOUTX2          (1 << 5)
 230
 231 /**
 232  * struct clk - OMAP struct clk
 233  * @node: list_head connecting this clock into the full clock list
 234  * @ops: struct clkops * for this clock
 235  * @name: the name of the clock in the hardware (used in hwmod data and debug)
 236  * @parent: pointer to this clock's parent struct clk
 237  * @children: list_head connecting to the child clks' @sibling list_heads
 238  * @sibling: list_head connecting this clk to its parent clk's @children
 239  * @rate: current clock rate
 240  * @enable_reg: register to write to enable the clock (see @enable_bit)
 241  * @recalc: fn ptr that returns the clock's current rate
 242  * @set_rate: fn ptr that can change the clock's current rate
 243  * @round_rate: fn ptr that can round the clock's current rate
 244  * @init: fn ptr to do clock-specific initialization
 245  * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
 246  * @usecount: number of users that have requested this clock to be enabled
 247  * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
 248  * @flags: see "struct clk.flags possibilities" above
 249  * @clksel_reg: for clksel clks, register va containing src/divisor select
 250  * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
 251  * @clksel: for clksel clks, pointer to struct clksel for this clock
 252  * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
 253  * @clkdm_name: clockdomain name that this clock is contained in
 254  * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
 255  * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
 256  * @src_offset: bitshift for source selection bitfield (OMAP1 only)
 257  *
 258  * XXX @rate_offset, @src_offset should probably be removed and OMAP1
 259  * clock code converted to use clksel.
 260  *
 261  * XXX @usecount is poorly named.  It should be "enable_count" or
 262  * something similar.  "users" in the description refers to kernel
 263  * code (core code or drivers) that have called clk_enable() and not
 264  * yet called clk_disable(); the usecount of parent clocks is also
 265  * incremented by the clock code when clk_enable() is called on child
 266  * clocks and decremented by the clock code when clk_disable() is
 267  * called on child clocks.
 268  *
 269  * XXX @clkdm, @usecount, @children, @sibling should be marked for
 270  * internal use only.
 271  *
 272  * @children and @sibling are used to optimize parent-to-child clock
 273  * tree traversals.  (child-to-parent traversals use @parent.)
 274  *
 275  * XXX The notion of the clock's current rate probably needs to be
 276  * separated from the clock's target rate.
 277  */
 278 struct clk {
 279         struct list_head        node;
 280         const struct clkops     *ops;
 281         const char              *name;
 282         struct clk              *parent;
 283         struct list_head        children;
 284         struct list_head        sibling;        /* node for children */
 285         unsigned long           rate;
 286         void __iomem            *enable_reg;
 287         unsigned long           (*recalc)(struct clk *);
 288         int                     (*set_rate)(struct clk *, unsigned long);
 289         long                    (*round_rate)(struct clk *, unsigned long);
 290         void                    (*init)(struct clk *);
 291         u8                      enable_bit;
 292         s8                      usecount;
 293         u8                      fixed_div;
 294         u8                      flags;
 295         void __iomem            *clksel_reg;
 296         u32                     clksel_mask;
 297         const struct clksel     *clksel;
 298         struct dpll_data        *dpll_data;
 299         const char              *clkdm_name;
 300         struct clockdomain      *clkdm;
 301 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
 302         struct dentry           *dent;  /* For visible tree hierarchy */
 303 #endif
 304 };
 305
 306 struct clk_functions {
 307         int             (*clk_enable)(struct clk *clk);
 308         void            (*clk_disable)(struct clk *clk);
 309         long            (*clk_round_rate)(struct clk *clk, unsigned long rate);
 310         int             (*clk_set_rate)(struct clk *clk, unsigned long rate);
 311         int             (*clk_set_parent)(struct clk *clk, struct clk *parent);
 312         void            (*clk_allow_idle)(struct clk *clk);
 313         void            (*clk_deny_idle)(struct clk *clk);
 314         void            (*clk_disable_unused)(struct clk *clk);
 315 };
 316
 317 extern int mpurate;
 318
 319 extern int clk_init(struct clk_functions *custom_clocks);
 320 extern void clk_preinit(struct clk *clk);
 321 extern int clk_register(struct clk *clk);
 322 extern void clk_reparent(struct clk *child, struct clk *parent);
 323 extern void clk_unregister(struct clk *clk);
 324 extern void propagate_rate(struct clk *clk);
 325 extern void recalculate_root_clocks(void);
 326 extern unsigned long followparent_recalc(struct clk *clk);
 327 extern void clk_enable_init_clocks(void);
 328 unsigned long omap_fixed_divisor_recalc(struct clk *clk);
 329 extern struct clk *omap_clk_get_by_name(const char *name);
 330 extern int omap_clk_enable_autoidle_all(void);
 331 extern int omap_clk_disable_autoidle_all(void);
 332
 333 extern const struct clkops clkops_null;
 334
 335 extern struct clk dummy_ck;
 336
 337
 338 /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
 339 #define CORE_CLK_SRC_32K                0x0
 340 #define CORE_CLK_SRC_DPLL               0x1
 341 #define CORE_CLK_SRC_DPLL_X2            0x2
 342
 343 /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
 344 #define OMAP2XXX_EN_DPLL_LPBYPASS               0x1
 345 #define OMAP2XXX_EN_DPLL_FRBYPASS               0x2
 346 #define OMAP2XXX_EN_DPLL_LOCKED                 0x3
 347
 348 /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
 349 #define OMAP3XXX_EN_DPLL_LPBYPASS               0x5
 350 #define OMAP3XXX_EN_DPLL_FRBYPASS               0x6
 351 #define OMAP3XXX_EN_DPLL_LOCKED                 0x7
 352
 353 /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
 354 #define OMAP4XXX_EN_DPLL_MNBYPASS               0x4
 355 #define OMAP4XXX_EN_DPLL_LPBYPASS               0x5
 356 #define OMAP4XXX_EN_DPLL_FRBYPASS               0x6
 357 #define OMAP4XXX_EN_DPLL_LOCKED                 0x7
 358
 359 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
 360 #define DPLL_LOW_POWER_STOP     0x1
 361 #define DPLL_LOW_POWER_BYPASS   0x5
 362 #define DPLL_LOCKED             0x7
 363
 364 /* DPLL Type and DCO Selection Flags */
 365 #define DPLL_J_TYPE             0x1
 366
 367 int omap2_clk_enable(struct clk *clk);
 368 void omap2_clk_disable(struct clk *clk);
 369 long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
 370 int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
 371 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
 372 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
 373 unsigned long omap3_dpll_recalc(struct clk *clk);
 374 unsigned long omap3_clkoutx2_recalc(struct clk *clk);
 375 void omap3_dpll_allow_idle(struct clk *clk);
 376 void omap3_dpll_deny_idle(struct clk *clk);
 377 u32 omap3_dpll_autoidle_read(struct clk *clk);
 378 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
 379 int omap3_noncore_dpll_enable(struct clk *clk);
 380 void omap3_noncore_dpll_disable(struct clk *clk);
 381 int omap4_dpllmx_gatectrl_read(struct clk *clk);
 382 void omap4_dpllmx_allow_gatectrl(struct clk *clk);
 383 void omap4_dpllmx_deny_gatectrl(struct clk *clk);
 384 long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate);
 385 unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk);
 386
 387 #ifdef CONFIG_OMAP_RESET_CLOCKS
 388 void omap2_clk_disable_unused(struct clk *clk);
 389 #else
 390 #define omap2_clk_disable_unused        NULL
 391 #endif
 392
 393 void omap2_init_clk_clkdm(struct clk *clk);
 394 void __init omap2_clk_disable_clkdm_control(void);
 395
 396 /* clkt_clksel.c public functions */
 397 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
 398                                 u32 *new_div);
 399 void omap2_init_clksel_parent(struct clk *clk);
 400 unsigned long omap2_clksel_recalc(struct clk *clk);
 401 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
 402 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
 403 int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
 404
 405 /* clkt_iclk.c public functions */
 406 extern void omap2_clkt_iclk_allow_idle(struct clk *clk);
 407 extern void omap2_clkt_iclk_deny_idle(struct clk *clk);
 408
 409 u32 omap2_get_dpll_rate(struct clk *clk);
 410 void omap2_init_dpll_parent(struct clk *clk);
 411
 412 int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
 413
 414
 415 #ifdef CONFIG_ARCH_OMAP2
 416 void omap2xxx_clk_prepare_for_reboot(void);
 417 #else
 418 static inline void omap2xxx_clk_prepare_for_reboot(void)
 419 {
 420 }
 421 #endif
 422
 423 #ifdef CONFIG_ARCH_OMAP3
 424 void omap3_clk_prepare_for_reboot(void);
 425 #else
 426 static inline void omap3_clk_prepare_for_reboot(void)
 427 {
 428 }
 429 #endif
 430
 431 #ifdef CONFIG_ARCH_OMAP4
 432 void omap4_clk_prepare_for_reboot(void);
 433 #else
 434 static inline void omap4_clk_prepare_for_reboot(void)
 435 {
 436 }
 437 #endif
 438
 439 int omap2_dflt_clk_enable(struct clk *clk);
 440 void omap2_dflt_clk_disable(struct clk *clk);
 441 void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
 442                                    u8 *other_bit);
 443 void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
 444                                 u8 *idlest_bit, u8 *idlest_val);
 445 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
 446 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
 447                                const char *core_ck_name,
 448                                const char *mpu_ck_name);
 449
 450 extern u16 cpu_mask;
 451
 452 extern const struct clkops clkops_omap2_dflt_wait;
 453 extern const struct clkops clkops_dummy;
 454 extern const struct clkops clkops_omap2_dflt;
 455
 456 extern struct clk_functions omap2_clk_functions;
 457 extern struct clk *vclk, *sclk;
 458
 459 extern const struct clksel_rate gpt_32k_rates[];
 460 extern const struct clksel_rate gpt_sys_rates[];
 461 extern const struct clksel_rate gfx_l3_rates[];
 462 extern const struct clksel_rate dsp_ick_rates[];
 463
 464 extern const struct clkops clkops_omap2_iclk_dflt_wait;
 465 extern const struct clkops clkops_omap2_iclk_dflt;
 466 extern const struct clkops clkops_omap2_iclk_idle_only;
 467 extern const struct clkops clkops_omap2_mdmclk_dflt_wait;
 468 extern const struct clkops clkops_omap2xxx_dpll_ops;
 469 extern const struct clkops clkops_omap3_noncore_dpll_ops;
 470 extern const struct clkops clkops_omap3_core_dpll_ops;
 471 extern const struct clkops clkops_omap4_dpllmx_ops;
 472
 473 /* clksel_rate blocks shared between OMAP44xx and AM33xx */
 474 extern const struct clksel_rate div_1_0_rates[];
 475 extern const struct clksel_rate div_1_1_rates[];
 476 extern const struct clksel_rate div_1_2_rates[];
 477 extern const struct clksel_rate div_1_3_rates[];
 478 extern const struct clksel_rate div_1_4_rates[];
 479 extern const struct clksel_rate div31_1to31_rates[];
 480
 481 /* clocks shared between various OMAP SoCs */
 482 extern struct clk virt_19200000_ck;
 483 extern struct clk virt_26000000_ck;
 484
 485 extern int am33xx_clk_init(void);
 486
 487 #endif