arch/arm/mach-omap2/clock2420_data.c

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock2420_data.c
   3  *
   4  *  Copyright (C) 2005-2009 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2010 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/clk.h>
  18 #include <linux/list.h>
  19
  20 #include <plat/clkdev_omap.h>
  21
  22 #include "clock.h"
  23 #include "clock2xxx.h"
  24 #include "opp2xxx.h"
  25 #include "prm.h"
  26 #include "cm.h"
  27 #include "prm-regbits-24xx.h"
  28 #include "cm-regbits-24xx.h"
  29 #include "sdrc.h"
  30 #include "control.h"
  31
  32 #define OMAP_CM_REGADDR                 OMAP2420_CM_REGADDR
  33
  34 /*
  35  * 2420 clock tree.
  36  *
  37  * NOTE:In many cases here we are assigning a 'default' parent. In many
  38  *      cases the parent is selectable. The get/set parent calls will also
  39  *      switch sources.
  40  *
  41  *      Many some clocks say always_enabled, but they can be auto idled for
  42  *      power savings. They will always be available upon clock request.
  43  *
  44  *      Several sources are given initial rates which may be wrong, this will
  45  *      be fixed up in the init func.
  46  *
  47  *      Things are broadly separated below by clock domains. It is
  48  *      noteworthy that most periferals have dependencies on multiple clock
  49  *      domains. Many get their interface clocks from the L4 domain, but get
  50  *      functional clocks from fixed sources or other core domain derived
  51  *      clocks.
  52  */
  53
  54 /* Base external input clocks */
  55 static struct clk func_32k_ck = {
  56         .name           = "func_32k_ck",
  57         .ops            = &clkops_null,
  58         .rate           = 32000,
  59         .clkdm_name     = "wkup_clkdm",
  60 };
  61
  62 static struct clk secure_32k_ck = {
  63         .name           = "secure_32k_ck",
  64         .ops            = &clkops_null,
  65         .rate           = 32768,
  66         .clkdm_name     = "wkup_clkdm",
  67 };
  68
  69 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
  70 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
  71         .name           = "osc_ck",
  72         .ops            = &clkops_oscck,
  73         .clkdm_name     = "wkup_clkdm",
  74         .recalc         = &omap2_osc_clk_recalc,
  75 };
  76
  77 /* Without modem likely 12MHz, with modem likely 13MHz */
  78 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
  79         .name           = "sys_ck",             /* ~ ref_clk also */
  80         .ops            = &clkops_null,
  81         .parent         = &osc_ck,
  82         .clkdm_name     = "wkup_clkdm",
  83         .recalc         = &omap2xxx_sys_clk_recalc,
  84 };
  85
  86 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
  87         .name           = "alt_ck",
  88         .ops            = &clkops_null,
  89         .rate           = 54000000,
  90         .clkdm_name     = "wkup_clkdm",
  91 };
  92
  93 /* Optional external clock input for McBSP CLKS */
  94 static struct clk mcbsp_clks = {
  95         .name           = "mcbsp_clks",
  96         .ops            = &clkops_null,
  97 };
  98
  99 /*
 100  * Analog domain root source clocks
 101  */
 102
 103 /* dpll_ck, is broken out in to special cases through clksel */
 104 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
 105  * deal with this
 106  */
 107
 108 static struct dpll_data dpll_dd = {
 109         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 110         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 111         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 112         .clk_bypass             = &sys_ck,
 113         .clk_ref                = &sys_ck,
 114         .control_reg            = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 115         .enable_mask            = OMAP24XX_EN_DPLL_MASK,
 116         .max_multiplier         = 1023,
 117         .min_divider            = 1,
 118         .max_divider            = 16,
 119         .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 120 };
 121
 122 /*
 123  * XXX Cannot add round_rate here yet, as this is still a composite clock,
 124  * not just a DPLL
 125  */
 126 static struct clk dpll_ck = {
 127         .name           = "dpll_ck",
 128         .ops            = &clkops_null,
 129         .parent         = &sys_ck,              /* Can be func_32k also */
 130         .dpll_data      = &dpll_dd,
 131         .clkdm_name     = "wkup_clkdm",
 132         .recalc         = &omap2_dpllcore_recalc,
 133         .set_rate       = &omap2_reprogram_dpllcore,
 134 };
 135
 136 static struct clk apll96_ck = {
 137         .name           = "apll96_ck",
 138         .ops            = &clkops_apll96,
 139         .parent         = &sys_ck,
 140         .rate           = 96000000,
 141         .flags          = ENABLE_ON_INIT,
 142         .clkdm_name     = "wkup_clkdm",
 143         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 144         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 145 };
 146
 147 static struct clk apll54_ck = {
 148         .name           = "apll54_ck",
 149         .ops            = &clkops_apll54,
 150         .parent         = &sys_ck,
 151         .rate           = 54000000,
 152         .flags          = ENABLE_ON_INIT,
 153         .clkdm_name     = "wkup_clkdm",
 154         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 155         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 156 };
 157
 158 /*
 159  * PRCM digital base sources
 160  */
 161
 162 /* func_54m_ck */
 163
 164 static const struct clksel_rate func_54m_apll54_rates[] = {
 165         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 166         { .div = 0 },
 167 };
 168
 169 static const struct clksel_rate func_54m_alt_rates[] = {
 170         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 171         { .div = 0 },
 172 };
 173
 174 static const struct clksel func_54m_clksel[] = {
 175         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 176         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 177         { .parent = NULL },
 178 };
 179
 180 static struct clk func_54m_ck = {
 181         .name           = "func_54m_ck",
 182         .ops            = &clkops_null,
 183         .parent         = &apll54_ck,   /* can also be alt_clk */
 184         .clkdm_name     = "wkup_clkdm",
 185         .init           = &omap2_init_clksel_parent,
 186         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 187         .clksel_mask    = OMAP24XX_54M_SOURCE_MASK,
 188         .clksel         = func_54m_clksel,
 189         .recalc         = &omap2_clksel_recalc,
 190 };
 191
 192 static struct clk core_ck = {
 193         .name           = "core_ck",
 194         .ops            = &clkops_null,
 195         .parent         = &dpll_ck,             /* can also be 32k */
 196         .clkdm_name     = "wkup_clkdm",
 197         .recalc         = &followparent_recalc,
 198 };
 199
 200 static struct clk func_96m_ck = {
 201         .name           = "func_96m_ck",
 202         .ops            = &clkops_null,
 203         .parent         = &apll96_ck,
 204         .clkdm_name     = "wkup_clkdm",
 205         .recalc         = &followparent_recalc,
 206 };
 207
 208 /* func_48m_ck */
 209
 210 static const struct clksel_rate func_48m_apll96_rates[] = {
 211         { .div = 2, .val = 0, .flags = RATE_IN_24XX },
 212         { .div = 0 },
 213 };
 214
 215 static const struct clksel_rate func_48m_alt_rates[] = {
 216         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 217         { .div = 0 },
 218 };
 219
 220 static const struct clksel func_48m_clksel[] = {
 221         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 222         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 223         { .parent = NULL }
 224 };
 225
 226 static struct clk func_48m_ck = {
 227         .name           = "func_48m_ck",
 228         .ops            = &clkops_null,
 229         .parent         = &apll96_ck,    /* 96M or Alt */
 230         .clkdm_name     = "wkup_clkdm",
 231         .init           = &omap2_init_clksel_parent,
 232         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 233         .clksel_mask    = OMAP24XX_48M_SOURCE_MASK,
 234         .clksel         = func_48m_clksel,
 235         .recalc         = &omap2_clksel_recalc,
 236         .round_rate     = &omap2_clksel_round_rate,
 237         .set_rate       = &omap2_clksel_set_rate
 238 };
 239
 240 static struct clk func_12m_ck = {
 241         .name           = "func_12m_ck",
 242         .ops            = &clkops_null,
 243         .parent         = &func_48m_ck,
 244         .fixed_div      = 4,
 245         .clkdm_name     = "wkup_clkdm",
 246         .recalc         = &omap_fixed_divisor_recalc,
 247 };
 248
 249 /* Secure timer, only available in secure mode */
 250 static struct clk wdt1_osc_ck = {
 251         .name           = "ck_wdt1_osc",
 252         .ops            = &clkops_null, /* RMK: missing? */
 253         .parent         = &osc_ck,
 254         .recalc         = &followparent_recalc,
 255 };
 256
 257 /*
 258  * The common_clkout* clksel_rate structs are common to
 259  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 260  * sys_clkout2_* are 2420-only, so the
 261  * clksel_rate flags fields are inaccurate for those clocks. This is
 262  * harmless since access to those clocks are gated by the struct clk
 263  * flags fields, which mark them as 2420-only.
 264  */
 265 static const struct clksel_rate common_clkout_src_core_rates[] = {
 266         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 267         { .div = 0 }
 268 };
 269
 270 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 271         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 272         { .div = 0 }
 273 };
 274
 275 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 276         { .div = 1, .val = 2, .flags = RATE_IN_24XX },
 277         { .div = 0 }
 278 };
 279
 280 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 281         { .div = 1, .val = 3, .flags = RATE_IN_24XX },
 282         { .div = 0 }
 283 };
 284
 285 static const struct clksel common_clkout_src_clksel[] = {
 286         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 287         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 288         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 289         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 290         { .parent = NULL }
 291 };
 292
 293 static struct clk sys_clkout_src = {
 294         .name           = "sys_clkout_src",
 295         .ops            = &clkops_omap2_dflt,
 296         .parent         = &func_54m_ck,
 297         .clkdm_name     = "wkup_clkdm",
 298         .enable_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
 299         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 300         .init           = &omap2_init_clksel_parent,
 301         .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
 302         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 303         .clksel         = common_clkout_src_clksel,
 304         .recalc         = &omap2_clksel_recalc,
 305         .round_rate     = &omap2_clksel_round_rate,
 306         .set_rate       = &omap2_clksel_set_rate
 307 };
 308
 309 static const struct clksel_rate common_clkout_rates[] = {
 310         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 311         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 312         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 313         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 314         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 315         { .div = 0 },
 316 };
 317
 318 static const struct clksel sys_clkout_clksel[] = {
 319         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 320         { .parent = NULL }
 321 };
 322
 323 static struct clk sys_clkout = {
 324         .name           = "sys_clkout",
 325         .ops            = &clkops_null,
 326         .parent         = &sys_clkout_src,
 327         .clkdm_name     = "wkup_clkdm",
 328         .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
 329         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 330         .clksel         = sys_clkout_clksel,
 331         .recalc         = &omap2_clksel_recalc,
 332         .round_rate     = &omap2_clksel_round_rate,
 333         .set_rate       = &omap2_clksel_set_rate
 334 };
 335
 336 /* In 2430, new in 2420 ES2 */
 337 static struct clk sys_clkout2_src = {
 338         .name           = "sys_clkout2_src",
 339         .ops            = &clkops_omap2_dflt,
 340         .parent         = &func_54m_ck,
 341         .clkdm_name     = "wkup_clkdm",
 342         .enable_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
 343         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 344         .init           = &omap2_init_clksel_parent,
 345         .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
 346         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 347         .clksel         = common_clkout_src_clksel,
 348         .recalc         = &omap2_clksel_recalc,
 349         .round_rate     = &omap2_clksel_round_rate,
 350         .set_rate       = &omap2_clksel_set_rate
 351 };
 352
 353 static const struct clksel sys_clkout2_clksel[] = {
 354         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 355         { .parent = NULL }
 356 };
 357
 358 /* In 2430, new in 2420 ES2 */
 359 static struct clk sys_clkout2 = {
 360         .name           = "sys_clkout2",
 361         .ops            = &clkops_null,
 362         .parent         = &sys_clkout2_src,
 363         .clkdm_name     = "wkup_clkdm",
 364         .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
 365         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 366         .clksel         = sys_clkout2_clksel,
 367         .recalc         = &omap2_clksel_recalc,
 368         .round_rate     = &omap2_clksel_round_rate,
 369         .set_rate       = &omap2_clksel_set_rate
 370 };
 371
 372 static struct clk emul_ck = {
 373         .name           = "emul_ck",
 374         .ops            = &clkops_omap2_dflt,
 375         .parent         = &func_54m_ck,
 376         .clkdm_name     = "wkup_clkdm",
 377         .enable_reg     = OMAP2420_PRCM_CLKEMUL_CTRL,
 378         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 379         .recalc         = &followparent_recalc,
 380
 381 };
 382
 383 /*
 384  * MPU clock domain
 385  *      Clocks:
 386  *              MPU_FCLK, MPU_ICLK
 387  *              INT_M_FCLK, INT_M_I_CLK
 388  *
 389  * - Individual clocks are hardware managed.
 390  * - Base divider comes from: CM_CLKSEL_MPU
 391  *
 392  */
 393 static const struct clksel_rate mpu_core_rates[] = {
 394         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 395         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 396         { .div = 4, .val = 4, .flags = RATE_IN_242X },
 397         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 398         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 399         { .div = 0 },
 400 };
 401
 402 static const struct clksel mpu_clksel[] = {
 403         { .parent = &core_ck, .rates = mpu_core_rates },
 404         { .parent = NULL }
 405 };
 406
 407 static struct clk mpu_ck = {    /* Control cpu */
 408         .name           = "mpu_ck",
 409         .ops            = &clkops_null,
 410         .parent         = &core_ck,
 411         .clkdm_name     = "mpu_clkdm",
 412         .init           = &omap2_init_clksel_parent,
 413         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
 414         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
 415         .clksel         = mpu_clksel,
 416         .recalc         = &omap2_clksel_recalc,
 417 };
 418
 419 /*
 420  * DSP (2420-UMA+IVA1) clock domain
 421  * Clocks:
 422  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 423  *
 424  * Won't be too specific here. The core clock comes into this block
 425  * it is divided then tee'ed. One branch goes directly to xyz enable
 426  * controls. The other branch gets further divided by 2 then possibly
 427  * routed into a synchronizer and out of clocks abc.
 428  */
 429 static const struct clksel_rate dsp_fck_core_rates[] = {
 430         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 431         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 432         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 433         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 434         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 435         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 436         { .div = 12, .val = 12, .flags = RATE_IN_242X },
 437         { .div = 0 },
 438 };
 439
 440 static const struct clksel dsp_fck_clksel[] = {
 441         { .parent = &core_ck, .rates = dsp_fck_core_rates },
 442         { .parent = NULL }
 443 };
 444
 445 static struct clk dsp_fck = {
 446         .name           = "dsp_fck",
 447         .ops            = &clkops_omap2_dflt_wait,
 448         .parent         = &core_ck,
 449         .clkdm_name     = "dsp_clkdm",
 450         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
 451         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 452         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 453         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
 454         .clksel         = dsp_fck_clksel,
 455         .recalc         = &omap2_clksel_recalc,
 456 };
 457
 458 /* DSP interface clock */
 459 static const struct clksel_rate dsp_irate_ick_rates[] = {
 460         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 461         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 462         { .div = 0 },
 463 };
 464
 465 static const struct clksel dsp_irate_ick_clksel[] = {
 466         { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
 467         { .parent = NULL }
 468 };
 469
 470 /* This clock does not exist as such in the TRM. */
 471 static struct clk dsp_irate_ick = {
 472         .name           = "dsp_irate_ick",
 473         .ops            = &clkops_null,
 474         .parent         = &dsp_fck,
 475         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 476         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
 477         .clksel         = dsp_irate_ick_clksel,
 478         .recalc         = &omap2_clksel_recalc,
 479 };
 480
 481 /* 2420 only */
 482 static struct clk dsp_ick = {
 483         .name           = "dsp_ick",     /* apparently ipi and isp */
 484         .ops            = &clkops_omap2_dflt_wait,
 485         .parent         = &dsp_irate_ick,
 486         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
 487         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
 488 };
 489
 490 /*
 491  * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
 492  * the C54x, but which is contained in the DSP powerdomain.  Does not
 493  * exist on later OMAPs.
 494  */
 495 static struct clk iva1_ifck = {
 496         .name           = "iva1_ifck",
 497         .ops            = &clkops_omap2_dflt_wait,
 498         .parent         = &core_ck,
 499         .clkdm_name     = "iva1_clkdm",
 500         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
 501         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
 502         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 503         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
 504         .clksel         = dsp_fck_clksel,
 505         .recalc         = &omap2_clksel_recalc,
 506 };
 507
 508 /* IVA1 mpu/int/i/f clocks are /2 of parent */
 509 static struct clk iva1_mpu_int_ifck = {
 510         .name           = "iva1_mpu_int_ifck",
 511         .ops            = &clkops_omap2_dflt_wait,
 512         .parent         = &iva1_ifck,
 513         .clkdm_name     = "iva1_clkdm",
 514         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
 515         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
 516         .fixed_div      = 2,
 517         .recalc         = &omap_fixed_divisor_recalc,
 518 };
 519
 520 /*
 521  * L3 clock domain
 522  * L3 clocks are used for both interface and functional clocks to
 523  * multiple entities. Some of these clocks are completely managed
 524  * by hardware, and some others allow software control. Hardware
 525  * managed ones general are based on directly CLK_REQ signals and
 526  * various auto idle settings. The functional spec sets many of these
 527  * as 'tie-high' for their enables.
 528  *
 529  * I-CLOCKS:
 530  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
 531  *      CAM, HS-USB.
 532  * F-CLOCK
 533  *      SSI.
 534  *
 535  * GPMC memories and SDRC have timing and clock sensitive registers which
 536  * may very well need notification when the clock changes. Currently for low
 537  * operating points, these are taken care of in sleep.S.
 538  */
 539 static const struct clksel_rate core_l3_core_rates[] = {
 540         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 541         { .div = 2, .val = 2, .flags = RATE_IN_242X },
 542         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 543         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
 544         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 545         { .div = 12, .val = 12, .flags = RATE_IN_242X },
 546         { .div = 16, .val = 16, .flags = RATE_IN_242X },
 547         { .div = 0 }
 548 };
 549
 550 static const struct clksel core_l3_clksel[] = {
 551         { .parent = &core_ck, .rates = core_l3_core_rates },
 552         { .parent = NULL }
 553 };
 554
 555 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
 556         .name           = "core_l3_ck",
 557         .ops            = &clkops_null,
 558         .parent         = &core_ck,
 559         .clkdm_name     = "core_l3_clkdm",
 560         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 561         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
 562         .clksel         = core_l3_clksel,
 563         .recalc         = &omap2_clksel_recalc,
 564 };
 565
 566 /* usb_l4_ick */
 567 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
 568         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 569         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 570         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 571         { .div = 0 }
 572 };
 573
 574 static const struct clksel usb_l4_ick_clksel[] = {
 575         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
 576         { .parent = NULL },
 577 };
 578
 579 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
 580 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
 581         .name           = "usb_l4_ick",
 582         .ops            = &clkops_omap2_dflt_wait,
 583         .parent         = &core_l3_ck,
 584         .clkdm_name     = "core_l4_clkdm",
 585         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 586         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
 587         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 588         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
 589         .clksel         = usb_l4_ick_clksel,
 590         .recalc         = &omap2_clksel_recalc,
 591 };
 592
 593 /*
 594  * L4 clock management domain
 595  *
 596  * This domain contains lots of interface clocks from the L4 interface, some
 597  * functional clocks.   Fixed APLL functional source clocks are managed in
 598  * this domain.
 599  */
 600 static const struct clksel_rate l4_core_l3_rates[] = {
 601         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 602         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 603         { .div = 0 }
 604 };
 605
 606 static const struct clksel l4_clksel[] = {
 607         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
 608         { .parent = NULL }
 609 };
 610
 611 static struct clk l4_ck = {             /* used both as an ick and fck */
 612         .name           = "l4_ck",
 613         .ops            = &clkops_null,
 614         .parent         = &core_l3_ck,
 615         .clkdm_name     = "core_l4_clkdm",
 616         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 617         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
 618         .clksel         = l4_clksel,
 619         .recalc         = &omap2_clksel_recalc,
 620 };
 621
 622 /*
 623  * SSI is in L3 management domain, its direct parent is core not l3,
 624  * many core power domain entities are grouped into the L3 clock
 625  * domain.
 626  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
 627  *
 628  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
 629  */
 630 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
 631         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 632         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 633         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 634         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 635         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 636         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 637         { .div = 0 }
 638 };
 639
 640 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
 641         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
 642         { .parent = NULL }
 643 };
 644
 645 static struct clk ssi_ssr_sst_fck = {
 646         .name           = "ssi_fck",
 647         .ops            = &clkops_omap2_dflt_wait,
 648         .parent         = &core_ck,
 649         .clkdm_name     = "core_l3_clkdm",
 650         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 651         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
 652         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 653         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
 654         .clksel         = ssi_ssr_sst_fck_clksel,
 655         .recalc         = &omap2_clksel_recalc,
 656 };
 657
 658 /*
 659  * Presumably this is the same as SSI_ICLK.
 660  * TRM contradicts itself on what clockdomain SSI_ICLK is in
 661  */
 662 static struct clk ssi_l4_ick = {
 663         .name           = "ssi_l4_ick",
 664         .ops            = &clkops_omap2_dflt_wait,
 665         .parent         = &l4_ck,
 666         .clkdm_name     = "core_l4_clkdm",
 667         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 668         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
 669         .recalc         = &followparent_recalc,
 670 };
 671
 672
 673 /*
 674  * GFX clock domain
 675  *      Clocks:
 676  * GFX_FCLK, GFX_ICLK
 677  * GFX_CG1(2d), GFX_CG2(3d)
 678  *
 679  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
 680  * The 2d and 3d clocks run at a hardware determined
 681  * divided value of fclk.
 682  *
 683  */
 684
 685 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
 686 static const struct clksel gfx_fck_clksel[] = {
 687         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
 688         { .parent = NULL },
 689 };
 690
 691 static struct clk gfx_3d_fck = {
 692         .name           = "gfx_3d_fck",
 693         .ops            = &clkops_omap2_dflt_wait,
 694         .parent         = &core_l3_ck,
 695         .clkdm_name     = "gfx_clkdm",
 696         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 697         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
 698         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
 699         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
 700         .clksel         = gfx_fck_clksel,
 701         .recalc         = &omap2_clksel_recalc,
 702         .round_rate     = &omap2_clksel_round_rate,
 703         .set_rate       = &omap2_clksel_set_rate
 704 };
 705
 706 static struct clk gfx_2d_fck = {
 707         .name           = "gfx_2d_fck",
 708         .ops            = &clkops_omap2_dflt_wait,
 709         .parent         = &core_l3_ck,
 710         .clkdm_name     = "gfx_clkdm",
 711         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 712         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
 713         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
 714         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
 715         .clksel         = gfx_fck_clksel,
 716         .recalc         = &omap2_clksel_recalc,
 717 };
 718
 719 static struct clk gfx_ick = {
 720         .name           = "gfx_ick",            /* From l3 */
 721         .ops            = &clkops_omap2_dflt_wait,
 722         .parent         = &core_l3_ck,
 723         .clkdm_name     = "gfx_clkdm",
 724         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
 725         .enable_bit     = OMAP_EN_GFX_SHIFT,
 726         .recalc         = &followparent_recalc,
 727 };
 728
 729 /*
 730  * DSS clock domain
 731  * CLOCKs:
 732  * DSS_L4_ICLK, DSS_L3_ICLK,
 733  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
 734  *
 735  * DSS is both initiator and target.
 736  */
 737 /* XXX Add RATE_NOT_VALIDATED */
 738
 739 static const struct clksel_rate dss1_fck_sys_rates[] = {
 740         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 741         { .div = 0 }
 742 };
 743
 744 static const struct clksel_rate dss1_fck_core_rates[] = {
 745         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 746         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 747         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 748         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 749         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
 750         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
 751         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
 752         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
 753         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
 754         { .div = 16, .val = 16, .flags = RATE_IN_24XX },
 755         { .div = 0 }
 756 };
 757
 758 static const struct clksel dss1_fck_clksel[] = {
 759         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
 760         { .parent = &core_ck, .rates = dss1_fck_core_rates },
 761         { .parent = NULL },
 762 };
 763
 764 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
 765         .name           = "dss_ick",
 766         .ops            = &clkops_omap2_dflt,
 767         .parent         = &l4_ck,       /* really both l3 and l4 */
 768         .clkdm_name     = "dss_clkdm",
 769         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 770         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
 771         .recalc         = &followparent_recalc,
 772 };
 773
 774 static struct clk dss1_fck = {
 775         .name           = "dss1_fck",
 776         .ops            = &clkops_omap2_dflt,
 777         .parent         = &core_ck,             /* Core or sys */
 778         .clkdm_name     = "dss_clkdm",
 779         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 780         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
 781         .init           = &omap2_init_clksel_parent,
 782         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 783         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
 784         .clksel         = dss1_fck_clksel,
 785         .recalc         = &omap2_clksel_recalc,
 786 };
 787
 788 static const struct clksel_rate dss2_fck_sys_rates[] = {
 789         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 790         { .div = 0 }
 791 };
 792
 793 static const struct clksel_rate dss2_fck_48m_rates[] = {
 794         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 795         { .div = 0 }
 796 };
 797
 798 static const struct clksel dss2_fck_clksel[] = {
 799         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
 800         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
 801         { .parent = NULL }
 802 };
 803
 804 static struct clk dss2_fck = {          /* Alt clk used in power management */
 805         .name           = "dss2_fck",
 806         .ops            = &clkops_omap2_dflt,
 807         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
 808         .clkdm_name     = "dss_clkdm",
 809         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 810         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
 811         .init           = &omap2_init_clksel_parent,
 812         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 813         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
 814         .clksel         = dss2_fck_clksel,
 815         .recalc         = &followparent_recalc,
 816 };
 817
 818 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
 819         .name           = "dss_54m_fck",        /* 54m tv clk */
 820         .ops            = &clkops_omap2_dflt_wait,
 821         .parent         = &func_54m_ck,
 822         .clkdm_name     = "dss_clkdm",
 823         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 824         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
 825         .recalc         = &followparent_recalc,
 826 };
 827
 828 /*
 829  * CORE power domain ICLK & FCLK defines.
 830  * Many of the these can have more than one possible parent. Entries
 831  * here will likely have an L4 interface parent, and may have multiple
 832  * functional clock parents.
 833  */
 834 static const struct clksel_rate gpt_alt_rates[] = {
 835         { .div = 1, .val = 2, .flags = RATE_IN_24XX },
 836         { .div = 0 }
 837 };
 838
 839 static const struct clksel omap24xx_gpt_clksel[] = {
 840         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
 841         { .parent = &sys_ck,      .rates = gpt_sys_rates },
 842         { .parent = &alt_ck,      .rates = gpt_alt_rates },
 843         { .parent = NULL },
 844 };
 845
 846 static struct clk gpt1_ick = {
 847         .name           = "gpt1_ick",
 848         .ops            = &clkops_omap2_dflt_wait,
 849         .parent         = &l4_ck,
 850         .clkdm_name     = "core_l4_clkdm",
 851         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 852         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
 853         .recalc         = &followparent_recalc,
 854 };
 855
 856 static struct clk gpt1_fck = {
 857         .name           = "gpt1_fck",
 858         .ops            = &clkops_omap2_dflt_wait,
 859         .parent         = &func_32k_ck,
 860         .clkdm_name     = "core_l4_clkdm",
 861         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 862         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
 863         .init           = &omap2_init_clksel_parent,
 864         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
 865         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
 866         .clksel         = omap24xx_gpt_clksel,
 867         .recalc         = &omap2_clksel_recalc,
 868         .round_rate     = &omap2_clksel_round_rate,
 869         .set_rate       = &omap2_clksel_set_rate
 870 };
 871
 872 static struct clk gpt2_ick = {
 873         .name           = "gpt2_ick",
 874         .ops            = &clkops_omap2_dflt_wait,
 875         .parent         = &l4_ck,
 876         .clkdm_name     = "core_l4_clkdm",
 877         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 878         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
 879         .recalc         = &followparent_recalc,
 880 };
 881
 882 static struct clk gpt2_fck = {
 883         .name           = "gpt2_fck",
 884         .ops            = &clkops_omap2_dflt_wait,
 885         .parent         = &func_32k_ck,
 886         .clkdm_name     = "core_l4_clkdm",
 887         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 888         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
 889         .init           = &omap2_init_clksel_parent,
 890         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 891         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
 892         .clksel         = omap24xx_gpt_clksel,
 893         .recalc         = &omap2_clksel_recalc,
 894 };
 895
 896 static struct clk gpt3_ick = {
 897         .name           = "gpt3_ick",
 898         .ops            = &clkops_omap2_dflt_wait,
 899         .parent         = &l4_ck,
 900         .clkdm_name     = "core_l4_clkdm",
 901         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 902         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
 903         .recalc         = &followparent_recalc,
 904 };
 905
 906 static struct clk gpt3_fck = {
 907         .name           = "gpt3_fck",
 908         .ops            = &clkops_omap2_dflt_wait,
 909         .parent         = &func_32k_ck,
 910         .clkdm_name     = "core_l4_clkdm",
 911         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 912         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
 913         .init           = &omap2_init_clksel_parent,
 914         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 915         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
 916         .clksel         = omap24xx_gpt_clksel,
 917         .recalc         = &omap2_clksel_recalc,
 918 };
 919
 920 static struct clk gpt4_ick = {
 921         .name           = "gpt4_ick",
 922         .ops            = &clkops_omap2_dflt_wait,
 923         .parent         = &l4_ck,
 924         .clkdm_name     = "core_l4_clkdm",
 925         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 926         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
 927         .recalc         = &followparent_recalc,
 928 };
 929
 930 static struct clk gpt4_fck = {
 931         .name           = "gpt4_fck",
 932         .ops            = &clkops_omap2_dflt_wait,
 933         .parent         = &func_32k_ck,
 934         .clkdm_name     = "core_l4_clkdm",
 935         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 936         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
 937         .init           = &omap2_init_clksel_parent,
 938         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 939         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
 940         .clksel         = omap24xx_gpt_clksel,
 941         .recalc         = &omap2_clksel_recalc,
 942 };
 943
 944 static struct clk gpt5_ick = {
 945         .name           = "gpt5_ick",
 946         .ops            = &clkops_omap2_dflt_wait,
 947         .parent         = &l4_ck,
 948         .clkdm_name     = "core_l4_clkdm",
 949         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 950         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
 951         .recalc         = &followparent_recalc,
 952 };
 953
 954 static struct clk gpt5_fck = {
 955         .name           = "gpt5_fck",
 956         .ops            = &clkops_omap2_dflt_wait,
 957         .parent         = &func_32k_ck,
 958         .clkdm_name     = "core_l4_clkdm",
 959         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 960         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
 961         .init           = &omap2_init_clksel_parent,
 962         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 963         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
 964         .clksel         = omap24xx_gpt_clksel,
 965         .recalc         = &omap2_clksel_recalc,
 966 };
 967
 968 static struct clk gpt6_ick = {
 969         .name           = "gpt6_ick",
 970         .ops            = &clkops_omap2_dflt_wait,
 971         .parent         = &l4_ck,
 972         .clkdm_name     = "core_l4_clkdm",
 973         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 974         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
 975         .recalc         = &followparent_recalc,
 976 };
 977
 978 static struct clk gpt6_fck = {
 979         .name           = "gpt6_fck",
 980         .ops            = &clkops_omap2_dflt_wait,
 981         .parent         = &func_32k_ck,
 982         .clkdm_name     = "core_l4_clkdm",
 983         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 984         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
 985         .init           = &omap2_init_clksel_parent,
 986         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 987         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
 988         .clksel         = omap24xx_gpt_clksel,
 989         .recalc         = &omap2_clksel_recalc,
 990 };
 991
 992 static struct clk gpt7_ick = {
 993         .name           = "gpt7_ick",
 994         .ops            = &clkops_omap2_dflt_wait,
 995         .parent         = &l4_ck,
 996         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 997         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
 998         .recalc         = &followparent_recalc,
 999 };
1000
1001 static struct clk gpt7_fck = {
1002         .name           = "gpt7_fck",
1003         .ops            = &clkops_omap2_dflt_wait,
1004         .parent         = &func_32k_ck,
1005         .clkdm_name     = "core_l4_clkdm",
1006         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1007         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
1008         .init           = &omap2_init_clksel_parent,
1009         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1010         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
1011         .clksel         = omap24xx_gpt_clksel,
1012         .recalc         = &omap2_clksel_recalc,
1013 };
1014
1015 static struct clk gpt8_ick = {
1016         .name           = "gpt8_ick",
1017         .ops            = &clkops_omap2_dflt_wait,
1018         .parent         = &l4_ck,
1019         .clkdm_name     = "core_l4_clkdm",
1020         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1021         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1022         .recalc         = &followparent_recalc,
1023 };
1024
1025 static struct clk gpt8_fck = {
1026         .name           = "gpt8_fck",
1027         .ops            = &clkops_omap2_dflt_wait,
1028         .parent         = &func_32k_ck,
1029         .clkdm_name     = "core_l4_clkdm",
1030         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1031         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1032         .init           = &omap2_init_clksel_parent,
1033         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1034         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1035         .clksel         = omap24xx_gpt_clksel,
1036         .recalc         = &omap2_clksel_recalc,
1037 };
1038
1039 static struct clk gpt9_ick = {
1040         .name           = "gpt9_ick",
1041         .ops            = &clkops_omap2_dflt_wait,
1042         .parent         = &l4_ck,
1043         .clkdm_name     = "core_l4_clkdm",
1044         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1045         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1046         .recalc         = &followparent_recalc,
1047 };
1048
1049 static struct clk gpt9_fck = {
1050         .name           = "gpt9_fck",
1051         .ops            = &clkops_omap2_dflt_wait,
1052         .parent         = &func_32k_ck,
1053         .clkdm_name     = "core_l4_clkdm",
1054         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1055         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1056         .init           = &omap2_init_clksel_parent,
1057         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1058         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1059         .clksel         = omap24xx_gpt_clksel,
1060         .recalc         = &omap2_clksel_recalc,
1061 };
1062
1063 static struct clk gpt10_ick = {
1064         .name           = "gpt10_ick",
1065         .ops            = &clkops_omap2_dflt_wait,
1066         .parent         = &l4_ck,
1067         .clkdm_name     = "core_l4_clkdm",
1068         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1069         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1070         .recalc         = &followparent_recalc,
1071 };
1072
1073 static struct clk gpt10_fck = {
1074         .name           = "gpt10_fck",
1075         .ops            = &clkops_omap2_dflt_wait,
1076         .parent         = &func_32k_ck,
1077         .clkdm_name     = "core_l4_clkdm",
1078         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1079         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1080         .init           = &omap2_init_clksel_parent,
1081         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1082         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1083         .clksel         = omap24xx_gpt_clksel,
1084         .recalc         = &omap2_clksel_recalc,
1085 };
1086
1087 static struct clk gpt11_ick = {
1088         .name           = "gpt11_ick",
1089         .ops            = &clkops_omap2_dflt_wait,
1090         .parent         = &l4_ck,
1091         .clkdm_name     = "core_l4_clkdm",
1092         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1093         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1094         .recalc         = &followparent_recalc,
1095 };
1096
1097 static struct clk gpt11_fck = {
1098         .name           = "gpt11_fck",
1099         .ops            = &clkops_omap2_dflt_wait,
1100         .parent         = &func_32k_ck,
1101         .clkdm_name     = "core_l4_clkdm",
1102         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1103         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1104         .init           = &omap2_init_clksel_parent,
1105         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1106         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1107         .clksel         = omap24xx_gpt_clksel,
1108         .recalc         = &omap2_clksel_recalc,
1109 };
1110
1111 static struct clk gpt12_ick = {
1112         .name           = "gpt12_ick",
1113         .ops            = &clkops_omap2_dflt_wait,
1114         .parent         = &l4_ck,
1115         .clkdm_name     = "core_l4_clkdm",
1116         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1117         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1118         .recalc         = &followparent_recalc,
1119 };
1120
1121 static struct clk gpt12_fck = {
1122         .name           = "gpt12_fck",
1123         .ops            = &clkops_omap2_dflt_wait,
1124         .parent         = &secure_32k_ck,
1125         .clkdm_name     = "core_l4_clkdm",
1126         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1127         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1128         .init           = &omap2_init_clksel_parent,
1129         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1130         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1131         .clksel         = omap24xx_gpt_clksel,
1132         .recalc         = &omap2_clksel_recalc,
1133 };
1134
1135 static struct clk mcbsp1_ick = {
1136         .name           = "mcbsp1_ick",
1137         .ops            = &clkops_omap2_dflt_wait,
1138         .parent         = &l4_ck,
1139         .clkdm_name     = "core_l4_clkdm",
1140         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1141         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1142         .recalc         = &followparent_recalc,
1143 };
1144
1145 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1146         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1147         { .div = 0 }
1148 };
1149
1150 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1151         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1152         { .div = 0 }
1153 };
1154
1155 static const struct clksel mcbsp_fck_clksel[] = {
1156         { .parent = &func_96m_ck,  .rates = common_mcbsp_96m_rates },
1157         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1158         { .parent = NULL }
1159 };
1160
1161 static struct clk mcbsp1_fck = {
1162         .name           = "mcbsp1_fck",
1163         .ops            = &clkops_omap2_dflt_wait,
1164         .parent         = &func_96m_ck,
1165         .init           = &omap2_init_clksel_parent,
1166         .clkdm_name     = "core_l4_clkdm",
1167         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1168         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1169         .clksel_reg     = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1170         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1171         .clksel         = mcbsp_fck_clksel,
1172         .recalc         = &omap2_clksel_recalc,
1173 };
1174
1175 static struct clk mcbsp2_ick = {
1176         .name           = "mcbsp2_ick",
1177         .ops            = &clkops_omap2_dflt_wait,
1178         .parent         = &l4_ck,
1179         .clkdm_name     = "core_l4_clkdm",
1180         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1181         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1182         .recalc         = &followparent_recalc,
1183 };
1184
1185 static struct clk mcbsp2_fck = {
1186         .name           = "mcbsp2_fck",
1187         .ops            = &clkops_omap2_dflt_wait,
1188         .parent         = &func_96m_ck,
1189         .init           = &omap2_init_clksel_parent,
1190         .clkdm_name     = "core_l4_clkdm",
1191         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1192         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1193         .clksel_reg     = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1194         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
1195         .clksel         = mcbsp_fck_clksel,
1196         .recalc         = &omap2_clksel_recalc,
1197 };
1198
1199 static struct clk mcspi1_ick = {
1200         .name           = "mcspi1_ick",
1201         .ops            = &clkops_omap2_dflt_wait,
1202         .parent         = &l4_ck,
1203         .clkdm_name     = "core_l4_clkdm",
1204         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1205         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1206         .recalc         = &followparent_recalc,
1207 };
1208
1209 static struct clk mcspi1_fck = {
1210         .name           = "mcspi1_fck",
1211         .ops            = &clkops_omap2_dflt_wait,
1212         .parent         = &func_48m_ck,
1213         .clkdm_name     = "core_l4_clkdm",
1214         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1215         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1216         .recalc         = &followparent_recalc,
1217 };
1218
1219 static struct clk mcspi2_ick = {
1220         .name           = "mcspi2_ick",
1221         .ops            = &clkops_omap2_dflt_wait,
1222         .parent         = &l4_ck,
1223         .clkdm_name     = "core_l4_clkdm",
1224         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1225         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1226         .recalc         = &followparent_recalc,
1227 };
1228
1229 static struct clk mcspi2_fck = {
1230         .name           = "mcspi2_fck",
1231         .ops            = &clkops_omap2_dflt_wait,
1232         .parent         = &func_48m_ck,
1233         .clkdm_name     = "core_l4_clkdm",
1234         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1235         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1236         .recalc         = &followparent_recalc,
1237 };
1238
1239 static struct clk uart1_ick = {
1240         .name           = "uart1_ick",
1241         .ops            = &clkops_omap2_dflt_wait,
1242         .parent         = &l4_ck,
1243         .clkdm_name     = "core_l4_clkdm",
1244         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1245         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1246         .recalc         = &followparent_recalc,
1247 };
1248
1249 static struct clk uart1_fck = {
1250         .name           = "uart1_fck",
1251         .ops            = &clkops_omap2_dflt_wait,
1252         .parent         = &func_48m_ck,
1253         .clkdm_name     = "core_l4_clkdm",
1254         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1255         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1256         .recalc         = &followparent_recalc,
1257 };
1258
1259 static struct clk uart2_ick = {
1260         .name           = "uart2_ick",
1261         .ops            = &clkops_omap2_dflt_wait,
1262         .parent         = &l4_ck,
1263         .clkdm_name     = "core_l4_clkdm",
1264         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1265         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1266         .recalc         = &followparent_recalc,
1267 };
1268
1269 static struct clk uart2_fck = {
1270         .name           = "uart2_fck",
1271         .ops            = &clkops_omap2_dflt_wait,
1272         .parent         = &func_48m_ck,
1273         .clkdm_name     = "core_l4_clkdm",
1274         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1275         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1276         .recalc         = &followparent_recalc,
1277 };
1278
1279 static struct clk uart3_ick = {
1280         .name           = "uart3_ick",
1281         .ops            = &clkops_omap2_dflt_wait,
1282         .parent         = &l4_ck,
1283         .clkdm_name     = "core_l4_clkdm",
1284         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1285         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1286         .recalc         = &followparent_recalc,
1287 };
1288
1289 static struct clk uart3_fck = {
1290         .name           = "uart3_fck",
1291         .ops            = &clkops_omap2_dflt_wait,
1292         .parent         = &func_48m_ck,
1293         .clkdm_name     = "core_l4_clkdm",
1294         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1295         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1296         .recalc         = &followparent_recalc,
1297 };
1298
1299 static struct clk gpios_ick = {
1300         .name           = "gpios_ick",
1301         .ops            = &clkops_omap2_dflt_wait,
1302         .parent         = &l4_ck,
1303         .clkdm_name     = "core_l4_clkdm",
1304         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1305         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1306         .recalc         = &followparent_recalc,
1307 };
1308
1309 static struct clk gpios_fck = {
1310         .name           = "gpios_fck",
1311         .ops            = &clkops_omap2_dflt_wait,
1312         .parent         = &func_32k_ck,
1313         .clkdm_name     = "wkup_clkdm",
1314         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1315         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1316         .recalc         = &followparent_recalc,
1317 };
1318
1319 static struct clk mpu_wdt_ick = {
1320         .name           = "mpu_wdt_ick",
1321         .ops            = &clkops_omap2_dflt_wait,
1322         .parent         = &l4_ck,
1323         .clkdm_name     = "core_l4_clkdm",
1324         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1325         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1326         .recalc         = &followparent_recalc,
1327 };
1328
1329 static struct clk mpu_wdt_fck = {
1330         .name           = "mpu_wdt_fck",
1331         .ops            = &clkops_omap2_dflt_wait,
1332         .parent         = &func_32k_ck,
1333         .clkdm_name     = "wkup_clkdm",
1334         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1335         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1336         .recalc         = &followparent_recalc,
1337 };
1338
1339 static struct clk sync_32k_ick = {
1340         .name           = "sync_32k_ick",
1341         .ops            = &clkops_omap2_dflt_wait,
1342         .parent         = &l4_ck,
1343         .flags          = ENABLE_ON_INIT,
1344         .clkdm_name     = "core_l4_clkdm",
1345         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1346         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
1347         .recalc         = &followparent_recalc,
1348 };
1349
1350 static struct clk wdt1_ick = {
1351         .name           = "wdt1_ick",
1352         .ops            = &clkops_omap2_dflt_wait,
1353         .parent         = &l4_ck,
1354         .clkdm_name     = "core_l4_clkdm",
1355         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1356         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
1357         .recalc         = &followparent_recalc,
1358 };
1359
1360 static struct clk omapctrl_ick = {
1361         .name           = "omapctrl_ick",
1362         .ops            = &clkops_omap2_dflt_wait,
1363         .parent         = &l4_ck,
1364         .flags          = ENABLE_ON_INIT,
1365         .clkdm_name     = "core_l4_clkdm",
1366         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1367         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
1368         .recalc         = &followparent_recalc,
1369 };
1370
1371 static struct clk cam_ick = {
1372         .name           = "cam_ick",
1373         .ops            = &clkops_omap2_dflt,
1374         .parent         = &l4_ck,
1375         .clkdm_name     = "core_l4_clkdm",
1376         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1377         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
1378         .recalc         = &followparent_recalc,
1379 };
1380
1381 /*
1382  * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
1383  * split into two separate clocks, since the parent clocks are different
1384  * and the clockdomains are also different.
1385  */
1386 static struct clk cam_fck = {
1387         .name           = "cam_fck",
1388         .ops            = &clkops_omap2_dflt,
1389         .parent         = &func_96m_ck,
1390         .clkdm_name     = "core_l3_clkdm",
1391         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1392         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
1393         .recalc         = &followparent_recalc,
1394 };
1395
1396 static struct clk mailboxes_ick = {
1397         .name           = "mailboxes_ick",
1398         .ops            = &clkops_omap2_dflt_wait,
1399         .parent         = &l4_ck,
1400         .clkdm_name     = "core_l4_clkdm",
1401         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1402         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
1403         .recalc         = &followparent_recalc,
1404 };
1405
1406 static struct clk wdt4_ick = {
1407         .name           = "wdt4_ick",
1408         .ops            = &clkops_omap2_dflt_wait,
1409         .parent         = &l4_ck,
1410         .clkdm_name     = "core_l4_clkdm",
1411         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1412         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
1413         .recalc         = &followparent_recalc,
1414 };
1415
1416 static struct clk wdt4_fck = {
1417         .name           = "wdt4_fck",
1418         .ops            = &clkops_omap2_dflt_wait,
1419         .parent         = &func_32k_ck,
1420         .clkdm_name     = "core_l4_clkdm",
1421         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1422         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
1423         .recalc         = &followparent_recalc,
1424 };
1425
1426 static struct clk wdt3_ick = {
1427         .name           = "wdt3_ick",
1428         .ops            = &clkops_omap2_dflt_wait,
1429         .parent         = &l4_ck,
1430         .clkdm_name     = "core_l4_clkdm",
1431         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1432         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
1433         .recalc         = &followparent_recalc,
1434 };
1435
1436 static struct clk wdt3_fck = {
1437         .name           = "wdt3_fck",
1438         .ops            = &clkops_omap2_dflt_wait,
1439         .parent         = &func_32k_ck,
1440         .clkdm_name     = "core_l4_clkdm",
1441         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1442         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
1443         .recalc         = &followparent_recalc,
1444 };
1445
1446 static struct clk mspro_ick = {
1447         .name           = "mspro_ick",
1448         .ops            = &clkops_omap2_dflt_wait,
1449         .parent         = &l4_ck,
1450         .clkdm_name     = "core_l4_clkdm",
1451         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1452         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
1453         .recalc         = &followparent_recalc,
1454 };
1455
1456 static struct clk mspro_fck = {
1457         .name           = "mspro_fck",
1458         .ops            = &clkops_omap2_dflt_wait,
1459         .parent         = &func_96m_ck,
1460         .clkdm_name     = "core_l4_clkdm",
1461         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1462         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
1463         .recalc         = &followparent_recalc,
1464 };
1465
1466 static struct clk mmc_ick = {
1467         .name           = "mmc_ick",
1468         .ops            = &clkops_omap2_dflt_wait,
1469         .parent         = &l4_ck,
1470         .clkdm_name     = "core_l4_clkdm",
1471         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1472         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
1473         .recalc         = &followparent_recalc,
1474 };
1475
1476 static struct clk mmc_fck = {
1477         .name           = "mmc_fck",
1478         .ops            = &clkops_omap2_dflt_wait,
1479         .parent         = &func_96m_ck,
1480         .clkdm_name     = "core_l4_clkdm",
1481         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1482         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
1483         .recalc         = &followparent_recalc,
1484 };
1485
1486 static struct clk fac_ick = {
1487         .name           = "fac_ick",
1488         .ops            = &clkops_omap2_dflt_wait,
1489         .parent         = &l4_ck,
1490         .clkdm_name     = "core_l4_clkdm",
1491         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1492         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
1493         .recalc         = &followparent_recalc,
1494 };
1495
1496 static struct clk fac_fck = {
1497         .name           = "fac_fck",
1498         .ops            = &clkops_omap2_dflt_wait,
1499         .parent         = &func_12m_ck,
1500         .clkdm_name     = "core_l4_clkdm",
1501         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1502         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
1503         .recalc         = &followparent_recalc,
1504 };
1505
1506 static struct clk eac_ick = {
1507         .name           = "eac_ick",
1508         .ops            = &clkops_omap2_dflt_wait,
1509         .parent         = &l4_ck,
1510         .clkdm_name     = "core_l4_clkdm",
1511         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1512         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
1513         .recalc         = &followparent_recalc,
1514 };
1515
1516 static struct clk eac_fck = {
1517         .name           = "eac_fck",
1518         .ops            = &clkops_omap2_dflt_wait,
1519         .parent         = &func_96m_ck,
1520         .clkdm_name     = "core_l4_clkdm",
1521         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1522         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
1523         .recalc         = &followparent_recalc,
1524 };
1525
1526 static struct clk hdq_ick = {
1527         .name           = "hdq_ick",
1528         .ops            = &clkops_omap2_dflt_wait,
1529         .parent         = &l4_ck,
1530         .clkdm_name     = "core_l4_clkdm",
1531         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1532         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
1533         .recalc         = &followparent_recalc,
1534 };
1535
1536 static struct clk hdq_fck = {
1537         .name           = "hdq_fck",
1538         .ops            = &clkops_omap2_dflt_wait,
1539         .parent         = &func_12m_ck,
1540         .clkdm_name     = "core_l4_clkdm",
1541         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1542         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
1543         .recalc         = &followparent_recalc,
1544 };
1545
1546 static struct clk i2c2_ick = {
1547         .name           = "i2c2_ick",
1548         .ops            = &clkops_omap2_dflt_wait,
1549         .parent         = &l4_ck,
1550         .clkdm_name     = "core_l4_clkdm",
1551         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1552         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
1553         .recalc         = &followparent_recalc,
1554 };
1555
1556 static struct clk i2c2_fck = {
1557         .name           = "i2c2_fck",
1558         .ops            = &clkops_omap2_dflt_wait,
1559         .parent         = &func_12m_ck,
1560         .clkdm_name     = "core_l4_clkdm",
1561         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1562         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
1563         .recalc         = &followparent_recalc,
1564 };
1565
1566 static struct clk i2c1_ick = {
1567         .name           = "i2c1_ick",
1568         .ops            = &clkops_omap2_dflt_wait,
1569         .parent         = &l4_ck,
1570         .clkdm_name     = "core_l4_clkdm",
1571         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1572         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
1573         .recalc         = &followparent_recalc,
1574 };
1575
1576 static struct clk i2c1_fck = {
1577         .name           = "i2c1_fck",
1578         .ops            = &clkops_omap2_dflt_wait,
1579         .parent         = &func_12m_ck,
1580         .clkdm_name     = "core_l4_clkdm",
1581         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1582         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
1583         .recalc         = &followparent_recalc,
1584 };
1585
1586 static struct clk gpmc_fck = {
1587         .name           = "gpmc_fck",
1588         .ops            = &clkops_null, /* RMK: missing? */
1589         .parent         = &core_l3_ck,
1590         .flags          = ENABLE_ON_INIT,
1591         .clkdm_name     = "core_l3_clkdm",
1592         .recalc         = &followparent_recalc,
1593 };
1594
1595 static struct clk sdma_fck = {
1596         .name           = "sdma_fck",
1597         .ops            = &clkops_null, /* RMK: missing? */
1598         .parent         = &core_l3_ck,
1599         .clkdm_name     = "core_l3_clkdm",
1600         .recalc         = &followparent_recalc,
1601 };
1602
1603 static struct clk sdma_ick = {
1604         .name           = "sdma_ick",
1605         .ops            = &clkops_null, /* RMK: missing? */
1606         .parent         = &l4_ck,
1607         .clkdm_name     = "core_l3_clkdm",
1608         .recalc         = &followparent_recalc,
1609 };
1610
1611 static struct clk vlynq_ick = {
1612         .name           = "vlynq_ick",
1613         .ops            = &clkops_omap2_dflt_wait,
1614         .parent         = &core_l3_ck,
1615         .clkdm_name     = "core_l3_clkdm",
1616         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1617         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
1618         .recalc         = &followparent_recalc,
1619 };
1620
1621 static const struct clksel_rate vlynq_fck_96m_rates[] = {
1622         { .div = 1, .val = 0, .flags = RATE_IN_242X },
1623         { .div = 0 }
1624 };
1625
1626 static const struct clksel_rate vlynq_fck_core_rates[] = {
1627         { .div = 1, .val = 1, .flags = RATE_IN_242X },
1628         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1629         { .div = 3, .val = 3, .flags = RATE_IN_242X },
1630         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1631         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1632         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1633         { .div = 9, .val = 9, .flags = RATE_IN_242X },
1634         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1635         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1636         { .div = 18, .val = 18, .flags = RATE_IN_242X },
1637         { .div = 0 }
1638 };
1639
1640 static const struct clksel vlynq_fck_clksel[] = {
1641         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
1642         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
1643         { .parent = NULL }
1644 };
1645
1646 static struct clk vlynq_fck = {
1647         .name           = "vlynq_fck",
1648         .ops            = &clkops_omap2_dflt_wait,
1649         .parent         = &func_96m_ck,
1650         .clkdm_name     = "core_l3_clkdm",
1651         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1652         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
1653         .init           = &omap2_init_clksel_parent,
1654         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1655         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
1656         .clksel         = vlynq_fck_clksel,
1657         .recalc         = &omap2_clksel_recalc,
1658 };
1659
1660 static struct clk des_ick = {
1661         .name           = "des_ick",
1662         .ops            = &clkops_omap2_dflt_wait,
1663         .parent         = &l4_ck,
1664         .clkdm_name     = "core_l4_clkdm",
1665         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1666         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
1667         .recalc         = &followparent_recalc,
1668 };
1669
1670 static struct clk sha_ick = {
1671         .name           = "sha_ick",
1672         .ops            = &clkops_omap2_dflt_wait,
1673         .parent         = &l4_ck,
1674         .clkdm_name     = "core_l4_clkdm",
1675         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1676         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
1677         .recalc         = &followparent_recalc,
1678 };
1679
1680 static struct clk rng_ick = {
1681         .name           = "rng_ick",
1682         .ops            = &clkops_omap2_dflt_wait,
1683         .parent         = &l4_ck,
1684         .clkdm_name     = "core_l4_clkdm",
1685         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1686         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
1687         .recalc         = &followparent_recalc,
1688 };
1689
1690 static struct clk aes_ick = {
1691         .name           = "aes_ick",
1692         .ops            = &clkops_omap2_dflt_wait,
1693         .parent         = &l4_ck,
1694         .clkdm_name     = "core_l4_clkdm",
1695         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1696         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
1697         .recalc         = &followparent_recalc,
1698 };
1699
1700 static struct clk pka_ick = {
1701         .name           = "pka_ick",
1702         .ops            = &clkops_omap2_dflt_wait,
1703         .parent         = &l4_ck,
1704         .clkdm_name     = "core_l4_clkdm",
1705         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1706         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
1707         .recalc         = &followparent_recalc,
1708 };
1709
1710 static struct clk usb_fck = {
1711         .name           = "usb_fck",
1712         .ops            = &clkops_omap2_dflt_wait,
1713         .parent         = &func_48m_ck,
1714         .clkdm_name     = "core_l3_clkdm",
1715         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1716         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1717         .recalc         = &followparent_recalc,
1718 };
1719
1720 /*
1721  * This clock is a composite clock which does entire set changes then
1722  * forces a rebalance. It keys on the MPU speed, but it really could
1723  * be any key speed part of a set in the rate table.
1724  *
1725  * to really change a set, you need memory table sets which get changed
1726  * in sram, pre-notifiers & post notifiers, changing the top set, without
1727  * having low level display recalc's won't work... this is why dpm notifiers
1728  * work, isr's off, walk a list of clocks already _off_ and not messing with
1729  * the bus.
1730  *
1731  * This clock should have no parent. It embodies the entire upper level
1732  * active set. A parent will mess up some of the init also.
1733  */
1734 static struct clk virt_prcm_set = {
1735         .name           = "virt_prcm_set",
1736         .ops            = &clkops_null,
1737         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
1738         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
1739         .set_rate       = &omap2_select_table_rate,
1740         .round_rate     = &omap2_round_to_table_rate,
1741 };
1742
1743
1744 /*
1745  * clkdev integration
1746  */
1747
1748 static struct omap_clk omap2420_clks[] = {
1749         /* external root sources */
1750         CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_242X),
1751         CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_242X),
1752         CLK(NULL,       "osc_ck",       &osc_ck,        CK_242X),
1753         CLK(NULL,       "sys_ck",       &sys_ck,        CK_242X),
1754         CLK(NULL,       "alt_ck",       &alt_ck,        CK_242X),
1755         CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_242X),
1756         CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_242X),
1757         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_242X),
1758         /* internal analog sources */
1759         CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_242X),
1760         CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_242X),
1761         CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_242X),
1762         /* internal prcm root sources */
1763         CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_242X),
1764         CLK(NULL,       "core_ck",      &core_ck,       CK_242X),
1765         CLK("omap-mcbsp.1",     "prcm_fck",     &func_96m_ck,   CK_242X),
1766         CLK("omap-mcbsp.2",     "prcm_fck",     &func_96m_ck,   CK_242X),
1767         CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_242X),
1768         CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_242X),
1769         CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_242X),
1770         CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_242X),
1771         CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_242X),
1772         CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_242X),
1773         CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src, CK_242X),
1774         CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_242X),
1775         CLK(NULL,       "emul_ck",      &emul_ck,       CK_242X),
1776         /* mpu domain clocks */
1777         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_242X),
1778         /* dsp domain clocks */
1779         CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_242X),
1780         CLK(NULL,       "dsp_irate_ick", &dsp_irate_ick, CK_242X),
1781         CLK(NULL,       "dsp_ick",      &dsp_ick,       CK_242X),
1782         CLK(NULL,       "iva1_ifck",    &iva1_ifck,     CK_242X),
1783         CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
1784         /* GFX domain clocks */
1785         CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_242X),
1786         CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_242X),
1787         CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_242X),
1788         /* DSS domain clocks */
1789         CLK("omapdss",  "ick",          &dss_ick,       CK_242X),
1790         CLK("omapdss",  "dss1_fck",     &dss1_fck,      CK_242X),
1791         CLK("omapdss",  "dss2_fck",     &dss2_fck,      CK_242X),
1792         CLK("omapdss",  "tv_fck",       &dss_54m_fck,   CK_242X),
1793         /* L3 domain clocks */
1794         CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_242X),
1795         CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_242X),
1796         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_242X),
1797         /* L4 domain clocks */
1798         CLK(NULL,       "l4_ck",        &l4_ck,         CK_242X),
1799         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_242X),
1800         /* virtual meta-group clock */
1801         CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_242X),
1802         /* general l4 interface ck, multi-parent functional clk */
1803         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_242X),
1804         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_242X),
1805         CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_242X),
1806         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_242X),
1807         CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_242X),
1808         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_242X),
1809         CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_242X),
1810         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_242X),
1811         CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_242X),
1812         CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_242X),
1813         CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_242X),
1814         CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_242X),
1815         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_242X),
1816         CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_242X),
1817         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_242X),
1818         CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_242X),
1819         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_242X),
1820         CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_242X),
1821         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_242X),
1822         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_242X),
1823         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_242X),
1824         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_242X),
1825         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_242X),
1826         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_242X),
1827         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_242X),
1828         CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_242X),
1829         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_242X),
1830         CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_242X),
1831         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_242X),
1832         CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_242X),
1833         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_242X),
1834         CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_242X),
1835         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_242X),
1836         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_242X),
1837         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_242X),
1838         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_242X),
1839         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_242X),
1840         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_242X),
1841         CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_242X),
1842         CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_242X),
1843         CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_242X),
1844         CLK("omap_wdt", "fck",          &mpu_wdt_fck,   CK_242X),
1845         CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_242X),
1846         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_242X),
1847         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_242X),
1848         CLK("omap24xxcam", "fck",       &cam_fck,       CK_242X),
1849         CLK("omap24xxcam", "ick",       &cam_ick,       CK_242X),
1850         CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_242X),
1851         CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_242X),
1852         CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_242X),
1853         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_242X),
1854         CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_242X),
1855         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_242X),
1856         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_242X),
1857         CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
1858         CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
1859         CLK(NULL,       "fac_ick",      &fac_ick,       CK_242X),
1860         CLK(NULL,       "fac_fck",      &fac_fck,       CK_242X),
1861         CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
1862         CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
1863         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_242X),
1864         CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_242X),
1865         CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_242X),
1866         CLK("omap_i2c.1", "fck",        &i2c1_fck,      CK_242X),
1867         CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_242X),
1868         CLK("omap_i2c.2", "fck",        &i2c2_fck,      CK_242X),
1869         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_242X),
1870         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_242X),
1871         CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_242X),
1872         CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
1873         CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
1874         CLK(NULL,       "des_ick",      &des_ick,       CK_242X),
1875         CLK("omap-sham",        "ick",  &sha_ick,       CK_242X),
1876         CLK("omap_rng", "ick",          &rng_ick,       CK_242X),
1877         CLK("omap-aes", "ick",  &aes_ick,       CK_242X),
1878         CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),
1879         CLK(NULL,       "usb_fck",      &usb_fck,       CK_242X),
1880         CLK("musb_hdrc",        "fck",  &osc_ck,        CK_242X),
1881 };
1882
1883 /*
1884  * init code
1885  */
1886
1887 int __init omap2420_clk_init(void)
1888 {
1889         const struct prcm_config *prcm;
1890         struct omap_clk *c;
1891         u32 clkrate;
1892
1893         prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
1894         cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
1895         cpu_mask = RATE_IN_242X;
1896         rate_table = omap2420_rate_table;
1897
1898         clk_init(&omap2_clk_functions);
1899
1900         for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1901              c++)
1902                 clk_preinit(c->lk.clk);
1903
1904         osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
1905         propagate_rate(&osc_ck);
1906         sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
1907         propagate_rate(&sys_ck);
1908
1909         for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1910              c++) {
1911                 clkdev_add(&c->lk);
1912                 clk_register(c->lk.clk);
1913                 omap2_init_clk_clkdm(c->lk.clk);
1914         }
1915
1916         /* Check the MPU rate set by bootloader */
1917         clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
1918         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1919                 if (!(prcm->flags & cpu_mask))
1920                         continue;
1921                 if (prcm->xtal_speed != sys_ck.rate)
1922                         continue;
1923                 if (prcm->dpll_speed <= clkrate)
1924                         break;
1925         }
1926         curr_prcm_set = prcm;
1927
1928         recalculate_root_clocks();
1929
1930         pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
1931                 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1932                 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1933
1934         /*
1935          * Only enable those clocks we will need, let the drivers
1936          * enable other clocks as necessary
1937          */
1938         clk_enable_init_clocks();
1939
1940         /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
1941         vclk = clk_get(NULL, "virt_prcm_set");
1942         sclk = clk_get(NULL, "sys_ck");
1943         dclk = clk_get(NULL, "dpll_ck");
1944
1945         return 0;
1946 }
1947