2 * OMAP3-specific clock framework functions
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>
22 #include <linux/list.h>
23 #include <linux/errno.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
27 #include <linux/limits.h>
28 #include <linux/bitops.h>
31 #include <mach/clock.h>
32 #include <mach/sram.h>
33 #include <asm/div64.h>
34 #include <asm/clkdev.h>
36 #include <mach/sdrc.h>
39 #include "prm-regbits-34xx.h"
41 #include "cm-regbits-34xx.h"
43 static const struct clkops clkops_noncore_dpll_ops
;
45 static void omap3430es2_clk_ssi_find_idlest(struct clk
*clk
,
46 void __iomem
**idlest_reg
,
48 static void omap3430es2_clk_hsotgusb_find_idlest(struct clk
*clk
,
49 void __iomem
**idlest_reg
,
51 static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk
*clk
,
52 void __iomem
**idlest_reg
,
55 static const struct clkops clkops_omap3430es2_ssi_wait
= {
56 .enable
= omap2_dflt_clk_enable
,
57 .disable
= omap2_dflt_clk_disable
,
58 .find_idlest
= omap3430es2_clk_ssi_find_idlest
,
59 .find_companion
= omap2_clk_dflt_find_companion
,
62 static const struct clkops clkops_omap3430es2_hsotgusb_wait
= {
63 .enable
= omap2_dflt_clk_enable
,
64 .disable
= omap2_dflt_clk_disable
,
65 .find_idlest
= omap3430es2_clk_hsotgusb_find_idlest
,
66 .find_companion
= omap2_clk_dflt_find_companion
,
69 static const struct clkops clkops_omap3430es2_dss_usbhost_wait
= {
70 .enable
= omap2_dflt_clk_enable
,
71 .disable
= omap2_dflt_clk_disable
,
72 .find_idlest
= omap3430es2_clk_dss_usbhost_find_idlest
,
73 .find_companion
= omap2_clk_dflt_find_companion
,
76 #include "clock34xx.h"
83 #define CLK(dev, con, ck, cp) \
93 #define CK_343X (1 << 0)
94 #define CK_3430ES1 (1 << 1)
95 #define CK_3430ES2 (1 << 2)
97 static struct omap_clk omap34xx_clks
[] = {
98 CLK(NULL
, "omap_32k_fck", &omap_32k_fck
, CK_343X
),
99 CLK(NULL
, "virt_12m_ck", &virt_12m_ck
, CK_343X
),
100 CLK(NULL
, "virt_13m_ck", &virt_13m_ck
, CK_343X
),
101 CLK(NULL
, "virt_16_8m_ck", &virt_16_8m_ck
, CK_3430ES2
),
102 CLK(NULL
, "virt_19_2m_ck", &virt_19_2m_ck
, CK_343X
),
103 CLK(NULL
, "virt_26m_ck", &virt_26m_ck
, CK_343X
),
104 CLK(NULL
, "virt_38_4m_ck", &virt_38_4m_ck
, CK_343X
),
105 CLK(NULL
, "osc_sys_ck", &osc_sys_ck
, CK_343X
),
106 CLK(NULL
, "sys_ck", &sys_ck
, CK_343X
),
107 CLK(NULL
, "sys_altclk", &sys_altclk
, CK_343X
),
108 CLK(NULL
, "mcbsp_clks", &mcbsp_clks
, CK_343X
),
109 CLK(NULL
, "sys_clkout1", &sys_clkout1
, CK_343X
),
110 CLK(NULL
, "dpll1_ck", &dpll1_ck
, CK_343X
),
111 CLK(NULL
, "dpll1_x2_ck", &dpll1_x2_ck
, CK_343X
),
112 CLK(NULL
, "dpll1_x2m2_ck", &dpll1_x2m2_ck
, CK_343X
),
113 CLK(NULL
, "dpll2_ck", &dpll2_ck
, CK_343X
),
114 CLK(NULL
, "dpll2_m2_ck", &dpll2_m2_ck
, CK_343X
),
115 CLK(NULL
, "dpll3_ck", &dpll3_ck
, CK_343X
),
116 CLK(NULL
, "core_ck", &core_ck
, CK_343X
),
117 CLK(NULL
, "dpll3_x2_ck", &dpll3_x2_ck
, CK_343X
),
118 CLK(NULL
, "dpll3_m2_ck", &dpll3_m2_ck
, CK_343X
),
119 CLK(NULL
, "dpll3_m2x2_ck", &dpll3_m2x2_ck
, CK_343X
),
120 CLK(NULL
, "dpll3_m3_ck", &dpll3_m3_ck
, CK_343X
),
121 CLK(NULL
, "dpll3_m3x2_ck", &dpll3_m3x2_ck
, CK_343X
),
122 CLK(NULL
, "emu_core_alwon_ck", &emu_core_alwon_ck
, CK_343X
),
123 CLK(NULL
, "dpll4_ck", &dpll4_ck
, CK_343X
),
124 CLK(NULL
, "dpll4_x2_ck", &dpll4_x2_ck
, CK_343X
),
125 CLK(NULL
, "omap_96m_alwon_fck", &omap_96m_alwon_fck
, CK_343X
),
126 CLK(NULL
, "omap_96m_fck", &omap_96m_fck
, CK_343X
),
127 CLK(NULL
, "cm_96m_fck", &cm_96m_fck
, CK_343X
),
128 CLK(NULL
, "omap_54m_fck", &omap_54m_fck
, CK_343X
),
129 CLK(NULL
, "omap_48m_fck", &omap_48m_fck
, CK_343X
),
130 CLK(NULL
, "omap_12m_fck", &omap_12m_fck
, CK_343X
),
131 CLK(NULL
, "dpll4_m2_ck", &dpll4_m2_ck
, CK_343X
),
132 CLK(NULL
, "dpll4_m2x2_ck", &dpll4_m2x2_ck
, CK_343X
),
133 CLK(NULL
, "dpll4_m3_ck", &dpll4_m3_ck
, CK_343X
),
134 CLK(NULL
, "dpll4_m3x2_ck", &dpll4_m3x2_ck
, CK_343X
),
135 CLK(NULL
, "dpll4_m4_ck", &dpll4_m4_ck
, CK_343X
),
136 CLK(NULL
, "dpll4_m4x2_ck", &dpll4_m4x2_ck
, CK_343X
),
137 CLK(NULL
, "dpll4_m5_ck", &dpll4_m5_ck
, CK_343X
),
138 CLK(NULL
, "dpll4_m5x2_ck", &dpll4_m5x2_ck
, CK_343X
),
139 CLK(NULL
, "dpll4_m6_ck", &dpll4_m6_ck
, CK_343X
),
140 CLK(NULL
, "dpll4_m6x2_ck", &dpll4_m6x2_ck
, CK_343X
),
141 CLK(NULL
, "emu_per_alwon_ck", &emu_per_alwon_ck
, CK_343X
),
142 CLK(NULL
, "dpll5_ck", &dpll5_ck
, CK_3430ES2
),
143 CLK(NULL
, "dpll5_m2_ck", &dpll5_m2_ck
, CK_3430ES2
),
144 CLK(NULL
, "clkout2_src_ck", &clkout2_src_ck
, CK_343X
),
145 CLK(NULL
, "sys_clkout2", &sys_clkout2
, CK_343X
),
146 CLK(NULL
, "corex2_fck", &corex2_fck
, CK_343X
),
147 CLK(NULL
, "dpll1_fck", &dpll1_fck
, CK_343X
),
148 CLK(NULL
, "mpu_ck", &mpu_ck
, CK_343X
),
149 CLK(NULL
, "arm_fck", &arm_fck
, CK_343X
),
150 CLK(NULL
, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck
, CK_343X
),
151 CLK(NULL
, "dpll2_fck", &dpll2_fck
, CK_343X
),
152 CLK(NULL
, "iva2_ck", &iva2_ck
, CK_343X
),
153 CLK(NULL
, "l3_ick", &l3_ick
, CK_343X
),
154 CLK(NULL
, "l4_ick", &l4_ick
, CK_343X
),
155 CLK(NULL
, "rm_ick", &rm_ick
, CK_343X
),
156 CLK(NULL
, "gfx_l3_ck", &gfx_l3_ck
, CK_3430ES1
),
157 CLK(NULL
, "gfx_l3_fck", &gfx_l3_fck
, CK_3430ES1
),
158 CLK(NULL
, "gfx_l3_ick", &gfx_l3_ick
, CK_3430ES1
),
159 CLK(NULL
, "gfx_cg1_ck", &gfx_cg1_ck
, CK_3430ES1
),
160 CLK(NULL
, "gfx_cg2_ck", &gfx_cg2_ck
, CK_3430ES1
),
161 CLK(NULL
, "sgx_fck", &sgx_fck
, CK_3430ES2
),
162 CLK(NULL
, "sgx_ick", &sgx_ick
, CK_3430ES2
),
163 CLK(NULL
, "d2d_26m_fck", &d2d_26m_fck
, CK_3430ES1
),
164 CLK(NULL
, "modem_fck", &modem_fck
, CK_343X
),
165 CLK(NULL
, "sad2d_ick", &sad2d_ick
, CK_343X
),
166 CLK(NULL
, "mad2d_ick", &mad2d_ick
, CK_343X
),
167 CLK(NULL
, "gpt10_fck", &gpt10_fck
, CK_343X
),
168 CLK(NULL
, "gpt11_fck", &gpt11_fck
, CK_343X
),
169 CLK(NULL
, "cpefuse_fck", &cpefuse_fck
, CK_3430ES2
),
170 CLK(NULL
, "ts_fck", &ts_fck
, CK_3430ES2
),
171 CLK(NULL
, "usbtll_fck", &usbtll_fck
, CK_3430ES2
),
172 CLK(NULL
, "core_96m_fck", &core_96m_fck
, CK_343X
),
173 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck
, CK_3430ES2
),
174 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck
, CK_343X
),
175 CLK(NULL
, "mspro_fck", &mspro_fck
, CK_343X
),
176 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck
, CK_343X
),
177 CLK("i2c_omap.3", "fck", &i2c3_fck
, CK_343X
),
178 CLK("i2c_omap.2", "fck", &i2c2_fck
, CK_343X
),
179 CLK("i2c_omap.1", "fck", &i2c1_fck
, CK_343X
),
180 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck
, CK_343X
),
181 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck
, CK_343X
),
182 CLK(NULL
, "core_48m_fck", &core_48m_fck
, CK_343X
),
183 CLK("omap2_mcspi.4", "fck", &mcspi4_fck
, CK_343X
),
184 CLK("omap2_mcspi.3", "fck", &mcspi3_fck
, CK_343X
),
185 CLK("omap2_mcspi.2", "fck", &mcspi2_fck
, CK_343X
),
186 CLK("omap2_mcspi.1", "fck", &mcspi1_fck
, CK_343X
),
187 CLK(NULL
, "uart2_fck", &uart2_fck
, CK_343X
),
188 CLK(NULL
, "uart1_fck", &uart1_fck
, CK_343X
),
189 CLK(NULL
, "fshostusb_fck", &fshostusb_fck
, CK_3430ES1
),
190 CLK(NULL
, "core_12m_fck", &core_12m_fck
, CK_343X
),
191 CLK("omap_hdq.0", "fck", &hdq_fck
, CK_343X
),
192 CLK(NULL
, "ssi_ssr_fck", &ssi_ssr_fck_3430es1
, CK_3430ES1
),
193 CLK(NULL
, "ssi_ssr_fck", &ssi_ssr_fck_3430es2
, CK_3430ES2
),
194 CLK(NULL
, "ssi_sst_fck", &ssi_sst_fck_3430es1
, CK_3430ES1
),
195 CLK(NULL
, "ssi_sst_fck", &ssi_sst_fck_3430es2
, CK_3430ES2
),
196 CLK(NULL
, "core_l3_ick", &core_l3_ick
, CK_343X
),
197 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1
, CK_3430ES1
),
198 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2
, CK_3430ES2
),
199 CLK(NULL
, "sdrc_ick", &sdrc_ick
, CK_343X
),
200 CLK(NULL
, "gpmc_fck", &gpmc_fck
, CK_343X
),
201 CLK(NULL
, "security_l3_ick", &security_l3_ick
, CK_343X
),
202 CLK(NULL
, "pka_ick", &pka_ick
, CK_343X
),
203 CLK(NULL
, "core_l4_ick", &core_l4_ick
, CK_343X
),
204 CLK(NULL
, "usbtll_ick", &usbtll_ick
, CK_3430ES2
),
205 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick
, CK_3430ES2
),
206 CLK(NULL
, "icr_ick", &icr_ick
, CK_343X
),
207 CLK(NULL
, "aes2_ick", &aes2_ick
, CK_343X
),
208 CLK(NULL
, "sha12_ick", &sha12_ick
, CK_343X
),
209 CLK(NULL
, "des2_ick", &des2_ick
, CK_343X
),
210 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick
, CK_343X
),
211 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick
, CK_343X
),
212 CLK(NULL
, "mspro_ick", &mspro_ick
, CK_343X
),
213 CLK("omap_hdq.0", "ick", &hdq_ick
, CK_343X
),
214 CLK("omap2_mcspi.4", "ick", &mcspi4_ick
, CK_343X
),
215 CLK("omap2_mcspi.3", "ick", &mcspi3_ick
, CK_343X
),
216 CLK("omap2_mcspi.2", "ick", &mcspi2_ick
, CK_343X
),
217 CLK("omap2_mcspi.1", "ick", &mcspi1_ick
, CK_343X
),
218 CLK("i2c_omap.3", "ick", &i2c3_ick
, CK_343X
),
219 CLK("i2c_omap.2", "ick", &i2c2_ick
, CK_343X
),
220 CLK("i2c_omap.1", "ick", &i2c1_ick
, CK_343X
),
221 CLK(NULL
, "uart2_ick", &uart2_ick
, CK_343X
),
222 CLK(NULL
, "uart1_ick", &uart1_ick
, CK_343X
),
223 CLK(NULL
, "gpt11_ick", &gpt11_ick
, CK_343X
),
224 CLK(NULL
, "gpt10_ick", &gpt10_ick
, CK_343X
),
225 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick
, CK_343X
),
226 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick
, CK_343X
),
227 CLK(NULL
, "fac_ick", &fac_ick
, CK_3430ES1
),
228 CLK(NULL
, "mailboxes_ick", &mailboxes_ick
, CK_343X
),
229 CLK(NULL
, "omapctrl_ick", &omapctrl_ick
, CK_343X
),
230 CLK(NULL
, "ssi_l4_ick", &ssi_l4_ick
, CK_343X
),
231 CLK(NULL
, "ssi_ick", &ssi_ick_3430es1
, CK_3430ES1
),
232 CLK(NULL
, "ssi_ick", &ssi_ick_3430es2
, CK_3430ES2
),
233 CLK(NULL
, "usb_l4_ick", &usb_l4_ick
, CK_3430ES1
),
234 CLK(NULL
, "security_l4_ick2", &security_l4_ick2
, CK_343X
),
235 CLK(NULL
, "aes1_ick", &aes1_ick
, CK_343X
),
236 CLK("omap_rng", "ick", &rng_ick
, CK_343X
),
237 CLK(NULL
, "sha11_ick", &sha11_ick
, CK_343X
),
238 CLK(NULL
, "des1_ick", &des1_ick
, CK_343X
),
239 CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es1
, CK_3430ES1
),
240 CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es2
, CK_3430ES2
),
241 CLK("omapfb", "tv_fck", &dss_tv_fck
, CK_343X
),
242 CLK("omapfb", "video_fck", &dss_96m_fck
, CK_343X
),
243 CLK("omapfb", "dss2_fck", &dss2_alwon_fck
, CK_343X
),
244 CLK("omapfb", "ick", &dss_ick_3430es1
, CK_3430ES1
),
245 CLK("omapfb", "ick", &dss_ick_3430es2
, CK_3430ES2
),
246 CLK(NULL
, "cam_mclk", &cam_mclk
, CK_343X
),
247 CLK(NULL
, "cam_ick", &cam_ick
, CK_343X
),
248 CLK(NULL
, "csi2_96m_fck", &csi2_96m_fck
, CK_343X
),
249 CLK(NULL
, "usbhost_120m_fck", &usbhost_120m_fck
, CK_3430ES2
),
250 CLK(NULL
, "usbhost_48m_fck", &usbhost_48m_fck
, CK_3430ES2
),
251 CLK(NULL
, "usbhost_ick", &usbhost_ick
, CK_3430ES2
),
252 CLK(NULL
, "usim_fck", &usim_fck
, CK_3430ES2
),
253 CLK(NULL
, "gpt1_fck", &gpt1_fck
, CK_343X
),
254 CLK(NULL
, "wkup_32k_fck", &wkup_32k_fck
, CK_343X
),
255 CLK(NULL
, "gpio1_dbck", &gpio1_dbck
, CK_343X
),
256 CLK("omap_wdt", "fck", &wdt2_fck
, CK_343X
),
257 CLK(NULL
, "wkup_l4_ick", &wkup_l4_ick
, CK_343X
),
258 CLK(NULL
, "usim_ick", &usim_ick
, CK_3430ES2
),
259 CLK("omap_wdt", "ick", &wdt2_ick
, CK_343X
),
260 CLK(NULL
, "wdt1_ick", &wdt1_ick
, CK_343X
),
261 CLK(NULL
, "gpio1_ick", &gpio1_ick
, CK_343X
),
262 CLK(NULL
, "omap_32ksync_ick", &omap_32ksync_ick
, CK_343X
),
263 CLK(NULL
, "gpt12_ick", &gpt12_ick
, CK_343X
),
264 CLK(NULL
, "gpt1_ick", &gpt1_ick
, CK_343X
),
265 CLK(NULL
, "per_96m_fck", &per_96m_fck
, CK_343X
),
266 CLK(NULL
, "per_48m_fck", &per_48m_fck
, CK_343X
),
267 CLK(NULL
, "uart3_fck", &uart3_fck
, CK_343X
),
268 CLK(NULL
, "gpt2_fck", &gpt2_fck
, CK_343X
),
269 CLK(NULL
, "gpt3_fck", &gpt3_fck
, CK_343X
),
270 CLK(NULL
, "gpt4_fck", &gpt4_fck
, CK_343X
),
271 CLK(NULL
, "gpt5_fck", &gpt5_fck
, CK_343X
),
272 CLK(NULL
, "gpt6_fck", &gpt6_fck
, CK_343X
),
273 CLK(NULL
, "gpt7_fck", &gpt7_fck
, CK_343X
),
274 CLK(NULL
, "gpt8_fck", &gpt8_fck
, CK_343X
),
275 CLK(NULL
, "gpt9_fck", &gpt9_fck
, CK_343X
),
276 CLK(NULL
, "per_32k_alwon_fck", &per_32k_alwon_fck
, CK_343X
),
277 CLK(NULL
, "gpio6_dbck", &gpio6_dbck
, CK_343X
),
278 CLK(NULL
, "gpio5_dbck", &gpio5_dbck
, CK_343X
),
279 CLK(NULL
, "gpio4_dbck", &gpio4_dbck
, CK_343X
),
280 CLK(NULL
, "gpio3_dbck", &gpio3_dbck
, CK_343X
),
281 CLK(NULL
, "gpio2_dbck", &gpio2_dbck
, CK_343X
),
282 CLK(NULL
, "wdt3_fck", &wdt3_fck
, CK_343X
),
283 CLK(NULL
, "per_l4_ick", &per_l4_ick
, CK_343X
),
284 CLK(NULL
, "gpio6_ick", &gpio6_ick
, CK_343X
),
285 CLK(NULL
, "gpio5_ick", &gpio5_ick
, CK_343X
),
286 CLK(NULL
, "gpio4_ick", &gpio4_ick
, CK_343X
),
287 CLK(NULL
, "gpio3_ick", &gpio3_ick
, CK_343X
),
288 CLK(NULL
, "gpio2_ick", &gpio2_ick
, CK_343X
),
289 CLK(NULL
, "wdt3_ick", &wdt3_ick
, CK_343X
),
290 CLK(NULL
, "uart3_ick", &uart3_ick
, CK_343X
),
291 CLK(NULL
, "gpt9_ick", &gpt9_ick
, CK_343X
),
292 CLK(NULL
, "gpt8_ick", &gpt8_ick
, CK_343X
),
293 CLK(NULL
, "gpt7_ick", &gpt7_ick
, CK_343X
),
294 CLK(NULL
, "gpt6_ick", &gpt6_ick
, CK_343X
),
295 CLK(NULL
, "gpt5_ick", &gpt5_ick
, CK_343X
),
296 CLK(NULL
, "gpt4_ick", &gpt4_ick
, CK_343X
),
297 CLK(NULL
, "gpt3_ick", &gpt3_ick
, CK_343X
),
298 CLK(NULL
, "gpt2_ick", &gpt2_ick
, CK_343X
),
299 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick
, CK_343X
),
300 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick
, CK_343X
),
301 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick
, CK_343X
),
302 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck
, CK_343X
),
303 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck
, CK_343X
),
304 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck
, CK_343X
),
305 CLK(NULL
, "emu_src_ck", &emu_src_ck
, CK_343X
),
306 CLK(NULL
, "pclk_fck", &pclk_fck
, CK_343X
),
307 CLK(NULL
, "pclkx2_fck", &pclkx2_fck
, CK_343X
),
308 CLK(NULL
, "atclk_fck", &atclk_fck
, CK_343X
),
309 CLK(NULL
, "traceclk_src_fck", &traceclk_src_fck
, CK_343X
),
310 CLK(NULL
, "traceclk_fck", &traceclk_fck
, CK_343X
),
311 CLK(NULL
, "sr1_fck", &sr1_fck
, CK_343X
),
312 CLK(NULL
, "sr2_fck", &sr2_fck
, CK_343X
),
313 CLK(NULL
, "sr_l4_ick", &sr_l4_ick
, CK_343X
),
314 CLK(NULL
, "secure_32k_fck", &secure_32k_fck
, CK_343X
),
315 CLK(NULL
, "gpt12_fck", &gpt12_fck
, CK_343X
),
316 CLK(NULL
, "wdt1_fck", &wdt1_fck
, CK_343X
),
319 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
320 #define DPLL_AUTOIDLE_DISABLE 0x0
321 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
323 #define MAX_DPLL_WAIT_TRIES 1000000
325 #define MIN_SDRC_DLL_LOCK_FREQ 83000000
327 #define CYCLES_PER_MHZ 1000000
329 /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
330 #define SDRC_MPURATE_SCALE 8
332 /* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
333 #define SDRC_MPURATE_BASE_SHIFT 9
336 * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
337 * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
339 #define SDRC_MPURATE_LOOPS 96
342 * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
343 * @clk: struct clk * being enabled
344 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
345 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
347 * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
348 * from the CM_{I,F}CLKEN bit. Pass back the correct info via
349 * @idlest_reg and @idlest_bit. No return value.
351 static void omap3430es2_clk_ssi_find_idlest(struct clk
*clk
,
352 void __iomem
**idlest_reg
,
357 r
= (((__force u32
)clk
->enable_reg
& ~0xf0) | 0x20);
358 *idlest_reg
= (__force
void __iomem
*)r
;
359 *idlest_bit
= OMAP3430ES2_ST_SSI_IDLE_SHIFT
;
363 * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
364 * @clk: struct clk * being enabled
365 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
366 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
368 * Some OMAP modules on OMAP3 ES2+ chips have both initiator and
369 * target IDLEST bits. For our purposes, we are concerned with the
370 * target IDLEST bits, which exist at a different bit position than
371 * the *CLKEN bit position for these modules (DSS and USBHOST) (The
372 * default find_idlest code assumes that they are at the same
373 * position.) No return value.
375 static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk
*clk
,
376 void __iomem
**idlest_reg
,
381 r
= (((__force u32
)clk
->enable_reg
& ~0xf0) | 0x20);
382 *idlest_reg
= (__force
void __iomem
*)r
;
383 /* USBHOST_IDLE has same shift */
384 *idlest_bit
= OMAP3430ES2_ST_DSS_IDLE_SHIFT
;
388 * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
389 * @clk: struct clk * being enabled
390 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
391 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
393 * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
394 * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
395 * @idlest_reg and @idlest_bit. No return value.
397 static void omap3430es2_clk_hsotgusb_find_idlest(struct clk
*clk
,
398 void __iomem
**idlest_reg
,
403 r
= (((__force u32
)clk
->enable_reg
& ~0xf0) | 0x20);
404 *idlest_reg
= (__force
void __iomem
*)r
;
405 *idlest_bit
= OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT
;
409 * omap3_dpll_recalc - recalculate DPLL rate
410 * @clk: DPLL struct clk
412 * Recalculate and propagate the DPLL rate.
414 static unsigned long omap3_dpll_recalc(struct clk
*clk
)
416 return omap2_get_dpll_rate(clk
);
419 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
420 static void _omap3_dpll_write_clken(struct clk
*clk
, u8 clken_bits
)
422 const struct dpll_data
*dd
;
427 v
= __raw_readl(dd
->control_reg
);
428 v
&= ~dd
->enable_mask
;
429 v
|= clken_bits
<< __ffs(dd
->enable_mask
);
430 __raw_writel(v
, dd
->control_reg
);
433 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
434 static int _omap3_wait_dpll_status(struct clk
*clk
, u8 state
)
436 const struct dpll_data
*dd
;
442 state
<<= __ffs(dd
->idlest_mask
);
444 while (((__raw_readl(dd
->idlest_reg
) & dd
->idlest_mask
) != state
) &&
445 i
< MAX_DPLL_WAIT_TRIES
) {
450 if (i
== MAX_DPLL_WAIT_TRIES
) {
451 printk(KERN_ERR
"clock: %s failed transition to '%s'\n",
452 clk
->name
, (state
) ? "locked" : "bypassed");
454 pr_debug("clock: %s transition to '%s' in %d loops\n",
455 clk
->name
, (state
) ? "locked" : "bypassed", i
);
463 /* From 3430 TRM ES2 4.7.6.2 */
464 static u16
_omap3_dpll_compute_freqsel(struct clk
*clk
, u8 n
)
469 fint
= clk
->dpll_data
->clk_ref
->rate
/ (n
+ 1);
471 pr_debug("clock: fint is %lu\n", fint
);
473 if (fint
>= 750000 && fint
<= 1000000)
475 else if (fint
> 1000000 && fint
<= 1250000)
477 else if (fint
> 1250000 && fint
<= 1500000)
479 else if (fint
> 1500000 && fint
<= 1750000)
481 else if (fint
> 1750000 && fint
<= 2100000)
483 else if (fint
> 7500000 && fint
<= 10000000)
485 else if (fint
> 10000000 && fint
<= 12500000)
487 else if (fint
> 12500000 && fint
<= 15000000)
489 else if (fint
> 15000000 && fint
<= 17500000)
491 else if (fint
> 17500000 && fint
<= 21000000)
494 pr_debug("clock: unknown freqsel setting for %d\n", n
);
499 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
502 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
503 * @clk: pointer to a DPLL struct clk
505 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
506 * readiness before returning. Will save and restore the DPLL's
507 * autoidle state across the enable, per the CDP code. If the DPLL
508 * locked successfully, return 0; if the DPLL did not lock in the time
509 * allotted, or DPLL3 was passed in, return -EINVAL.
511 static int _omap3_noncore_dpll_lock(struct clk
*clk
)
516 if (clk
== &dpll3_ck
)
519 pr_debug("clock: locking DPLL %s\n", clk
->name
);
521 ai
= omap3_dpll_autoidle_read(clk
);
523 omap3_dpll_deny_idle(clk
);
525 _omap3_dpll_write_clken(clk
, DPLL_LOCKED
);
527 r
= _omap3_wait_dpll_status(clk
, 1);
530 omap3_dpll_allow_idle(clk
);
536 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
537 * @clk: pointer to a DPLL struct clk
539 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
540 * bypass mode, the DPLL's rate is set equal to its parent clock's
541 * rate. Waits for the DPLL to report readiness before returning.
542 * Will save and restore the DPLL's autoidle state across the enable,
543 * per the CDP code. If the DPLL entered bypass mode successfully,
544 * return 0; if the DPLL did not enter bypass in the time allotted, or
545 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
548 static int _omap3_noncore_dpll_bypass(struct clk
*clk
)
553 if (clk
== &dpll3_ck
)
556 if (!(clk
->dpll_data
->modes
& (1 << DPLL_LOW_POWER_BYPASS
)))
559 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
562 ai
= omap3_dpll_autoidle_read(clk
);
564 _omap3_dpll_write_clken(clk
, DPLL_LOW_POWER_BYPASS
);
566 r
= _omap3_wait_dpll_status(clk
, 0);
569 omap3_dpll_allow_idle(clk
);
571 omap3_dpll_deny_idle(clk
);
577 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
578 * @clk: pointer to a DPLL struct clk
580 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
581 * restore the DPLL's autoidle state across the stop, per the CDP
582 * code. If DPLL3 was passed in, or the DPLL does not support
583 * low-power stop, return -EINVAL; otherwise, return 0.
585 static int _omap3_noncore_dpll_stop(struct clk
*clk
)
589 if (clk
== &dpll3_ck
)
592 if (!(clk
->dpll_data
->modes
& (1 << DPLL_LOW_POWER_STOP
)))
595 pr_debug("clock: stopping DPLL %s\n", clk
->name
);
597 ai
= omap3_dpll_autoidle_read(clk
);
599 _omap3_dpll_write_clken(clk
, DPLL_LOW_POWER_STOP
);
602 omap3_dpll_allow_idle(clk
);
604 omap3_dpll_deny_idle(clk
);
610 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
611 * @clk: pointer to a DPLL struct clk
613 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
614 * The choice of modes depends on the DPLL's programmed rate: if it is
615 * the same as the DPLL's parent clock, it will enter bypass;
616 * otherwise, it will enter lock. This code will wait for the DPLL to
617 * indicate readiness before returning, unless the DPLL takes too long
618 * to enter the target state. Intended to be used as the struct clk's
619 * enable function. If DPLL3 was passed in, or the DPLL does not
620 * support low-power stop, or if the DPLL took too long to enter
621 * bypass or lock, return -EINVAL; otherwise, return 0.
623 static int omap3_noncore_dpll_enable(struct clk
*clk
)
626 struct dpll_data
*dd
;
628 if (clk
== &dpll3_ck
)
635 if (clk
->rate
== dd
->clk_bypass
->rate
) {
636 WARN_ON(clk
->parent
!= dd
->clk_bypass
);
637 r
= _omap3_noncore_dpll_bypass(clk
);
639 WARN_ON(clk
->parent
!= dd
->clk_ref
);
640 r
= _omap3_noncore_dpll_lock(clk
);
642 /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */
644 clk
->rate
= omap2_get_dpll_rate(clk
);
650 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
651 * @clk: pointer to a DPLL struct clk
653 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
654 * The choice of modes depends on the DPLL's programmed rate: if it is
655 * the same as the DPLL's parent clock, it will enter bypass;
656 * otherwise, it will enter lock. This code will wait for the DPLL to
657 * indicate readiness before returning, unless the DPLL takes too long
658 * to enter the target state. Intended to be used as the struct clk's
659 * enable function. If DPLL3 was passed in, or the DPLL does not
660 * support low-power stop, or if the DPLL took too long to enter
661 * bypass or lock, return -EINVAL; otherwise, return 0.
663 static void omap3_noncore_dpll_disable(struct clk
*clk
)
665 if (clk
== &dpll3_ck
)
668 _omap3_noncore_dpll_stop(clk
);
672 /* Non-CORE DPLL rate set code */
675 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
676 * @clk: struct clk * of DPLL to set
677 * @m: DPLL multiplier to set
678 * @n: DPLL divider to set
679 * @freqsel: FREQSEL value to set
681 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
682 * lock.. Returns -EINVAL upon error, or 0 upon success.
684 static int omap3_noncore_dpll_program(struct clk
*clk
, u16 m
, u8 n
, u16 freqsel
)
686 struct dpll_data
*dd
= clk
->dpll_data
;
689 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
690 _omap3_noncore_dpll_bypass(clk
);
692 /* Set jitter correction */
693 v
= __raw_readl(dd
->control_reg
);
694 v
&= ~dd
->freqsel_mask
;
695 v
|= freqsel
<< __ffs(dd
->freqsel_mask
);
696 __raw_writel(v
, dd
->control_reg
);
698 /* Set DPLL multiplier, divider */
699 v
= __raw_readl(dd
->mult_div1_reg
);
700 v
&= ~(dd
->mult_mask
| dd
->div1_mask
);
701 v
|= m
<< __ffs(dd
->mult_mask
);
702 v
|= (n
- 1) << __ffs(dd
->div1_mask
);
703 __raw_writel(v
, dd
->mult_div1_reg
);
705 /* We let the clock framework set the other output dividers later */
707 /* REVISIT: Set ramp-up delay? */
709 _omap3_noncore_dpll_lock(clk
);
715 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
716 * @clk: struct clk * of DPLL to set
717 * @rate: rounded target rate
719 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
720 * low-power bypass, and the target rate is the bypass source clock
721 * rate, then configure the DPLL for bypass. Otherwise, round the
722 * target rate if it hasn't been done already, then program and lock
723 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
725 static int omap3_noncore_dpll_set_rate(struct clk
*clk
, unsigned long rate
)
727 struct clk
*new_parent
= NULL
;
729 struct dpll_data
*dd
;
739 if (rate
== omap2_get_dpll_rate(clk
))
743 * Ensure both the bypass and ref clocks are enabled prior to
744 * doing anything; we need the bypass clock running to reprogram
747 omap2_clk_enable(dd
->clk_bypass
);
748 omap2_clk_enable(dd
->clk_ref
);
750 if (dd
->clk_bypass
->rate
== rate
&&
751 (clk
->dpll_data
->modes
& (1 << DPLL_LOW_POWER_BYPASS
))) {
752 pr_debug("clock: %s: set rate: entering bypass.\n", clk
->name
);
754 ret
= _omap3_noncore_dpll_bypass(clk
);
756 new_parent
= dd
->clk_bypass
;
758 if (dd
->last_rounded_rate
!= rate
)
759 omap2_dpll_round_rate(clk
, rate
);
761 if (dd
->last_rounded_rate
== 0)
764 freqsel
= _omap3_dpll_compute_freqsel(clk
, dd
->last_rounded_n
);
768 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
771 ret
= omap3_noncore_dpll_program(clk
, dd
->last_rounded_m
,
772 dd
->last_rounded_n
, freqsel
);
774 new_parent
= dd
->clk_ref
;
778 * Switch the parent clock in the heirarchy, and make sure
779 * that the new parent's usecount is correct. Note: we
780 * enable the new parent before disabling the old to avoid
781 * any unnecessary hardware disable->enable transitions.
784 omap2_clk_enable(new_parent
);
785 omap2_clk_disable(clk
->parent
);
787 clk_reparent(clk
, new_parent
);
790 omap2_clk_disable(dd
->clk_ref
);
791 omap2_clk_disable(dd
->clk_bypass
);
796 static int omap3_dpll4_set_rate(struct clk
*clk
, unsigned long rate
)
799 * According to the 12-5 CDP code from TI, "Limitation 2.5"
800 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
803 if (omap_rev() == OMAP3430_REV_ES1_0
) {
804 printk(KERN_ERR
"clock: DPLL4 cannot change rate due to "
805 "silicon 'Limitation 2.5' on 3430ES1.\n");
808 return omap3_noncore_dpll_set_rate(clk
, rate
);
813 * CORE DPLL (DPLL3) rate programming functions
815 * These call into SRAM code to do the actual CM writes, since the SDRAM
816 * is clocked from DPLL3.
820 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
821 * @clk: struct clk * of DPLL to set
822 * @rate: rounded target rate
824 * Program the DPLL M2 divider with the rounded target rate. Returns
825 * -EINVAL upon error, or 0 upon success.
827 static int omap3_core_dpll_m2_set_rate(struct clk
*clk
, unsigned long rate
)
832 unsigned long validrate
, sdrcrate
, mpurate
;
833 struct omap_sdrc_params
*sdrc_cs0
;
834 struct omap_sdrc_params
*sdrc_cs1
;
840 if (clk
!= &dpll3_m2_ck
)
843 validrate
= omap2_clksel_round_rate_div(clk
, rate
, &new_div
);
844 if (validrate
!= rate
)
847 sdrcrate
= sdrc_ick
.rate
;
848 if (rate
> clk
->rate
)
849 sdrcrate
<<= ((rate
/ clk
->rate
) >> 1);
851 sdrcrate
>>= ((clk
->rate
/ rate
) >> 1);
853 ret
= omap2_sdrc_get_params(sdrcrate
, &sdrc_cs0
, &sdrc_cs1
);
857 if (sdrcrate
< MIN_SDRC_DLL_LOCK_FREQ
) {
858 pr_debug("clock: will unlock SDRC DLL\n");
863 * XXX This only needs to be done when the CPU frequency changes
865 mpurate
= arm_fck
.rate
/ CYCLES_PER_MHZ
;
866 c
= (mpurate
<< SDRC_MPURATE_SCALE
) >> SDRC_MPURATE_BASE_SHIFT
;
867 c
+= 1; /* for safety */
868 c
*= SDRC_MPURATE_LOOPS
;
869 c
>>= SDRC_MPURATE_SCALE
;
873 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk
->rate
,
875 pr_debug("clock: SDRC CS0 timing params used:"
876 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
877 sdrc_cs0
->rfr_ctrl
, sdrc_cs0
->actim_ctrla
,
878 sdrc_cs0
->actim_ctrlb
, sdrc_cs0
->mr
);
880 pr_debug("clock: SDRC CS1 timing params used: "
881 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
882 sdrc_cs1
->rfr_ctrl
, sdrc_cs1
->actim_ctrla
,
883 sdrc_cs1
->actim_ctrlb
, sdrc_cs1
->mr
);
886 omap3_configure_core_dpll(
887 new_div
, unlock_dll
, c
, rate
> clk
->rate
,
888 sdrc_cs0
->rfr_ctrl
, sdrc_cs0
->actim_ctrla
,
889 sdrc_cs0
->actim_ctrlb
, sdrc_cs0
->mr
,
890 sdrc_cs1
->rfr_ctrl
, sdrc_cs1
->actim_ctrla
,
891 sdrc_cs1
->actim_ctrlb
, sdrc_cs1
->mr
);
893 omap3_configure_core_dpll(
894 new_div
, unlock_dll
, c
, rate
> clk
->rate
,
895 sdrc_cs0
->rfr_ctrl
, sdrc_cs0
->actim_ctrla
,
896 sdrc_cs0
->actim_ctrlb
, sdrc_cs0
->mr
,
903 static const struct clkops clkops_noncore_dpll_ops
= {
904 .enable
= &omap3_noncore_dpll_enable
,
905 .disable
= &omap3_noncore_dpll_disable
,
908 /* DPLL autoidle read/set code */
912 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
913 * @clk: struct clk * of the DPLL to read
915 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
916 * -EINVAL if passed a null pointer or if the struct clk does not
917 * appear to refer to a DPLL.
919 static u32
omap3_dpll_autoidle_read(struct clk
*clk
)
921 const struct dpll_data
*dd
;
924 if (!clk
|| !clk
->dpll_data
)
929 v
= __raw_readl(dd
->autoidle_reg
);
930 v
&= dd
->autoidle_mask
;
931 v
>>= __ffs(dd
->autoidle_mask
);
937 * omap3_dpll_allow_idle - enable DPLL autoidle bits
938 * @clk: struct clk * of the DPLL to operate on
940 * Enable DPLL automatic idle control. This automatic idle mode
941 * switching takes effect only when the DPLL is locked, at least on
942 * OMAP3430. The DPLL will enter low-power stop when its downstream
943 * clocks are gated. No return value.
945 static void omap3_dpll_allow_idle(struct clk
*clk
)
947 const struct dpll_data
*dd
;
950 if (!clk
|| !clk
->dpll_data
)
956 * REVISIT: CORE DPLL can optionally enter low-power bypass
957 * by writing 0x5 instead of 0x1. Add some mechanism to
958 * optionally enter this mode.
960 v
= __raw_readl(dd
->autoidle_reg
);
961 v
&= ~dd
->autoidle_mask
;
962 v
|= DPLL_AUTOIDLE_LOW_POWER_STOP
<< __ffs(dd
->autoidle_mask
);
963 __raw_writel(v
, dd
->autoidle_reg
);
967 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
968 * @clk: struct clk * of the DPLL to operate on
970 * Disable DPLL automatic idle control. No return value.
972 static void omap3_dpll_deny_idle(struct clk
*clk
)
974 const struct dpll_data
*dd
;
977 if (!clk
|| !clk
->dpll_data
)
982 v
= __raw_readl(dd
->autoidle_reg
);
983 v
&= ~dd
->autoidle_mask
;
984 v
|= DPLL_AUTOIDLE_DISABLE
<< __ffs(dd
->autoidle_mask
);
985 __raw_writel(v
, dd
->autoidle_reg
);
988 /* Clock control for DPLL outputs */
991 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
992 * @clk: DPLL output struct clk
994 * Using parent clock DPLL data, look up DPLL state. If locked, set our
995 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
997 static unsigned long omap3_clkoutx2_recalc(struct clk
*clk
)
999 const struct dpll_data
*dd
;
1004 /* Walk up the parents of clk, looking for a DPLL */
1006 while (pclk
&& !pclk
->dpll_data
)
1007 pclk
= pclk
->parent
;
1009 /* clk does not have a DPLL as a parent? */
1012 dd
= pclk
->dpll_data
;
1014 WARN_ON(!dd
->enable_mask
);
1016 v
= __raw_readl(dd
->control_reg
) & dd
->enable_mask
;
1017 v
>>= __ffs(dd
->enable_mask
);
1018 if (v
!= OMAP3XXX_EN_DPLL_LOCKED
)
1019 rate
= clk
->parent
->rate
;
1021 rate
= clk
->parent
->rate
* 2;
1025 /* Common clock code */
1028 * As it is structured now, this will prevent an OMAP2/3 multiboot
1029 * kernel from compiling. This will need further attention.
1031 #if defined(CONFIG_ARCH_OMAP3)
1033 static struct clk_functions omap2_clk_functions
= {
1034 .clk_enable
= omap2_clk_enable
,
1035 .clk_disable
= omap2_clk_disable
,
1036 .clk_round_rate
= omap2_clk_round_rate
,
1037 .clk_set_rate
= omap2_clk_set_rate
,
1038 .clk_set_parent
= omap2_clk_set_parent
,
1039 .clk_disable_unused
= omap2_clk_disable_unused
,
1043 * Set clocks for bypass mode for reboot to work.
1045 void omap2_clk_prepare_for_reboot(void)
1047 /* REVISIT: Not ready for 343x */
1051 if (vclk
== NULL
|| sclk
== NULL
)
1054 rate
= clk_get_rate(sclk
);
1055 clk_set_rate(vclk
, rate
);
1059 /* REVISIT: Move this init stuff out into clock.c */
1062 * Switch the MPU rate if specified on cmdline.
1063 * We cannot do this early until cmdline is parsed.
1065 static int __init
omap2_clk_arch_init(void)
1070 /* REVISIT: not yet ready for 343x */
1071 if (clk_set_rate(&dpll1_ck
, mpurate
))
1072 printk(KERN_ERR
"*** Unable to set MPU rate\n");
1074 recalculate_root_clocks();
1076 printk(KERN_INFO
"Switched to new clocking rate (Crystal/Core/MPU): "
1077 "%ld.%01ld/%ld/%ld MHz\n",
1078 (osc_sys_ck
.rate
/ 1000000), ((osc_sys_ck
.rate
/ 100000) % 10),
1079 (core_ck
.rate
/ 1000000), (arm_fck
.rate
/ 1000000)) ;
1085 arch_initcall(omap2_clk_arch_init
);
1087 int __init
omap2_clk_init(void)
1089 /* struct prcm_config *prcm; */
1094 if (cpu_is_omap34xx()) {
1095 cpu_mask
= RATE_IN_343X
;
1096 cpu_clkflg
= CK_343X
;
1099 * Update this if there are further clock changes between ES2
1100 * and production parts
1102 if (omap_rev() == OMAP3430_REV_ES1_0
) {
1103 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
1104 cpu_clkflg
|= CK_3430ES1
;
1106 cpu_mask
|= RATE_IN_3430ES2
;
1107 cpu_clkflg
|= CK_3430ES2
;
1111 clk_init(&omap2_clk_functions
);
1113 for (c
= omap34xx_clks
; c
< omap34xx_clks
+ ARRAY_SIZE(omap34xx_clks
); c
++)
1114 clk_preinit(c
->lk
.clk
);
1116 for (c
= omap34xx_clks
; c
< omap34xx_clks
+ ARRAY_SIZE(omap34xx_clks
); c
++)
1117 if (c
->cpu
& cpu_clkflg
) {
1119 clk_register(c
->lk
.clk
);
1120 omap2_init_clk_clkdm(c
->lk
.clk
);
1123 /* REVISIT: Not yet ready for OMAP3 */
1125 /* Check the MPU rate set by bootloader */
1126 clkrate
= omap2_get_dpll_rate_24xx(&dpll_ck
);
1127 for (prcm
= rate_table
; prcm
->mpu_speed
; prcm
++) {
1128 if (!(prcm
->flags
& cpu_mask
))
1130 if (prcm
->xtal_speed
!= sys_ck
.rate
)
1132 if (prcm
->dpll_speed
<= clkrate
)
1135 curr_prcm_set
= prcm
;
1138 recalculate_root_clocks();
1140 printk(KERN_INFO
"Clocking rate (Crystal/Core/MPU): "
1141 "%ld.%01ld/%ld/%ld MHz\n",
1142 (osc_sys_ck
.rate
/ 1000000), (osc_sys_ck
.rate
/ 100000) % 10,
1143 (core_ck
.rate
/ 1000000), (arm_fck
.rate
/ 1000000));
1146 * Only enable those clocks we will need, let the drivers
1147 * enable other clocks as necessary
1149 clk_enable_init_clocks();
1151 /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
1152 /* REVISIT: not yet ready for 343x */
1154 vclk
= clk_get(NULL
, "virt_prcm_set");
1155 sclk
= clk_get(NULL
, "sys_ck");