arch/arm/mach-omap2/clock34xx.c

   1 /*
   2  * OMAP3-specific clock framework functions
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2009 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * Testing and integration fixes by Jouni Högander
   9  *
  10  * Parts of this code are based on code written by
  11  * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17 #undef DEBUG
  18
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/device.h>
  22 #include <linux/list.h>
  23 #include <linux/errno.h>
  24 #include <linux/delay.h>
  25 #include <linux/clk.h>
  26 #include <linux/io.h>
  27 #include <linux/limits.h>
  28 #include <linux/bitops.h>
  29
  30 #include <plat/cpu.h>
  31 #include <plat/clock.h>
  32 #include <plat/sram.h>
  33 #include <plat/sdrc.h>
  34 #include <asm/div64.h>
  35 #include <asm/clkdev.h>
  36
  37 #include "clock.h"
  38 #include "clock34xx.h"
  39 #include "sdrc.h"
  40 #include "prm.h"
  41 #include "prm-regbits-34xx.h"
  42 #include "cm.h"
  43 #include "cm-regbits-34xx.h"
  44
  45 #define CYCLES_PER_MHZ                  1000000
  46
  47 /*
  48  * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
  49  * that are sourced by DPLL5, and both of these require this clock
  50  * to be at 120 MHz for proper operation.
  51  */
  52 #define DPLL5_FREQ_FOR_USBHOST          120000000
  53
  54 /* needed by omap3_core_dpll_m2_set_rate() */
  55 struct clk *sdrc_ick_p, *arm_fck_p;
  56
  57 /**
  58  * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
  59  * @clk: struct clk * being enabled
  60  * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
  61  * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
  62  *
  63  * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
  64  * from the CM_{I,F}CLKEN bit.  Pass back the correct info via
  65  * @idlest_reg and @idlest_bit.  No return value.
  66  */
  67 static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
  68                                             void __iomem **idlest_reg,
  69                                             u8 *idlest_bit)
  70 {
  71         u32 r;
  72
  73         r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
  74         *idlest_reg = (__force void __iomem *)r;
  75         *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
  76 }
  77
  78 const struct clkops clkops_omap3430es2_ssi_wait = {
  79         .enable         = omap2_dflt_clk_enable,
  80         .disable        = omap2_dflt_clk_disable,
  81         .find_idlest    = omap3430es2_clk_ssi_find_idlest,
  82         .find_companion = omap2_clk_dflt_find_companion,
  83 };
  84
  85 /**
  86  * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
  87  * @clk: struct clk * being enabled
  88  * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
  89  * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
  90  *
  91  * Some OMAP modules on OMAP3 ES2+ chips have both initiator and
  92  * target IDLEST bits.  For our purposes, we are concerned with the
  93  * target IDLEST bits, which exist at a different bit position than
  94  * the *CLKEN bit position for these modules (DSS and USBHOST) (The
  95  * default find_idlest code assumes that they are at the same
  96  * position.)  No return value.
  97  */
  98 static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
  99                                                     void __iomem **idlest_reg,
 100                                                     u8 *idlest_bit)
 101 {
 102         u32 r;
 103
 104         r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
 105         *idlest_reg = (__force void __iomem *)r;
 106         /* USBHOST_IDLE has same shift */
 107         *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
 108 }
 109
 110 const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
 111         .enable         = omap2_dflt_clk_enable,
 112         .disable        = omap2_dflt_clk_disable,
 113         .find_idlest    = omap3430es2_clk_dss_usbhost_find_idlest,
 114         .find_companion = omap2_clk_dflt_find_companion,
 115 };
 116
 117 /**
 118  * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
 119  * @clk: struct clk * being enabled
 120  * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
 121  * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
 122  *
 123  * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
 124  * shift from the CM_{I,F}CLKEN bit.  Pass back the correct info via
 125  * @idlest_reg and @idlest_bit.  No return value.
 126  */
 127 static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
 128                                                  void __iomem **idlest_reg,
 129                                                  u8 *idlest_bit)
 130 {
 131         u32 r;
 132
 133         r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
 134         *idlest_reg = (__force void __iomem *)r;
 135         *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
 136 }
 137
 138 const struct clkops clkops_omap3430es2_hsotgusb_wait = {
 139         .enable         = omap2_dflt_clk_enable,
 140         .disable        = omap2_dflt_clk_disable,
 141         .find_idlest    = omap3430es2_clk_hsotgusb_find_idlest,
 142         .find_companion = omap2_clk_dflt_find_companion,
 143 };
 144
 145 const struct clkops clkops_noncore_dpll_ops = {
 146         .enable         = omap3_noncore_dpll_enable,
 147         .disable        = omap3_noncore_dpll_disable,
 148 };
 149
 150 int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
 151 {
 152         /*
 153          * According to the 12-5 CDP code from TI, "Limitation 2.5"
 154          * on 3430ES1 prevents us from changing DPLL multipliers or dividers
 155          * on DPLL4.
 156          */
 157         if (omap_rev() == OMAP3430_REV_ES1_0) {
 158                 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
 159                        "silicon 'Limitation 2.5' on 3430ES1.\n");
 160                 return -EINVAL;
 161         }
 162         return omap3_noncore_dpll_set_rate(clk, rate);
 163 }
 164
 165
 166 /*
 167  * CORE DPLL (DPLL3) rate programming functions
 168  *
 169  * These call into SRAM code to do the actual CM writes, since the SDRAM
 170  * is clocked from DPLL3.
 171  */
 172
 173 /**
 174  * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
 175  * @clk: struct clk * of DPLL to set
 176  * @rate: rounded target rate
 177  *
 178  * Program the DPLL M2 divider with the rounded target rate.  Returns
 179  * -EINVAL upon error, or 0 upon success.
 180  */
 181 int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 182 {
 183         u32 new_div = 0;
 184         u32 unlock_dll = 0;
 185         u32 c;
 186         unsigned long validrate, sdrcrate, _mpurate;
 187         struct omap_sdrc_params *sdrc_cs0;
 188         struct omap_sdrc_params *sdrc_cs1;
 189         int ret;
 190
 191         if (!clk || !rate)
 192                 return -EINVAL;
 193
 194         validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
 195         if (validrate != rate)
 196                 return -EINVAL;
 197
 198         sdrcrate = sdrc_ick_p->rate;
 199         if (rate > clk->rate)
 200                 sdrcrate <<= ((rate / clk->rate) >> 1);
 201         else
 202                 sdrcrate >>= ((clk->rate / rate) >> 1);
 203
 204         ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
 205         if (ret)
 206                 return -EINVAL;
 207
 208         if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
 209                 pr_debug("clock: will unlock SDRC DLL\n");
 210                 unlock_dll = 1;
 211         }
 212
 213         /*
 214          * XXX This only needs to be done when the CPU frequency changes
 215          */
 216         _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
 217         c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
 218         c += 1;  /* for safety */
 219         c *= SDRC_MPURATE_LOOPS;
 220         c >>= SDRC_MPURATE_SCALE;
 221         if (c == 0)
 222                 c = 1;
 223
 224         pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
 225                  validrate);
 226         pr_debug("clock: SDRC CS0 timing params used:"
 227                  " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
 228                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
 229                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
 230         if (sdrc_cs1)
 231                 pr_debug("clock: SDRC CS1 timing params used: "
 232                  " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
 233                  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
 234                  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
 235
 236         if (sdrc_cs1)
 237                 omap3_configure_core_dpll(
 238                                   new_div, unlock_dll, c, rate > clk->rate,
 239                                   sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
 240                                   sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
 241                                   sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
 242                                   sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
 243         else
 244                 omap3_configure_core_dpll(
 245                                   new_div, unlock_dll, c, rate > clk->rate,
 246                                   sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
 247                                   sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
 248                                   0, 0, 0, 0);
 249
 250         return 0;
 251 }
 252
 253 /* Common clock code */
 254
 255 /*
 256  * As it is structured now, this will prevent an OMAP2/3 multiboot
 257  * kernel from compiling.  This will need further attention.
 258  */
 259 #if defined(CONFIG_ARCH_OMAP3)
 260
 261 struct clk_functions omap2_clk_functions = {
 262         .clk_enable             = omap2_clk_enable,
 263         .clk_disable            = omap2_clk_disable,
 264         .clk_round_rate         = omap2_clk_round_rate,
 265         .clk_set_rate           = omap2_clk_set_rate,
 266         .clk_set_parent         = omap2_clk_set_parent,
 267         .clk_disable_unused     = omap2_clk_disable_unused,
 268 };
 269
 270 /*
 271  * Set clocks for bypass mode for reboot to work.
 272  */
 273 void omap2_clk_prepare_for_reboot(void)
 274 {
 275         /* REVISIT: Not ready for 343x */
 276 #if 0
 277         u32 rate;
 278
 279         if (vclk == NULL || sclk == NULL)
 280                 return;
 281
 282         rate = clk_get_rate(sclk);
 283         clk_set_rate(vclk, rate);
 284 #endif
 285 }
 286
 287 void omap3_clk_lock_dpll5(void)
 288 {
 289         struct clk *dpll5_clk;
 290         struct clk *dpll5_m2_clk;
 291
 292         dpll5_clk = clk_get(NULL, "dpll5_ck");
 293         clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
 294         clk_enable(dpll5_clk);
 295
 296         /* Enable autoidle to allow it to enter low power bypass */
 297         omap3_dpll_allow_idle(dpll5_clk);
 298
 299         /* Program dpll5_m2_clk divider for no division */
 300         dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
 301         clk_enable(dpll5_m2_clk);
 302         clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
 303
 304         clk_disable(dpll5_m2_clk);
 305         clk_disable(dpll5_clk);
 306         return;
 307 }
 308
 309 /* REVISIT: Move this init stuff out into clock.c */
 310
 311 /*
 312  * Switch the MPU rate if specified on cmdline.
 313  * We cannot do this early until cmdline is parsed.
 314  */
 315 static int __init omap2_clk_arch_init(void)
 316 {
 317         struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck;
 318         unsigned long osc_sys_rate;
 319
 320         if (!mpurate)
 321                 return -EINVAL;
 322
 323         /* XXX test these for success */
 324         dpll1_ck = clk_get(NULL, "dpll1_ck");
 325         arm_fck = clk_get(NULL, "arm_fck");
 326         core_ck = clk_get(NULL, "core_ck");
 327         osc_sys_ck = clk_get(NULL, "osc_sys_ck");
 328
 329         /* REVISIT: not yet ready for 343x */
 330         if (clk_set_rate(dpll1_ck, mpurate))
 331                 printk(KERN_ERR "*** Unable to set MPU rate\n");
 332
 333         recalculate_root_clocks();
 334
 335         osc_sys_rate = clk_get_rate(osc_sys_ck);
 336
 337         pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
 338                 "%ld.%01ld/%ld/%ld MHz\n",
 339                 (osc_sys_rate / 1000000),
 340                 ((osc_sys_rate / 100000) % 10),
 341                 (clk_get_rate(core_ck) / 1000000),
 342                 (clk_get_rate(arm_fck) / 1000000));
 343
 344         calibrate_delay();
 345
 346         return 0;
 347 }
 348 arch_initcall(omap2_clk_arch_init);
 349
 350
 351 #endif
 352
 353