4 * Copyright (C) 2007-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
19 #include <linux/kernel.h>
20 #include <linux/clk.h>
21 #include <linux/list.h>
24 #include <plat/hardware.h>
25 #include <plat/clkdev_omap.h>
29 #include "clock3xxx.h"
30 #include "clock34xx.h"
31 #include "clock36xx.h"
32 #include "clock3517.h"
33 #include "cm2xxx_3xxx.h"
34 #include "cm-regbits-34xx.h"
35 #include "prm2xxx_3xxx.h"
36 #include "prm-regbits-34xx.h"
43 #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
45 /* Maximum DPLL multiplier, divider values for OMAP3 */
46 #define OMAP3_MAX_DPLL_MULT 2047
47 #define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
48 #define OMAP3_MAX_DPLL_DIV 128
51 * DPLL1 supplies clock to the MPU.
52 * DPLL2 supplies clock to the IVA2.
53 * DPLL3 supplies CORE domain clocks.
54 * DPLL4 supplies peripheral clocks.
55 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
58 /* Forward declarations for DPLL bypass clocks */
59 static struct clk dpll1_fck
;
60 static struct clk dpll2_fck
;
64 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
65 static struct clk omap_32k_fck
= {
66 .name
= "omap_32k_fck",
71 static struct clk secure_32k_fck
= {
72 .name
= "secure_32k_fck",
77 /* Virtual source clocks for osc_sys_ck */
78 static struct clk virt_12m_ck
= {
79 .name
= "virt_12m_ck",
84 static struct clk virt_13m_ck
= {
85 .name
= "virt_13m_ck",
90 static struct clk virt_16_8m_ck
= {
91 .name
= "virt_16_8m_ck",
96 static struct clk virt_19_2m_ck
= {
97 .name
= "virt_19_2m_ck",
102 static struct clk virt_26m_ck
= {
103 .name
= "virt_26m_ck",
108 static struct clk virt_38_4m_ck
= {
109 .name
= "virt_38_4m_ck",
114 static const struct clksel_rate osc_sys_12m_rates
[] = {
115 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
119 static const struct clksel_rate osc_sys_13m_rates
[] = {
120 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
124 static const struct clksel_rate osc_sys_16_8m_rates
[] = {
125 { .div
= 1, .val
= 5, .flags
= RATE_IN_3430ES2PLUS_36XX
},
129 static const struct clksel_rate osc_sys_19_2m_rates
[] = {
130 { .div
= 1, .val
= 2, .flags
= RATE_IN_3XXX
},
134 static const struct clksel_rate osc_sys_26m_rates
[] = {
135 { .div
= 1, .val
= 3, .flags
= RATE_IN_3XXX
},
139 static const struct clksel_rate osc_sys_38_4m_rates
[] = {
140 { .div
= 1, .val
= 4, .flags
= RATE_IN_3XXX
},
144 static const struct clksel osc_sys_clksel
[] = {
145 { .parent
= &virt_12m_ck
, .rates
= osc_sys_12m_rates
},
146 { .parent
= &virt_13m_ck
, .rates
= osc_sys_13m_rates
},
147 { .parent
= &virt_16_8m_ck
, .rates
= osc_sys_16_8m_rates
},
148 { .parent
= &virt_19_2m_ck
, .rates
= osc_sys_19_2m_rates
},
149 { .parent
= &virt_26m_ck
, .rates
= osc_sys_26m_rates
},
150 { .parent
= &virt_38_4m_ck
, .rates
= osc_sys_38_4m_rates
},
154 /* Oscillator clock */
155 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
156 static struct clk osc_sys_ck
= {
157 .name
= "osc_sys_ck",
159 .init
= &omap2_init_clksel_parent
,
160 .clksel_reg
= OMAP3430_PRM_CLKSEL
,
161 .clksel_mask
= OMAP3430_SYS_CLKIN_SEL_MASK
,
162 .clksel
= osc_sys_clksel
,
163 /* REVISIT: deal with autoextclkmode? */
164 .recalc
= &omap2_clksel_recalc
,
167 static const struct clksel_rate div2_rates
[] = {
168 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
169 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
173 static const struct clksel sys_clksel
[] = {
174 { .parent
= &osc_sys_ck
, .rates
= div2_rates
},
178 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
179 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
180 static struct clk sys_ck
= {
183 .parent
= &osc_sys_ck
,
184 .init
= &omap2_init_clksel_parent
,
185 .clksel_reg
= OMAP3430_PRM_CLKSRC_CTRL
,
186 .clksel_mask
= OMAP_SYSCLKDIV_MASK
,
187 .clksel
= sys_clksel
,
188 .recalc
= &omap2_clksel_recalc
,
191 static struct clk sys_altclk
= {
192 .name
= "sys_altclk",
196 /* Optional external clock input for some McBSPs */
197 static struct clk mcbsp_clks
= {
198 .name
= "mcbsp_clks",
202 /* PRM EXTERNAL CLOCK OUTPUT */
204 static struct clk sys_clkout1
= {
205 .name
= "sys_clkout1",
206 .ops
= &clkops_omap2_dflt
,
207 .parent
= &osc_sys_ck
,
208 .enable_reg
= OMAP3430_PRM_CLKOUT_CTRL
,
209 .enable_bit
= OMAP3430_CLKOUT_EN_SHIFT
,
210 .recalc
= &followparent_recalc
,
217 static const struct clksel_rate div16_dpll_rates
[] = {
218 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
219 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
220 { .div
= 3, .val
= 3, .flags
= RATE_IN_3XXX
},
221 { .div
= 4, .val
= 4, .flags
= RATE_IN_3XXX
},
222 { .div
= 5, .val
= 5, .flags
= RATE_IN_3XXX
},
223 { .div
= 6, .val
= 6, .flags
= RATE_IN_3XXX
},
224 { .div
= 7, .val
= 7, .flags
= RATE_IN_3XXX
},
225 { .div
= 8, .val
= 8, .flags
= RATE_IN_3XXX
},
226 { .div
= 9, .val
= 9, .flags
= RATE_IN_3XXX
},
227 { .div
= 10, .val
= 10, .flags
= RATE_IN_3XXX
},
228 { .div
= 11, .val
= 11, .flags
= RATE_IN_3XXX
},
229 { .div
= 12, .val
= 12, .flags
= RATE_IN_3XXX
},
230 { .div
= 13, .val
= 13, .flags
= RATE_IN_3XXX
},
231 { .div
= 14, .val
= 14, .flags
= RATE_IN_3XXX
},
232 { .div
= 15, .val
= 15, .flags
= RATE_IN_3XXX
},
233 { .div
= 16, .val
= 16, .flags
= RATE_IN_3XXX
},
237 static const struct clksel_rate dpll4_rates
[] = {
238 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
239 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
240 { .div
= 3, .val
= 3, .flags
= RATE_IN_3XXX
},
241 { .div
= 4, .val
= 4, .flags
= RATE_IN_3XXX
},
242 { .div
= 5, .val
= 5, .flags
= RATE_IN_3XXX
},
243 { .div
= 6, .val
= 6, .flags
= RATE_IN_3XXX
},
244 { .div
= 7, .val
= 7, .flags
= RATE_IN_3XXX
},
245 { .div
= 8, .val
= 8, .flags
= RATE_IN_3XXX
},
246 { .div
= 9, .val
= 9, .flags
= RATE_IN_3XXX
},
247 { .div
= 10, .val
= 10, .flags
= RATE_IN_3XXX
},
248 { .div
= 11, .val
= 11, .flags
= RATE_IN_3XXX
},
249 { .div
= 12, .val
= 12, .flags
= RATE_IN_3XXX
},
250 { .div
= 13, .val
= 13, .flags
= RATE_IN_3XXX
},
251 { .div
= 14, .val
= 14, .flags
= RATE_IN_3XXX
},
252 { .div
= 15, .val
= 15, .flags
= RATE_IN_3XXX
},
253 { .div
= 16, .val
= 16, .flags
= RATE_IN_3XXX
},
254 { .div
= 17, .val
= 17, .flags
= RATE_IN_36XX
},
255 { .div
= 18, .val
= 18, .flags
= RATE_IN_36XX
},
256 { .div
= 19, .val
= 19, .flags
= RATE_IN_36XX
},
257 { .div
= 20, .val
= 20, .flags
= RATE_IN_36XX
},
258 { .div
= 21, .val
= 21, .flags
= RATE_IN_36XX
},
259 { .div
= 22, .val
= 22, .flags
= RATE_IN_36XX
},
260 { .div
= 23, .val
= 23, .flags
= RATE_IN_36XX
},
261 { .div
= 24, .val
= 24, .flags
= RATE_IN_36XX
},
262 { .div
= 25, .val
= 25, .flags
= RATE_IN_36XX
},
263 { .div
= 26, .val
= 26, .flags
= RATE_IN_36XX
},
264 { .div
= 27, .val
= 27, .flags
= RATE_IN_36XX
},
265 { .div
= 28, .val
= 28, .flags
= RATE_IN_36XX
},
266 { .div
= 29, .val
= 29, .flags
= RATE_IN_36XX
},
267 { .div
= 30, .val
= 30, .flags
= RATE_IN_36XX
},
268 { .div
= 31, .val
= 31, .flags
= RATE_IN_36XX
},
269 { .div
= 32, .val
= 32, .flags
= RATE_IN_36XX
},
274 /* MPU clock source */
276 static struct dpll_data dpll1_dd
= {
277 .mult_div1_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
278 .mult_mask
= OMAP3430_MPU_DPLL_MULT_MASK
,
279 .div1_mask
= OMAP3430_MPU_DPLL_DIV_MASK
,
280 .clk_bypass
= &dpll1_fck
,
282 .freqsel_mask
= OMAP3430_MPU_DPLL_FREQSEL_MASK
,
283 .control_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKEN_PLL
),
284 .enable_mask
= OMAP3430_EN_MPU_DPLL_MASK
,
285 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
286 .auto_recal_bit
= OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT
,
287 .recal_en_bit
= OMAP3430_MPU_DPLL_RECAL_EN_SHIFT
,
288 .recal_st_bit
= OMAP3430_MPU_DPLL_ST_SHIFT
,
289 .autoidle_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_AUTOIDLE_PLL
),
290 .autoidle_mask
= OMAP3430_AUTO_MPU_DPLL_MASK
,
291 .idlest_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_IDLEST_PLL
),
292 .idlest_mask
= OMAP3430_ST_MPU_CLK_MASK
,
293 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
295 .max_divider
= OMAP3_MAX_DPLL_DIV
,
298 static struct clk dpll1_ck
= {
300 .ops
= &clkops_omap3_noncore_dpll_ops
,
302 .dpll_data
= &dpll1_dd
,
303 .round_rate
= &omap2_dpll_round_rate
,
304 .set_rate
= &omap3_noncore_dpll_set_rate
,
305 .clkdm_name
= "dpll1_clkdm",
306 .recalc
= &omap3_dpll_recalc
,
310 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
311 * DPLL isn't bypassed.
313 static struct clk dpll1_x2_ck
= {
314 .name
= "dpll1_x2_ck",
317 .clkdm_name
= "dpll1_clkdm",
318 .recalc
= &omap3_clkoutx2_recalc
,
321 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
322 static const struct clksel div16_dpll1_x2m2_clksel
[] = {
323 { .parent
= &dpll1_x2_ck
, .rates
= div16_dpll_rates
},
328 * Does not exist in the TRM - needed to separate the M2 divider from
329 * bypass selection in mpu_ck
331 static struct clk dpll1_x2m2_ck
= {
332 .name
= "dpll1_x2m2_ck",
334 .parent
= &dpll1_x2_ck
,
335 .init
= &omap2_init_clksel_parent
,
336 .clksel_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKSEL2_PLL
),
337 .clksel_mask
= OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK
,
338 .clksel
= div16_dpll1_x2m2_clksel
,
339 .clkdm_name
= "dpll1_clkdm",
340 .recalc
= &omap2_clksel_recalc
,
344 /* IVA2 clock source */
347 static struct dpll_data dpll2_dd
= {
348 .mult_div1_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
349 .mult_mask
= OMAP3430_IVA2_DPLL_MULT_MASK
,
350 .div1_mask
= OMAP3430_IVA2_DPLL_DIV_MASK
,
351 .clk_bypass
= &dpll2_fck
,
353 .freqsel_mask
= OMAP3430_IVA2_DPLL_FREQSEL_MASK
,
354 .control_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKEN_PLL
),
355 .enable_mask
= OMAP3430_EN_IVA2_DPLL_MASK
,
356 .modes
= (1 << DPLL_LOW_POWER_STOP
) | (1 << DPLL_LOCKED
) |
357 (1 << DPLL_LOW_POWER_BYPASS
),
358 .auto_recal_bit
= OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT
,
359 .recal_en_bit
= OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT
,
360 .recal_st_bit
= OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT
,
361 .autoidle_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_AUTOIDLE_PLL
),
362 .autoidle_mask
= OMAP3430_AUTO_IVA2_DPLL_MASK
,
363 .idlest_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_IDLEST_PLL
),
364 .idlest_mask
= OMAP3430_ST_IVA2_CLK_MASK
,
365 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
367 .max_divider
= OMAP3_MAX_DPLL_DIV
,
370 static struct clk dpll2_ck
= {
372 .ops
= &clkops_omap3_noncore_dpll_ops
,
374 .dpll_data
= &dpll2_dd
,
375 .round_rate
= &omap2_dpll_round_rate
,
376 .set_rate
= &omap3_noncore_dpll_set_rate
,
377 .clkdm_name
= "dpll2_clkdm",
378 .recalc
= &omap3_dpll_recalc
,
381 static const struct clksel div16_dpll2_m2x2_clksel
[] = {
382 { .parent
= &dpll2_ck
, .rates
= div16_dpll_rates
},
387 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
388 * or CLKOUTX2. CLKOUT seems most plausible.
390 static struct clk dpll2_m2_ck
= {
391 .name
= "dpll2_m2_ck",
394 .init
= &omap2_init_clksel_parent
,
395 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
,
396 OMAP3430_CM_CLKSEL2_PLL
),
397 .clksel_mask
= OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK
,
398 .clksel
= div16_dpll2_m2x2_clksel
,
399 .clkdm_name
= "dpll2_clkdm",
400 .recalc
= &omap2_clksel_recalc
,
405 * Source clock for all interfaces and for some device fclks
406 * REVISIT: Also supports fast relock bypass - not included below
408 static struct dpll_data dpll3_dd
= {
409 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
410 .mult_mask
= OMAP3430_CORE_DPLL_MULT_MASK
,
411 .div1_mask
= OMAP3430_CORE_DPLL_DIV_MASK
,
412 .clk_bypass
= &sys_ck
,
414 .freqsel_mask
= OMAP3430_CORE_DPLL_FREQSEL_MASK
,
415 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
416 .enable_mask
= OMAP3430_EN_CORE_DPLL_MASK
,
417 .auto_recal_bit
= OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT
,
418 .recal_en_bit
= OMAP3430_CORE_DPLL_RECAL_EN_SHIFT
,
419 .recal_st_bit
= OMAP3430_CORE_DPLL_ST_SHIFT
,
420 .autoidle_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_AUTOIDLE
),
421 .autoidle_mask
= OMAP3430_AUTO_CORE_DPLL_MASK
,
422 .idlest_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_IDLEST
),
423 .idlest_mask
= OMAP3430_ST_CORE_CLK_MASK
,
424 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
426 .max_divider
= OMAP3_MAX_DPLL_DIV
,
429 static struct clk dpll3_ck
= {
431 .ops
= &clkops_omap3_core_dpll_ops
,
433 .dpll_data
= &dpll3_dd
,
434 .round_rate
= &omap2_dpll_round_rate
,
435 .clkdm_name
= "dpll3_clkdm",
436 .recalc
= &omap3_dpll_recalc
,
440 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
441 * DPLL isn't bypassed
443 static struct clk dpll3_x2_ck
= {
444 .name
= "dpll3_x2_ck",
447 .clkdm_name
= "dpll3_clkdm",
448 .recalc
= &omap3_clkoutx2_recalc
,
451 static const struct clksel_rate div31_dpll3_rates
[] = {
452 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
453 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
454 { .div
= 3, .val
= 3, .flags
= RATE_IN_3430ES2PLUS_36XX
},
455 { .div
= 4, .val
= 4, .flags
= RATE_IN_3430ES2PLUS_36XX
},
456 { .div
= 5, .val
= 5, .flags
= RATE_IN_3430ES2PLUS_36XX
},
457 { .div
= 6, .val
= 6, .flags
= RATE_IN_3430ES2PLUS_36XX
},
458 { .div
= 7, .val
= 7, .flags
= RATE_IN_3430ES2PLUS_36XX
},
459 { .div
= 8, .val
= 8, .flags
= RATE_IN_3430ES2PLUS_36XX
},
460 { .div
= 9, .val
= 9, .flags
= RATE_IN_3430ES2PLUS_36XX
},
461 { .div
= 10, .val
= 10, .flags
= RATE_IN_3430ES2PLUS_36XX
},
462 { .div
= 11, .val
= 11, .flags
= RATE_IN_3430ES2PLUS_36XX
},
463 { .div
= 12, .val
= 12, .flags
= RATE_IN_3430ES2PLUS_36XX
},
464 { .div
= 13, .val
= 13, .flags
= RATE_IN_3430ES2PLUS_36XX
},
465 { .div
= 14, .val
= 14, .flags
= RATE_IN_3430ES2PLUS_36XX
},
466 { .div
= 15, .val
= 15, .flags
= RATE_IN_3430ES2PLUS_36XX
},
467 { .div
= 16, .val
= 16, .flags
= RATE_IN_3430ES2PLUS_36XX
},
468 { .div
= 17, .val
= 17, .flags
= RATE_IN_3430ES2PLUS_36XX
},
469 { .div
= 18, .val
= 18, .flags
= RATE_IN_3430ES2PLUS_36XX
},
470 { .div
= 19, .val
= 19, .flags
= RATE_IN_3430ES2PLUS_36XX
},
471 { .div
= 20, .val
= 20, .flags
= RATE_IN_3430ES2PLUS_36XX
},
472 { .div
= 21, .val
= 21, .flags
= RATE_IN_3430ES2PLUS_36XX
},
473 { .div
= 22, .val
= 22, .flags
= RATE_IN_3430ES2PLUS_36XX
},
474 { .div
= 23, .val
= 23, .flags
= RATE_IN_3430ES2PLUS_36XX
},
475 { .div
= 24, .val
= 24, .flags
= RATE_IN_3430ES2PLUS_36XX
},
476 { .div
= 25, .val
= 25, .flags
= RATE_IN_3430ES2PLUS_36XX
},
477 { .div
= 26, .val
= 26, .flags
= RATE_IN_3430ES2PLUS_36XX
},
478 { .div
= 27, .val
= 27, .flags
= RATE_IN_3430ES2PLUS_36XX
},
479 { .div
= 28, .val
= 28, .flags
= RATE_IN_3430ES2PLUS_36XX
},
480 { .div
= 29, .val
= 29, .flags
= RATE_IN_3430ES2PLUS_36XX
},
481 { .div
= 30, .val
= 30, .flags
= RATE_IN_3430ES2PLUS_36XX
},
482 { .div
= 31, .val
= 31, .flags
= RATE_IN_3430ES2PLUS_36XX
},
486 static const struct clksel div31_dpll3m2_clksel
[] = {
487 { .parent
= &dpll3_ck
, .rates
= div31_dpll3_rates
},
491 /* DPLL3 output M2 - primary control point for CORE speed */
492 static struct clk dpll3_m2_ck
= {
493 .name
= "dpll3_m2_ck",
496 .init
= &omap2_init_clksel_parent
,
497 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
498 .clksel_mask
= OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK
,
499 .clksel
= div31_dpll3m2_clksel
,
500 .clkdm_name
= "dpll3_clkdm",
501 .round_rate
= &omap2_clksel_round_rate
,
502 .set_rate
= &omap3_core_dpll_m2_set_rate
,
503 .recalc
= &omap2_clksel_recalc
,
506 static struct clk core_ck
= {
509 .parent
= &dpll3_m2_ck
,
510 .recalc
= &followparent_recalc
,
513 static struct clk dpll3_m2x2_ck
= {
514 .name
= "dpll3_m2x2_ck",
516 .parent
= &dpll3_m2_ck
,
517 .clkdm_name
= "dpll3_clkdm",
518 .recalc
= &omap3_clkoutx2_recalc
,
521 /* The PWRDN bit is apparently only available on 3430ES2 and above */
522 static const struct clksel div16_dpll3_clksel
[] = {
523 { .parent
= &dpll3_ck
, .rates
= div16_dpll_rates
},
527 /* This virtual clock is the source for dpll3_m3x2_ck */
528 static struct clk dpll3_m3_ck
= {
529 .name
= "dpll3_m3_ck",
532 .init
= &omap2_init_clksel_parent
,
533 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
534 .clksel_mask
= OMAP3430_DIV_DPLL3_MASK
,
535 .clksel
= div16_dpll3_clksel
,
536 .clkdm_name
= "dpll3_clkdm",
537 .recalc
= &omap2_clksel_recalc
,
540 /* The PWRDN bit is apparently only available on 3430ES2 and above */
541 static struct clk dpll3_m3x2_ck
= {
542 .name
= "dpll3_m3x2_ck",
543 .ops
= &clkops_omap2_dflt_wait
,
544 .parent
= &dpll3_m3_ck
,
545 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
546 .enable_bit
= OMAP3430_PWRDN_EMU_CORE_SHIFT
,
547 .flags
= INVERT_ENABLE
,
548 .clkdm_name
= "dpll3_clkdm",
549 .recalc
= &omap3_clkoutx2_recalc
,
552 static struct clk emu_core_alwon_ck
= {
553 .name
= "emu_core_alwon_ck",
555 .parent
= &dpll3_m3x2_ck
,
556 .clkdm_name
= "dpll3_clkdm",
557 .recalc
= &followparent_recalc
,
561 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
563 static struct dpll_data dpll4_dd
;
565 static struct dpll_data dpll4_dd_34xx __initdata
= {
566 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL2
),
567 .mult_mask
= OMAP3430_PERIPH_DPLL_MULT_MASK
,
568 .div1_mask
= OMAP3430_PERIPH_DPLL_DIV_MASK
,
569 .clk_bypass
= &sys_ck
,
571 .freqsel_mask
= OMAP3430_PERIPH_DPLL_FREQSEL_MASK
,
572 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
573 .enable_mask
= OMAP3430_EN_PERIPH_DPLL_MASK
,
574 .modes
= (1 << DPLL_LOW_POWER_STOP
) | (1 << DPLL_LOCKED
),
575 .auto_recal_bit
= OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT
,
576 .recal_en_bit
= OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT
,
577 .recal_st_bit
= OMAP3430_PERIPH_DPLL_ST_SHIFT
,
578 .autoidle_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_AUTOIDLE
),
579 .autoidle_mask
= OMAP3430_AUTO_PERIPH_DPLL_MASK
,
580 .idlest_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_IDLEST
),
581 .idlest_mask
= OMAP3430_ST_PERIPH_CLK_MASK
,
582 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
584 .max_divider
= OMAP3_MAX_DPLL_DIV
,
587 static struct dpll_data dpll4_dd_3630 __initdata
= {
588 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL2
),
589 .mult_mask
= OMAP3630_PERIPH_DPLL_MULT_MASK
,
590 .div1_mask
= OMAP3430_PERIPH_DPLL_DIV_MASK
,
591 .clk_bypass
= &sys_ck
,
593 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
594 .enable_mask
= OMAP3430_EN_PERIPH_DPLL_MASK
,
595 .modes
= (1 << DPLL_LOW_POWER_STOP
) | (1 << DPLL_LOCKED
),
596 .auto_recal_bit
= OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT
,
597 .recal_en_bit
= OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT
,
598 .recal_st_bit
= OMAP3430_PERIPH_DPLL_ST_SHIFT
,
599 .autoidle_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_AUTOIDLE
),
600 .autoidle_mask
= OMAP3430_AUTO_PERIPH_DPLL_MASK
,
601 .idlest_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_IDLEST
),
602 .idlest_mask
= OMAP3430_ST_PERIPH_CLK_MASK
,
603 .dco_mask
= OMAP3630_PERIPH_DPLL_DCO_SEL_MASK
,
604 .sddiv_mask
= OMAP3630_PERIPH_DPLL_SD_DIV_MASK
,
605 .max_multiplier
= OMAP3630_MAX_JTYPE_DPLL_MULT
,
607 .max_divider
= OMAP3_MAX_DPLL_DIV
,
611 static struct clk dpll4_ck
= {
613 .ops
= &clkops_omap3_noncore_dpll_ops
,
615 .dpll_data
= &dpll4_dd
,
616 .round_rate
= &omap2_dpll_round_rate
,
617 .set_rate
= &omap3_dpll4_set_rate
,
618 .clkdm_name
= "dpll4_clkdm",
619 .recalc
= &omap3_dpll_recalc
,
623 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
624 * DPLL isn't bypassed --
625 * XXX does this serve any downstream clocks?
627 static struct clk dpll4_x2_ck
= {
628 .name
= "dpll4_x2_ck",
631 .clkdm_name
= "dpll4_clkdm",
632 .recalc
= &omap3_clkoutx2_recalc
,
635 static const struct clksel dpll4_clksel
[] = {
636 { .parent
= &dpll4_ck
, .rates
= dpll4_rates
},
640 /* This virtual clock is the source for dpll4_m2x2_ck */
641 static struct clk dpll4_m2_ck
= {
642 .name
= "dpll4_m2_ck",
645 .init
= &omap2_init_clksel_parent
,
646 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430_CM_CLKSEL3
),
647 .clksel_mask
= OMAP3630_DIV_96M_MASK
,
648 .clksel
= dpll4_clksel
,
649 .clkdm_name
= "dpll4_clkdm",
650 .recalc
= &omap2_clksel_recalc
,
653 /* The PWRDN bit is apparently only available on 3430ES2 and above */
654 static struct clk dpll4_m2x2_ck
= {
655 .name
= "dpll4_m2x2_ck",
656 .ops
= &clkops_omap2_dflt_wait
,
657 .parent
= &dpll4_m2_ck
,
658 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
659 .enable_bit
= OMAP3430_PWRDN_96M_SHIFT
,
660 .flags
= INVERT_ENABLE
,
661 .clkdm_name
= "dpll4_clkdm",
662 .recalc
= &omap3_clkoutx2_recalc
,
666 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
667 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
668 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
672 /* Adding 192MHz Clock node needed by SGX */
673 static struct clk omap_192m_alwon_fck
= {
674 .name
= "omap_192m_alwon_fck",
676 .parent
= &dpll4_m2x2_ck
,
677 .recalc
= &followparent_recalc
,
680 static const struct clksel_rate omap_96m_alwon_fck_rates
[] = {
681 { .div
= 1, .val
= 1, .flags
= RATE_IN_36XX
},
682 { .div
= 2, .val
= 2, .flags
= RATE_IN_36XX
},
686 static const struct clksel omap_96m_alwon_fck_clksel
[] = {
687 { .parent
= &omap_192m_alwon_fck
, .rates
= omap_96m_alwon_fck_rates
},
691 static const struct clksel_rate omap_96m_dpll_rates
[] = {
692 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
696 static const struct clksel_rate omap_96m_sys_rates
[] = {
697 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
701 static struct clk omap_96m_alwon_fck
= {
702 .name
= "omap_96m_alwon_fck",
704 .parent
= &dpll4_m2x2_ck
,
705 .recalc
= &followparent_recalc
,
708 static struct clk omap_96m_alwon_fck_3630
= {
709 .name
= "omap_96m_alwon_fck",
710 .parent
= &omap_192m_alwon_fck
,
711 .init
= &omap2_init_clksel_parent
,
713 .recalc
= &omap2_clksel_recalc
,
714 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
715 .clksel_mask
= OMAP3630_CLKSEL_96M_MASK
,
716 .clksel
= omap_96m_alwon_fck_clksel
719 static struct clk cm_96m_fck
= {
720 .name
= "cm_96m_fck",
722 .parent
= &omap_96m_alwon_fck
,
723 .recalc
= &followparent_recalc
,
726 static const struct clksel omap_96m_fck_clksel
[] = {
727 { .parent
= &cm_96m_fck
, .rates
= omap_96m_dpll_rates
},
728 { .parent
= &sys_ck
, .rates
= omap_96m_sys_rates
},
732 static struct clk omap_96m_fck
= {
733 .name
= "omap_96m_fck",
736 .init
= &omap2_init_clksel_parent
,
737 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
738 .clksel_mask
= OMAP3430_SOURCE_96M_MASK
,
739 .clksel
= omap_96m_fck_clksel
,
740 .recalc
= &omap2_clksel_recalc
,
743 /* This virtual clock is the source for dpll4_m3x2_ck */
744 static struct clk dpll4_m3_ck
= {
745 .name
= "dpll4_m3_ck",
748 .init
= &omap2_init_clksel_parent
,
749 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_CLKSEL
),
750 .clksel_mask
= OMAP3630_CLKSEL_TV_MASK
,
751 .clksel
= dpll4_clksel
,
752 .clkdm_name
= "dpll4_clkdm",
753 .recalc
= &omap2_clksel_recalc
,
756 /* The PWRDN bit is apparently only available on 3430ES2 and above */
757 static struct clk dpll4_m3x2_ck
= {
758 .name
= "dpll4_m3x2_ck",
759 .ops
= &clkops_omap2_dflt_wait
,
760 .parent
= &dpll4_m3_ck
,
761 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
762 .enable_bit
= OMAP3430_PWRDN_TV_SHIFT
,
763 .flags
= INVERT_ENABLE
,
764 .clkdm_name
= "dpll4_clkdm",
765 .recalc
= &omap3_clkoutx2_recalc
,
768 static const struct clksel_rate omap_54m_d4m3x2_rates
[] = {
769 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
773 static const struct clksel_rate omap_54m_alt_rates
[] = {
774 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
778 static const struct clksel omap_54m_clksel
[] = {
779 { .parent
= &dpll4_m3x2_ck
, .rates
= omap_54m_d4m3x2_rates
},
780 { .parent
= &sys_altclk
, .rates
= omap_54m_alt_rates
},
784 static struct clk omap_54m_fck
= {
785 .name
= "omap_54m_fck",
787 .init
= &omap2_init_clksel_parent
,
788 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
789 .clksel_mask
= OMAP3430_SOURCE_54M_MASK
,
790 .clksel
= omap_54m_clksel
,
791 .recalc
= &omap2_clksel_recalc
,
794 static const struct clksel_rate omap_48m_cm96m_rates
[] = {
795 { .div
= 2, .val
= 0, .flags
= RATE_IN_3XXX
},
799 static const struct clksel_rate omap_48m_alt_rates
[] = {
800 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
804 static const struct clksel omap_48m_clksel
[] = {
805 { .parent
= &cm_96m_fck
, .rates
= omap_48m_cm96m_rates
},
806 { .parent
= &sys_altclk
, .rates
= omap_48m_alt_rates
},
810 static struct clk omap_48m_fck
= {
811 .name
= "omap_48m_fck",
813 .init
= &omap2_init_clksel_parent
,
814 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
815 .clksel_mask
= OMAP3430_SOURCE_48M_MASK
,
816 .clksel
= omap_48m_clksel
,
817 .recalc
= &omap2_clksel_recalc
,
820 static struct clk omap_12m_fck
= {
821 .name
= "omap_12m_fck",
823 .parent
= &omap_48m_fck
,
825 .recalc
= &omap_fixed_divisor_recalc
,
828 /* This virtual clock is the source for dpll4_m4x2_ck */
829 static struct clk dpll4_m4_ck
= {
830 .name
= "dpll4_m4_ck",
833 .init
= &omap2_init_clksel_parent
,
834 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_CLKSEL
),
835 .clksel_mask
= OMAP3630_CLKSEL_DSS1_MASK
,
836 .clksel
= dpll4_clksel
,
837 .clkdm_name
= "dpll4_clkdm",
838 .recalc
= &omap2_clksel_recalc
,
839 .set_rate
= &omap2_clksel_set_rate
,
840 .round_rate
= &omap2_clksel_round_rate
,
843 /* The PWRDN bit is apparently only available on 3430ES2 and above */
844 static struct clk dpll4_m4x2_ck
= {
845 .name
= "dpll4_m4x2_ck",
846 .ops
= &clkops_omap2_dflt_wait
,
847 .parent
= &dpll4_m4_ck
,
848 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
849 .enable_bit
= OMAP3430_PWRDN_DSS1_SHIFT
,
850 .flags
= INVERT_ENABLE
,
851 .clkdm_name
= "dpll4_clkdm",
852 .recalc
= &omap3_clkoutx2_recalc
,
855 /* This virtual clock is the source for dpll4_m5x2_ck */
856 static struct clk dpll4_m5_ck
= {
857 .name
= "dpll4_m5_ck",
860 .init
= &omap2_init_clksel_parent
,
861 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_CLKSEL
),
862 .clksel_mask
= OMAP3630_CLKSEL_CAM_MASK
,
863 .clksel
= dpll4_clksel
,
864 .clkdm_name
= "dpll4_clkdm",
865 .set_rate
= &omap2_clksel_set_rate
,
866 .round_rate
= &omap2_clksel_round_rate
,
867 .recalc
= &omap2_clksel_recalc
,
870 /* The PWRDN bit is apparently only available on 3430ES2 and above */
871 static struct clk dpll4_m5x2_ck
= {
872 .name
= "dpll4_m5x2_ck",
873 .ops
= &clkops_omap2_dflt_wait
,
874 .parent
= &dpll4_m5_ck
,
875 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
876 .enable_bit
= OMAP3430_PWRDN_CAM_SHIFT
,
877 .flags
= INVERT_ENABLE
,
878 .clkdm_name
= "dpll4_clkdm",
879 .recalc
= &omap3_clkoutx2_recalc
,
882 /* This virtual clock is the source for dpll4_m6x2_ck */
883 static struct clk dpll4_m6_ck
= {
884 .name
= "dpll4_m6_ck",
887 .init
= &omap2_init_clksel_parent
,
888 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
889 .clksel_mask
= OMAP3630_DIV_DPLL4_MASK
,
890 .clksel
= dpll4_clksel
,
891 .clkdm_name
= "dpll4_clkdm",
892 .recalc
= &omap2_clksel_recalc
,
895 /* The PWRDN bit is apparently only available on 3430ES2 and above */
896 static struct clk dpll4_m6x2_ck
= {
897 .name
= "dpll4_m6x2_ck",
898 .ops
= &clkops_omap2_dflt_wait
,
899 .parent
= &dpll4_m6_ck
,
900 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
901 .enable_bit
= OMAP3430_PWRDN_EMU_PERIPH_SHIFT
,
902 .flags
= INVERT_ENABLE
,
903 .clkdm_name
= "dpll4_clkdm",
904 .recalc
= &omap3_clkoutx2_recalc
,
907 static struct clk emu_per_alwon_ck
= {
908 .name
= "emu_per_alwon_ck",
910 .parent
= &dpll4_m6x2_ck
,
911 .clkdm_name
= "dpll4_clkdm",
912 .recalc
= &followparent_recalc
,
916 /* Supplies 120MHz clock, USIM source clock */
919 static struct dpll_data dpll5_dd
= {
920 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_CLKSEL4
),
921 .mult_mask
= OMAP3430ES2_PERIPH2_DPLL_MULT_MASK
,
922 .div1_mask
= OMAP3430ES2_PERIPH2_DPLL_DIV_MASK
,
923 .clk_bypass
= &sys_ck
,
925 .freqsel_mask
= OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK
,
926 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_CLKEN2
),
927 .enable_mask
= OMAP3430ES2_EN_PERIPH2_DPLL_MASK
,
928 .modes
= (1 << DPLL_LOW_POWER_STOP
) | (1 << DPLL_LOCKED
),
929 .auto_recal_bit
= OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT
,
930 .recal_en_bit
= OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT
,
931 .recal_st_bit
= OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT
,
932 .autoidle_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_AUTOIDLE2_PLL
),
933 .autoidle_mask
= OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK
,
934 .idlest_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_IDLEST2
),
935 .idlest_mask
= OMAP3430ES2_ST_PERIPH2_CLK_MASK
,
936 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
938 .max_divider
= OMAP3_MAX_DPLL_DIV
,
941 static struct clk dpll5_ck
= {
943 .ops
= &clkops_omap3_noncore_dpll_ops
,
945 .dpll_data
= &dpll5_dd
,
946 .round_rate
= &omap2_dpll_round_rate
,
947 .set_rate
= &omap3_noncore_dpll_set_rate
,
948 .clkdm_name
= "dpll5_clkdm",
949 .recalc
= &omap3_dpll_recalc
,
952 static const struct clksel div16_dpll5_clksel
[] = {
953 { .parent
= &dpll5_ck
, .rates
= div16_dpll_rates
},
957 static struct clk dpll5_m2_ck
= {
958 .name
= "dpll5_m2_ck",
961 .init
= &omap2_init_clksel_parent
,
962 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_CLKSEL5
),
963 .clksel_mask
= OMAP3430ES2_DIV_120M_MASK
,
964 .clksel
= div16_dpll5_clksel
,
965 .clkdm_name
= "dpll5_clkdm",
966 .recalc
= &omap2_clksel_recalc
,
969 /* CM EXTERNAL CLOCK OUTPUTS */
971 static const struct clksel_rate clkout2_src_core_rates
[] = {
972 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
976 static const struct clksel_rate clkout2_src_sys_rates
[] = {
977 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
981 static const struct clksel_rate clkout2_src_96m_rates
[] = {
982 { .div
= 1, .val
= 2, .flags
= RATE_IN_3XXX
},
986 static const struct clksel_rate clkout2_src_54m_rates
[] = {
987 { .div
= 1, .val
= 3, .flags
= RATE_IN_3XXX
},
991 static const struct clksel clkout2_src_clksel
[] = {
992 { .parent
= &core_ck
, .rates
= clkout2_src_core_rates
},
993 { .parent
= &sys_ck
, .rates
= clkout2_src_sys_rates
},
994 { .parent
= &cm_96m_fck
, .rates
= clkout2_src_96m_rates
},
995 { .parent
= &omap_54m_fck
, .rates
= clkout2_src_54m_rates
},
999 static struct clk clkout2_src_ck
= {
1000 .name
= "clkout2_src_ck",
1001 .ops
= &clkops_omap2_dflt
,
1002 .init
= &omap2_init_clksel_parent
,
1003 .enable_reg
= OMAP3430_CM_CLKOUT_CTRL
,
1004 .enable_bit
= OMAP3430_CLKOUT2_EN_SHIFT
,
1005 .clksel_reg
= OMAP3430_CM_CLKOUT_CTRL
,
1006 .clksel_mask
= OMAP3430_CLKOUT2SOURCE_MASK
,
1007 .clksel
= clkout2_src_clksel
,
1008 .clkdm_name
= "core_clkdm",
1009 .recalc
= &omap2_clksel_recalc
,
1012 static const struct clksel_rate sys_clkout2_rates
[] = {
1013 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
1014 { .div
= 2, .val
= 1, .flags
= RATE_IN_3XXX
},
1015 { .div
= 4, .val
= 2, .flags
= RATE_IN_3XXX
},
1016 { .div
= 8, .val
= 3, .flags
= RATE_IN_3XXX
},
1017 { .div
= 16, .val
= 4, .flags
= RATE_IN_3XXX
},
1021 static const struct clksel sys_clkout2_clksel
[] = {
1022 { .parent
= &clkout2_src_ck
, .rates
= sys_clkout2_rates
},
1026 static struct clk sys_clkout2
= {
1027 .name
= "sys_clkout2",
1028 .ops
= &clkops_null
,
1029 .init
= &omap2_init_clksel_parent
,
1030 .clksel_reg
= OMAP3430_CM_CLKOUT_CTRL
,
1031 .clksel_mask
= OMAP3430_CLKOUT2_DIV_MASK
,
1032 .clksel
= sys_clkout2_clksel
,
1033 .recalc
= &omap2_clksel_recalc
,
1034 .round_rate
= &omap2_clksel_round_rate
,
1035 .set_rate
= &omap2_clksel_set_rate
1038 /* CM OUTPUT CLOCKS */
1040 static struct clk corex2_fck
= {
1041 .name
= "corex2_fck",
1042 .ops
= &clkops_null
,
1043 .parent
= &dpll3_m2x2_ck
,
1044 .recalc
= &followparent_recalc
,
1047 /* DPLL power domain clock controls */
1049 static const struct clksel_rate div4_rates
[] = {
1050 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
1051 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
1052 { .div
= 4, .val
= 4, .flags
= RATE_IN_3XXX
},
1056 static const struct clksel div4_core_clksel
[] = {
1057 { .parent
= &core_ck
, .rates
= div4_rates
},
1062 * REVISIT: Are these in DPLL power domain or CM power domain? docs
1063 * may be inconsistent here?
1065 static struct clk dpll1_fck
= {
1066 .name
= "dpll1_fck",
1067 .ops
= &clkops_null
,
1069 .init
= &omap2_init_clksel_parent
,
1070 .clksel_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
1071 .clksel_mask
= OMAP3430_MPU_CLK_SRC_MASK
,
1072 .clksel
= div4_core_clksel
,
1073 .recalc
= &omap2_clksel_recalc
,
1076 static struct clk mpu_ck
= {
1078 .ops
= &clkops_null
,
1079 .parent
= &dpll1_x2m2_ck
,
1080 .clkdm_name
= "mpu_clkdm",
1081 .recalc
= &followparent_recalc
,
1084 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1085 static const struct clksel_rate arm_fck_rates
[] = {
1086 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
1087 { .div
= 2, .val
= 1, .flags
= RATE_IN_3XXX
},
1091 static const struct clksel arm_fck_clksel
[] = {
1092 { .parent
= &mpu_ck
, .rates
= arm_fck_rates
},
1096 static struct clk arm_fck
= {
1098 .ops
= &clkops_null
,
1100 .init
= &omap2_init_clksel_parent
,
1101 .clksel_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_IDLEST_PLL
),
1102 .clksel_mask
= OMAP3430_ST_MPU_CLK_MASK
,
1103 .clksel
= arm_fck_clksel
,
1104 .clkdm_name
= "mpu_clkdm",
1105 .recalc
= &omap2_clksel_recalc
,
1108 /* XXX What about neon_clkdm ? */
1111 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1112 * although it is referenced - so this is a guess
1114 static struct clk emu_mpu_alwon_ck
= {
1115 .name
= "emu_mpu_alwon_ck",
1116 .ops
= &clkops_null
,
1118 .recalc
= &followparent_recalc
,
1121 static struct clk dpll2_fck
= {
1122 .name
= "dpll2_fck",
1123 .ops
= &clkops_null
,
1125 .init
= &omap2_init_clksel_parent
,
1126 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
1127 .clksel_mask
= OMAP3430_IVA2_CLK_SRC_MASK
,
1128 .clksel
= div4_core_clksel
,
1129 .recalc
= &omap2_clksel_recalc
,
1132 static struct clk iva2_ck
= {
1134 .ops
= &clkops_omap2_dflt_wait
,
1135 .parent
= &dpll2_m2_ck
,
1136 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, CM_FCLKEN
),
1137 .enable_bit
= OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT
,
1138 .clkdm_name
= "iva2_clkdm",
1139 .recalc
= &followparent_recalc
,
1142 /* Common interface clocks */
1144 static const struct clksel div2_core_clksel
[] = {
1145 { .parent
= &core_ck
, .rates
= div2_rates
},
1149 static struct clk l3_ick
= {
1151 .ops
= &clkops_null
,
1153 .init
= &omap2_init_clksel_parent
,
1154 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1155 .clksel_mask
= OMAP3430_CLKSEL_L3_MASK
,
1156 .clksel
= div2_core_clksel
,
1157 .clkdm_name
= "core_l3_clkdm",
1158 .recalc
= &omap2_clksel_recalc
,
1161 static const struct clksel div2_l3_clksel
[] = {
1162 { .parent
= &l3_ick
, .rates
= div2_rates
},
1166 static struct clk l4_ick
= {
1168 .ops
= &clkops_null
,
1170 .init
= &omap2_init_clksel_parent
,
1171 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1172 .clksel_mask
= OMAP3430_CLKSEL_L4_MASK
,
1173 .clksel
= div2_l3_clksel
,
1174 .clkdm_name
= "core_l4_clkdm",
1175 .recalc
= &omap2_clksel_recalc
,
1179 static const struct clksel div2_l4_clksel
[] = {
1180 { .parent
= &l4_ick
, .rates
= div2_rates
},
1184 static struct clk rm_ick
= {
1186 .ops
= &clkops_null
,
1188 .init
= &omap2_init_clksel_parent
,
1189 .clksel_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_CLKSEL
),
1190 .clksel_mask
= OMAP3430_CLKSEL_RM_MASK
,
1191 .clksel
= div2_l4_clksel
,
1192 .recalc
= &omap2_clksel_recalc
,
1195 /* GFX power domain */
1197 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1199 static const struct clksel gfx_l3_clksel
[] = {
1200 { .parent
= &l3_ick
, .rates
= gfx_l3_rates
},
1205 * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
1206 * This interface clock does not have a CM_AUTOIDLE bit
1208 static struct clk gfx_l3_ck
= {
1209 .name
= "gfx_l3_ck",
1210 .ops
= &clkops_omap2_dflt_wait
,
1212 .enable_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_ICLKEN
),
1213 .enable_bit
= OMAP_EN_GFX_SHIFT
,
1214 .recalc
= &followparent_recalc
,
1217 static struct clk gfx_l3_fck
= {
1218 .name
= "gfx_l3_fck",
1219 .ops
= &clkops_null
,
1220 .parent
= &gfx_l3_ck
,
1221 .init
= &omap2_init_clksel_parent
,
1222 .clksel_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_CLKSEL
),
1223 .clksel_mask
= OMAP_CLKSEL_GFX_MASK
,
1224 .clksel
= gfx_l3_clksel
,
1225 .clkdm_name
= "gfx_3430es1_clkdm",
1226 .recalc
= &omap2_clksel_recalc
,
1229 static struct clk gfx_l3_ick
= {
1230 .name
= "gfx_l3_ick",
1231 .ops
= &clkops_null
,
1232 .parent
= &gfx_l3_ck
,
1233 .clkdm_name
= "gfx_3430es1_clkdm",
1234 .recalc
= &followparent_recalc
,
1237 static struct clk gfx_cg1_ck
= {
1238 .name
= "gfx_cg1_ck",
1239 .ops
= &clkops_omap2_dflt_wait
,
1240 .parent
= &gfx_l3_fck
, /* REVISIT: correct? */
1241 .enable_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_FCLKEN
),
1242 .enable_bit
= OMAP3430ES1_EN_2D_SHIFT
,
1243 .clkdm_name
= "gfx_3430es1_clkdm",
1244 .recalc
= &followparent_recalc
,
1247 static struct clk gfx_cg2_ck
= {
1248 .name
= "gfx_cg2_ck",
1249 .ops
= &clkops_omap2_dflt_wait
,
1250 .parent
= &gfx_l3_fck
, /* REVISIT: correct? */
1251 .enable_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_FCLKEN
),
1252 .enable_bit
= OMAP3430ES1_EN_3D_SHIFT
,
1253 .clkdm_name
= "gfx_3430es1_clkdm",
1254 .recalc
= &followparent_recalc
,
1257 /* SGX power domain - 3430ES2 only */
1259 static const struct clksel_rate sgx_core_rates
[] = {
1260 { .div
= 2, .val
= 5, .flags
= RATE_IN_36XX
},
1261 { .div
= 3, .val
= 0, .flags
= RATE_IN_3XXX
},
1262 { .div
= 4, .val
= 1, .flags
= RATE_IN_3XXX
},
1263 { .div
= 6, .val
= 2, .flags
= RATE_IN_3XXX
},
1267 static const struct clksel_rate sgx_192m_rates
[] = {
1268 { .div
= 1, .val
= 4, .flags
= RATE_IN_36XX
},
1272 static const struct clksel_rate sgx_corex2_rates
[] = {
1273 { .div
= 3, .val
= 6, .flags
= RATE_IN_36XX
},
1274 { .div
= 5, .val
= 7, .flags
= RATE_IN_36XX
},
1278 static const struct clksel_rate sgx_96m_rates
[] = {
1279 { .div
= 1, .val
= 3, .flags
= RATE_IN_3XXX
},
1283 static const struct clksel sgx_clksel
[] = {
1284 { .parent
= &core_ck
, .rates
= sgx_core_rates
},
1285 { .parent
= &cm_96m_fck
, .rates
= sgx_96m_rates
},
1286 { .parent
= &omap_192m_alwon_fck
, .rates
= sgx_192m_rates
},
1287 { .parent
= &corex2_fck
, .rates
= sgx_corex2_rates
},
1291 static struct clk sgx_fck
= {
1293 .ops
= &clkops_omap2_dflt_wait
,
1294 .init
= &omap2_init_clksel_parent
,
1295 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD
, CM_FCLKEN
),
1296 .enable_bit
= OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT
,
1297 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD
, CM_CLKSEL
),
1298 .clksel_mask
= OMAP3430ES2_CLKSEL_SGX_MASK
,
1299 .clksel
= sgx_clksel
,
1300 .clkdm_name
= "sgx_clkdm",
1301 .recalc
= &omap2_clksel_recalc
,
1302 .set_rate
= &omap2_clksel_set_rate
,
1303 .round_rate
= &omap2_clksel_round_rate
1306 /* This interface clock does not have a CM_AUTOIDLE bit */
1307 static struct clk sgx_ick
= {
1309 .ops
= &clkops_omap2_dflt_wait
,
1311 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD
, CM_ICLKEN
),
1312 .enable_bit
= OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT
,
1313 .clkdm_name
= "sgx_clkdm",
1314 .recalc
= &followparent_recalc
,
1317 /* CORE power domain */
1319 static struct clk d2d_26m_fck
= {
1320 .name
= "d2d_26m_fck",
1321 .ops
= &clkops_omap2_dflt_wait
,
1323 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1324 .enable_bit
= OMAP3430ES1_EN_D2D_SHIFT
,
1325 .clkdm_name
= "d2d_clkdm",
1326 .recalc
= &followparent_recalc
,
1329 static struct clk modem_fck
= {
1330 .name
= "modem_fck",
1331 .ops
= &clkops_omap2_mdmclk_dflt_wait
,
1333 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1334 .enable_bit
= OMAP3430_EN_MODEM_SHIFT
,
1335 .clkdm_name
= "d2d_clkdm",
1336 .recalc
= &followparent_recalc
,
1339 static struct clk sad2d_ick
= {
1340 .name
= "sad2d_ick",
1341 .ops
= &clkops_omap2_iclk_dflt_wait
,
1343 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1344 .enable_bit
= OMAP3430_EN_SAD2D_SHIFT
,
1345 .clkdm_name
= "d2d_clkdm",
1346 .recalc
= &followparent_recalc
,
1349 static struct clk mad2d_ick
= {
1350 .name
= "mad2d_ick",
1351 .ops
= &clkops_omap2_iclk_dflt_wait
,
1353 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN3
),
1354 .enable_bit
= OMAP3430_EN_MAD2D_SHIFT
,
1355 .clkdm_name
= "d2d_clkdm",
1356 .recalc
= &followparent_recalc
,
1359 static const struct clksel omap343x_gpt_clksel
[] = {
1360 { .parent
= &omap_32k_fck
, .rates
= gpt_32k_rates
},
1361 { .parent
= &sys_ck
, .rates
= gpt_sys_rates
},
1365 static struct clk gpt10_fck
= {
1366 .name
= "gpt10_fck",
1367 .ops
= &clkops_omap2_dflt_wait
,
1369 .init
= &omap2_init_clksel_parent
,
1370 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1371 .enable_bit
= OMAP3430_EN_GPT10_SHIFT
,
1372 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1373 .clksel_mask
= OMAP3430_CLKSEL_GPT10_MASK
,
1374 .clksel
= omap343x_gpt_clksel
,
1375 .clkdm_name
= "core_l4_clkdm",
1376 .recalc
= &omap2_clksel_recalc
,
1379 static struct clk gpt11_fck
= {
1380 .name
= "gpt11_fck",
1381 .ops
= &clkops_omap2_dflt_wait
,
1383 .init
= &omap2_init_clksel_parent
,
1384 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1385 .enable_bit
= OMAP3430_EN_GPT11_SHIFT
,
1386 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1387 .clksel_mask
= OMAP3430_CLKSEL_GPT11_MASK
,
1388 .clksel
= omap343x_gpt_clksel
,
1389 .clkdm_name
= "core_l4_clkdm",
1390 .recalc
= &omap2_clksel_recalc
,
1393 static struct clk cpefuse_fck
= {
1394 .name
= "cpefuse_fck",
1395 .ops
= &clkops_omap2_dflt
,
1397 .clkdm_name
= "core_l4_clkdm",
1398 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP3430ES2_CM_FCLKEN3
),
1399 .enable_bit
= OMAP3430ES2_EN_CPEFUSE_SHIFT
,
1400 .recalc
= &followparent_recalc
,
1403 static struct clk ts_fck
= {
1405 .ops
= &clkops_omap2_dflt
,
1406 .parent
= &omap_32k_fck
,
1407 .clkdm_name
= "core_l4_clkdm",
1408 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP3430ES2_CM_FCLKEN3
),
1409 .enable_bit
= OMAP3430ES2_EN_TS_SHIFT
,
1410 .recalc
= &followparent_recalc
,
1413 static struct clk usbtll_fck
= {
1414 .name
= "usbtll_fck",
1415 .ops
= &clkops_omap2_dflt_wait
,
1416 .parent
= &dpll5_m2_ck
,
1417 .clkdm_name
= "core_l4_clkdm",
1418 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP3430ES2_CM_FCLKEN3
),
1419 .enable_bit
= OMAP3430ES2_EN_USBTLL_SHIFT
,
1420 .recalc
= &followparent_recalc
,
1423 /* CORE 96M FCLK-derived clocks */
1425 static struct clk core_96m_fck
= {
1426 .name
= "core_96m_fck",
1427 .ops
= &clkops_null
,
1428 .parent
= &omap_96m_fck
,
1429 .clkdm_name
= "core_l4_clkdm",
1430 .recalc
= &followparent_recalc
,
1433 static struct clk mmchs3_fck
= {
1434 .name
= "mmchs3_fck",
1435 .ops
= &clkops_omap2_dflt_wait
,
1436 .parent
= &core_96m_fck
,
1437 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1438 .enable_bit
= OMAP3430ES2_EN_MMC3_SHIFT
,
1439 .clkdm_name
= "core_l4_clkdm",
1440 .recalc
= &followparent_recalc
,
1443 static struct clk mmchs2_fck
= {
1444 .name
= "mmchs2_fck",
1445 .ops
= &clkops_omap2_dflt_wait
,
1446 .parent
= &core_96m_fck
,
1447 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1448 .enable_bit
= OMAP3430_EN_MMC2_SHIFT
,
1449 .clkdm_name
= "core_l4_clkdm",
1450 .recalc
= &followparent_recalc
,
1453 static struct clk mspro_fck
= {
1454 .name
= "mspro_fck",
1455 .ops
= &clkops_omap2_dflt_wait
,
1456 .parent
= &core_96m_fck
,
1457 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1458 .enable_bit
= OMAP3430_EN_MSPRO_SHIFT
,
1459 .clkdm_name
= "core_l4_clkdm",
1460 .recalc
= &followparent_recalc
,
1463 static struct clk mmchs1_fck
= {
1464 .name
= "mmchs1_fck",
1465 .ops
= &clkops_omap2_dflt_wait
,
1466 .parent
= &core_96m_fck
,
1467 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1468 .enable_bit
= OMAP3430_EN_MMC1_SHIFT
,
1469 .clkdm_name
= "core_l4_clkdm",
1470 .recalc
= &followparent_recalc
,
1473 static struct clk i2c3_fck
= {
1475 .ops
= &clkops_omap2_dflt_wait
,
1476 .parent
= &core_96m_fck
,
1477 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1478 .enable_bit
= OMAP3430_EN_I2C3_SHIFT
,
1479 .clkdm_name
= "core_l4_clkdm",
1480 .recalc
= &followparent_recalc
,
1483 static struct clk i2c2_fck
= {
1485 .ops
= &clkops_omap2_dflt_wait
,
1486 .parent
= &core_96m_fck
,
1487 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1488 .enable_bit
= OMAP3430_EN_I2C2_SHIFT
,
1489 .clkdm_name
= "core_l4_clkdm",
1490 .recalc
= &followparent_recalc
,
1493 static struct clk i2c1_fck
= {
1495 .ops
= &clkops_omap2_dflt_wait
,
1496 .parent
= &core_96m_fck
,
1497 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1498 .enable_bit
= OMAP3430_EN_I2C1_SHIFT
,
1499 .clkdm_name
= "core_l4_clkdm",
1500 .recalc
= &followparent_recalc
,
1504 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1505 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1507 static const struct clksel_rate common_mcbsp_96m_rates
[] = {
1508 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
1512 static const struct clksel_rate common_mcbsp_mcbsp_rates
[] = {
1513 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
1517 static const struct clksel mcbsp_15_clksel
[] = {
1518 { .parent
= &core_96m_fck
, .rates
= common_mcbsp_96m_rates
},
1519 { .parent
= &mcbsp_clks
, .rates
= common_mcbsp_mcbsp_rates
},
1523 static struct clk mcbsp5_fck
= {
1524 .name
= "mcbsp5_fck",
1525 .ops
= &clkops_omap2_dflt_wait
,
1526 .init
= &omap2_init_clksel_parent
,
1527 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1528 .enable_bit
= OMAP3430_EN_MCBSP5_SHIFT
,
1529 .clksel_reg
= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1
),
1530 .clksel_mask
= OMAP2_MCBSP5_CLKS_MASK
,
1531 .clksel
= mcbsp_15_clksel
,
1532 .clkdm_name
= "core_l4_clkdm",
1533 .recalc
= &omap2_clksel_recalc
,
1536 static struct clk mcbsp1_fck
= {
1537 .name
= "mcbsp1_fck",
1538 .ops
= &clkops_omap2_dflt_wait
,
1539 .init
= &omap2_init_clksel_parent
,
1540 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1541 .enable_bit
= OMAP3430_EN_MCBSP1_SHIFT
,
1542 .clksel_reg
= OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0
),
1543 .clksel_mask
= OMAP2_MCBSP1_CLKS_MASK
,
1544 .clksel
= mcbsp_15_clksel
,
1545 .clkdm_name
= "core_l4_clkdm",
1546 .recalc
= &omap2_clksel_recalc
,
1549 /* CORE_48M_FCK-derived clocks */
1551 static struct clk core_48m_fck
= {
1552 .name
= "core_48m_fck",
1553 .ops
= &clkops_null
,
1554 .parent
= &omap_48m_fck
,
1555 .clkdm_name
= "core_l4_clkdm",
1556 .recalc
= &followparent_recalc
,
1559 static struct clk mcspi4_fck
= {
1560 .name
= "mcspi4_fck",
1561 .ops
= &clkops_omap2_dflt_wait
,
1562 .parent
= &core_48m_fck
,
1563 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1564 .enable_bit
= OMAP3430_EN_MCSPI4_SHIFT
,
1565 .recalc
= &followparent_recalc
,
1566 .clkdm_name
= "core_l4_clkdm",
1569 static struct clk mcspi3_fck
= {
1570 .name
= "mcspi3_fck",
1571 .ops
= &clkops_omap2_dflt_wait
,
1572 .parent
= &core_48m_fck
,
1573 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1574 .enable_bit
= OMAP3430_EN_MCSPI3_SHIFT
,
1575 .recalc
= &followparent_recalc
,
1576 .clkdm_name
= "core_l4_clkdm",
1579 static struct clk mcspi2_fck
= {
1580 .name
= "mcspi2_fck",
1581 .ops
= &clkops_omap2_dflt_wait
,
1582 .parent
= &core_48m_fck
,
1583 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1584 .enable_bit
= OMAP3430_EN_MCSPI2_SHIFT
,
1585 .recalc
= &followparent_recalc
,
1586 .clkdm_name
= "core_l4_clkdm",
1589 static struct clk mcspi1_fck
= {
1590 .name
= "mcspi1_fck",
1591 .ops
= &clkops_omap2_dflt_wait
,
1592 .parent
= &core_48m_fck
,
1593 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1594 .enable_bit
= OMAP3430_EN_MCSPI1_SHIFT
,
1595 .recalc
= &followparent_recalc
,
1596 .clkdm_name
= "core_l4_clkdm",
1599 static struct clk uart2_fck
= {
1600 .name
= "uart2_fck",
1601 .ops
= &clkops_omap2_dflt_wait
,
1602 .parent
= &core_48m_fck
,
1603 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1604 .enable_bit
= OMAP3430_EN_UART2_SHIFT
,
1605 .clkdm_name
= "core_l4_clkdm",
1606 .recalc
= &followparent_recalc
,
1609 static struct clk uart1_fck
= {
1610 .name
= "uart1_fck",
1611 .ops
= &clkops_omap2_dflt_wait
,
1612 .parent
= &core_48m_fck
,
1613 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1614 .enable_bit
= OMAP3430_EN_UART1_SHIFT
,
1615 .clkdm_name
= "core_l4_clkdm",
1616 .recalc
= &followparent_recalc
,
1619 static struct clk fshostusb_fck
= {
1620 .name
= "fshostusb_fck",
1621 .ops
= &clkops_omap2_dflt_wait
,
1622 .parent
= &core_48m_fck
,
1623 .clkdm_name
= "core_l4_clkdm",
1624 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1625 .enable_bit
= OMAP3430ES1_EN_FSHOSTUSB_SHIFT
,
1626 .recalc
= &followparent_recalc
,
1629 /* CORE_12M_FCK based clocks */
1631 static struct clk core_12m_fck
= {
1632 .name
= "core_12m_fck",
1633 .ops
= &clkops_null
,
1634 .parent
= &omap_12m_fck
,
1635 .clkdm_name
= "core_l4_clkdm",
1636 .recalc
= &followparent_recalc
,
1639 static struct clk hdq_fck
= {
1641 .ops
= &clkops_omap2_dflt_wait
,
1642 .parent
= &core_12m_fck
,
1643 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1644 .enable_bit
= OMAP3430_EN_HDQ_SHIFT
,
1645 .recalc
= &followparent_recalc
,
1648 /* DPLL3-derived clock */
1650 static const struct clksel_rate ssi_ssr_corex2_rates
[] = {
1651 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
1652 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
1653 { .div
= 3, .val
= 3, .flags
= RATE_IN_3XXX
},
1654 { .div
= 4, .val
= 4, .flags
= RATE_IN_3XXX
},
1655 { .div
= 6, .val
= 6, .flags
= RATE_IN_3XXX
},
1656 { .div
= 8, .val
= 8, .flags
= RATE_IN_3XXX
},
1660 static const struct clksel ssi_ssr_clksel
[] = {
1661 { .parent
= &corex2_fck
, .rates
= ssi_ssr_corex2_rates
},
1665 static struct clk ssi_ssr_fck_3430es1
= {
1666 .name
= "ssi_ssr_fck",
1667 .ops
= &clkops_omap2_dflt
,
1668 .init
= &omap2_init_clksel_parent
,
1669 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1670 .enable_bit
= OMAP3430_EN_SSI_SHIFT
,
1671 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1672 .clksel_mask
= OMAP3430_CLKSEL_SSI_MASK
,
1673 .clksel
= ssi_ssr_clksel
,
1674 .clkdm_name
= "core_l4_clkdm",
1675 .recalc
= &omap2_clksel_recalc
,
1678 static struct clk ssi_ssr_fck_3430es2
= {
1679 .name
= "ssi_ssr_fck",
1680 .ops
= &clkops_omap3430es2_ssi_wait
,
1681 .init
= &omap2_init_clksel_parent
,
1682 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1683 .enable_bit
= OMAP3430_EN_SSI_SHIFT
,
1684 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1685 .clksel_mask
= OMAP3430_CLKSEL_SSI_MASK
,
1686 .clksel
= ssi_ssr_clksel
,
1687 .clkdm_name
= "core_l4_clkdm",
1688 .recalc
= &omap2_clksel_recalc
,
1691 static struct clk ssi_sst_fck_3430es1
= {
1692 .name
= "ssi_sst_fck",
1693 .ops
= &clkops_null
,
1694 .parent
= &ssi_ssr_fck_3430es1
,
1696 .recalc
= &omap_fixed_divisor_recalc
,
1699 static struct clk ssi_sst_fck_3430es2
= {
1700 .name
= "ssi_sst_fck",
1701 .ops
= &clkops_null
,
1702 .parent
= &ssi_ssr_fck_3430es2
,
1704 .recalc
= &omap_fixed_divisor_recalc
,
1709 /* CORE_L3_ICK based clocks */
1712 * XXX must add clk_enable/clk_disable for these if standard code won't
1715 static struct clk core_l3_ick
= {
1716 .name
= "core_l3_ick",
1717 .ops
= &clkops_null
,
1719 .clkdm_name
= "core_l3_clkdm",
1720 .recalc
= &followparent_recalc
,
1723 static struct clk hsotgusb_ick_3430es1
= {
1724 .name
= "hsotgusb_ick",
1725 .ops
= &clkops_omap2_iclk_dflt
,
1726 .parent
= &core_l3_ick
,
1727 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1728 .enable_bit
= OMAP3430_EN_HSOTGUSB_SHIFT
,
1729 .clkdm_name
= "core_l3_clkdm",
1730 .recalc
= &followparent_recalc
,
1733 static struct clk hsotgusb_ick_3430es2
= {
1734 .name
= "hsotgusb_ick",
1735 .ops
= &clkops_omap3430es2_iclk_hsotgusb_wait
,
1736 .parent
= &core_l3_ick
,
1737 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1738 .enable_bit
= OMAP3430_EN_HSOTGUSB_SHIFT
,
1739 .clkdm_name
= "core_l3_clkdm",
1740 .recalc
= &followparent_recalc
,
1743 /* This interface clock does not have a CM_AUTOIDLE bit */
1744 static struct clk sdrc_ick
= {
1746 .ops
= &clkops_omap2_dflt_wait
,
1747 .parent
= &core_l3_ick
,
1748 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1749 .enable_bit
= OMAP3430_EN_SDRC_SHIFT
,
1750 .flags
= ENABLE_ON_INIT
,
1751 .clkdm_name
= "core_l3_clkdm",
1752 .recalc
= &followparent_recalc
,
1755 static struct clk gpmc_fck
= {
1757 .ops
= &clkops_null
,
1758 .parent
= &core_l3_ick
,
1759 .flags
= ENABLE_ON_INIT
, /* huh? */
1760 .clkdm_name
= "core_l3_clkdm",
1761 .recalc
= &followparent_recalc
,
1764 /* SECURITY_L3_ICK based clocks */
1766 static struct clk security_l3_ick
= {
1767 .name
= "security_l3_ick",
1768 .ops
= &clkops_null
,
1770 .recalc
= &followparent_recalc
,
1773 static struct clk pka_ick
= {
1775 .ops
= &clkops_omap2_iclk_dflt_wait
,
1776 .parent
= &security_l3_ick
,
1777 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
1778 .enable_bit
= OMAP3430_EN_PKA_SHIFT
,
1779 .recalc
= &followparent_recalc
,
1782 /* CORE_L4_ICK based clocks */
1784 static struct clk core_l4_ick
= {
1785 .name
= "core_l4_ick",
1786 .ops
= &clkops_null
,
1788 .clkdm_name
= "core_l4_clkdm",
1789 .recalc
= &followparent_recalc
,
1792 static struct clk usbtll_ick
= {
1793 .name
= "usbtll_ick",
1794 .ops
= &clkops_omap2_iclk_dflt_wait
,
1795 .parent
= &core_l4_ick
,
1796 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN3
),
1797 .enable_bit
= OMAP3430ES2_EN_USBTLL_SHIFT
,
1798 .clkdm_name
= "core_l4_clkdm",
1799 .recalc
= &followparent_recalc
,
1802 static struct clk mmchs3_ick
= {
1803 .name
= "mmchs3_ick",
1804 .ops
= &clkops_omap2_iclk_dflt_wait
,
1805 .parent
= &core_l4_ick
,
1806 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1807 .enable_bit
= OMAP3430ES2_EN_MMC3_SHIFT
,
1808 .clkdm_name
= "core_l4_clkdm",
1809 .recalc
= &followparent_recalc
,
1812 /* Intersystem Communication Registers - chassis mode only */
1813 static struct clk icr_ick
= {
1815 .ops
= &clkops_omap2_iclk_dflt_wait
,
1816 .parent
= &core_l4_ick
,
1817 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1818 .enable_bit
= OMAP3430_EN_ICR_SHIFT
,
1819 .clkdm_name
= "core_l4_clkdm",
1820 .recalc
= &followparent_recalc
,
1823 static struct clk aes2_ick
= {
1825 .ops
= &clkops_omap2_iclk_dflt_wait
,
1826 .parent
= &core_l4_ick
,
1827 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1828 .enable_bit
= OMAP3430_EN_AES2_SHIFT
,
1829 .clkdm_name
= "core_l4_clkdm",
1830 .recalc
= &followparent_recalc
,
1833 static struct clk sha12_ick
= {
1834 .name
= "sha12_ick",
1835 .ops
= &clkops_omap2_iclk_dflt_wait
,
1836 .parent
= &core_l4_ick
,
1837 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1838 .enable_bit
= OMAP3430_EN_SHA12_SHIFT
,
1839 .clkdm_name
= "core_l4_clkdm",
1840 .recalc
= &followparent_recalc
,
1843 static struct clk des2_ick
= {
1845 .ops
= &clkops_omap2_iclk_dflt_wait
,
1846 .parent
= &core_l4_ick
,
1847 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1848 .enable_bit
= OMAP3430_EN_DES2_SHIFT
,
1849 .clkdm_name
= "core_l4_clkdm",
1850 .recalc
= &followparent_recalc
,
1853 static struct clk mmchs2_ick
= {
1854 .name
= "mmchs2_ick",
1855 .ops
= &clkops_omap2_iclk_dflt_wait
,
1856 .parent
= &core_l4_ick
,
1857 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1858 .enable_bit
= OMAP3430_EN_MMC2_SHIFT
,
1859 .clkdm_name
= "core_l4_clkdm",
1860 .recalc
= &followparent_recalc
,
1863 static struct clk mmchs1_ick
= {
1864 .name
= "mmchs1_ick",
1865 .ops
= &clkops_omap2_iclk_dflt_wait
,
1866 .parent
= &core_l4_ick
,
1867 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1868 .enable_bit
= OMAP3430_EN_MMC1_SHIFT
,
1869 .clkdm_name
= "core_l4_clkdm",
1870 .recalc
= &followparent_recalc
,
1873 static struct clk mspro_ick
= {
1874 .name
= "mspro_ick",
1875 .ops
= &clkops_omap2_iclk_dflt_wait
,
1876 .parent
= &core_l4_ick
,
1877 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1878 .enable_bit
= OMAP3430_EN_MSPRO_SHIFT
,
1879 .clkdm_name
= "core_l4_clkdm",
1880 .recalc
= &followparent_recalc
,
1883 static struct clk hdq_ick
= {
1885 .ops
= &clkops_omap2_iclk_dflt_wait
,
1886 .parent
= &core_l4_ick
,
1887 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1888 .enable_bit
= OMAP3430_EN_HDQ_SHIFT
,
1889 .clkdm_name
= "core_l4_clkdm",
1890 .recalc
= &followparent_recalc
,
1893 static struct clk mcspi4_ick
= {
1894 .name
= "mcspi4_ick",
1895 .ops
= &clkops_omap2_iclk_dflt_wait
,
1896 .parent
= &core_l4_ick
,
1897 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1898 .enable_bit
= OMAP3430_EN_MCSPI4_SHIFT
,
1899 .clkdm_name
= "core_l4_clkdm",
1900 .recalc
= &followparent_recalc
,
1903 static struct clk mcspi3_ick
= {
1904 .name
= "mcspi3_ick",
1905 .ops
= &clkops_omap2_iclk_dflt_wait
,
1906 .parent
= &core_l4_ick
,
1907 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1908 .enable_bit
= OMAP3430_EN_MCSPI3_SHIFT
,
1909 .clkdm_name
= "core_l4_clkdm",
1910 .recalc
= &followparent_recalc
,
1913 static struct clk mcspi2_ick
= {
1914 .name
= "mcspi2_ick",
1915 .ops
= &clkops_omap2_iclk_dflt_wait
,
1916 .parent
= &core_l4_ick
,
1917 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1918 .enable_bit
= OMAP3430_EN_MCSPI2_SHIFT
,
1919 .clkdm_name
= "core_l4_clkdm",
1920 .recalc
= &followparent_recalc
,
1923 static struct clk mcspi1_ick
= {
1924 .name
= "mcspi1_ick",
1925 .ops
= &clkops_omap2_iclk_dflt_wait
,
1926 .parent
= &core_l4_ick
,
1927 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1928 .enable_bit
= OMAP3430_EN_MCSPI1_SHIFT
,
1929 .clkdm_name
= "core_l4_clkdm",
1930 .recalc
= &followparent_recalc
,
1933 static struct clk i2c3_ick
= {
1935 .ops
= &clkops_omap2_iclk_dflt_wait
,
1936 .parent
= &core_l4_ick
,
1937 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1938 .enable_bit
= OMAP3430_EN_I2C3_SHIFT
,
1939 .clkdm_name
= "core_l4_clkdm",
1940 .recalc
= &followparent_recalc
,
1943 static struct clk i2c2_ick
= {
1945 .ops
= &clkops_omap2_iclk_dflt_wait
,
1946 .parent
= &core_l4_ick
,
1947 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1948 .enable_bit
= OMAP3430_EN_I2C2_SHIFT
,
1949 .clkdm_name
= "core_l4_clkdm",
1950 .recalc
= &followparent_recalc
,
1953 static struct clk i2c1_ick
= {
1955 .ops
= &clkops_omap2_iclk_dflt_wait
,
1956 .parent
= &core_l4_ick
,
1957 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1958 .enable_bit
= OMAP3430_EN_I2C1_SHIFT
,
1959 .clkdm_name
= "core_l4_clkdm",
1960 .recalc
= &followparent_recalc
,
1963 static struct clk uart2_ick
= {
1964 .name
= "uart2_ick",
1965 .ops
= &clkops_omap2_iclk_dflt_wait
,
1966 .parent
= &core_l4_ick
,
1967 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1968 .enable_bit
= OMAP3430_EN_UART2_SHIFT
,
1969 .clkdm_name
= "core_l4_clkdm",
1970 .recalc
= &followparent_recalc
,
1973 static struct clk uart1_ick
= {
1974 .name
= "uart1_ick",
1975 .ops
= &clkops_omap2_iclk_dflt_wait
,
1976 .parent
= &core_l4_ick
,
1977 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1978 .enable_bit
= OMAP3430_EN_UART1_SHIFT
,
1979 .clkdm_name
= "core_l4_clkdm",
1980 .recalc
= &followparent_recalc
,
1983 static struct clk gpt11_ick
= {
1984 .name
= "gpt11_ick",
1985 .ops
= &clkops_omap2_iclk_dflt_wait
,
1986 .parent
= &core_l4_ick
,
1987 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1988 .enable_bit
= OMAP3430_EN_GPT11_SHIFT
,
1989 .clkdm_name
= "core_l4_clkdm",
1990 .recalc
= &followparent_recalc
,
1993 static struct clk gpt10_ick
= {
1994 .name
= "gpt10_ick",
1995 .ops
= &clkops_omap2_iclk_dflt_wait
,
1996 .parent
= &core_l4_ick
,
1997 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1998 .enable_bit
= OMAP3430_EN_GPT10_SHIFT
,
1999 .clkdm_name
= "core_l4_clkdm",
2000 .recalc
= &followparent_recalc
,
2003 static struct clk mcbsp5_ick
= {
2004 .name
= "mcbsp5_ick",
2005 .ops
= &clkops_omap2_iclk_dflt_wait
,
2006 .parent
= &core_l4_ick
,
2007 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2008 .enable_bit
= OMAP3430_EN_MCBSP5_SHIFT
,
2009 .clkdm_name
= "core_l4_clkdm",
2010 .recalc
= &followparent_recalc
,
2013 static struct clk mcbsp1_ick
= {
2014 .name
= "mcbsp1_ick",
2015 .ops
= &clkops_omap2_iclk_dflt_wait
,
2016 .parent
= &core_l4_ick
,
2017 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2018 .enable_bit
= OMAP3430_EN_MCBSP1_SHIFT
,
2019 .clkdm_name
= "core_l4_clkdm",
2020 .recalc
= &followparent_recalc
,
2023 static struct clk fac_ick
= {
2025 .ops
= &clkops_omap2_iclk_dflt_wait
,
2026 .parent
= &core_l4_ick
,
2027 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2028 .enable_bit
= OMAP3430ES1_EN_FAC_SHIFT
,
2029 .clkdm_name
= "core_l4_clkdm",
2030 .recalc
= &followparent_recalc
,
2033 static struct clk mailboxes_ick
= {
2034 .name
= "mailboxes_ick",
2035 .ops
= &clkops_omap2_iclk_dflt_wait
,
2036 .parent
= &core_l4_ick
,
2037 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2038 .enable_bit
= OMAP3430_EN_MAILBOXES_SHIFT
,
2039 .clkdm_name
= "core_l4_clkdm",
2040 .recalc
= &followparent_recalc
,
2043 static struct clk omapctrl_ick
= {
2044 .name
= "omapctrl_ick",
2045 .ops
= &clkops_omap2_iclk_dflt_wait
,
2046 .parent
= &core_l4_ick
,
2047 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2048 .enable_bit
= OMAP3430_EN_OMAPCTRL_SHIFT
,
2049 .flags
= ENABLE_ON_INIT
,
2050 .clkdm_name
= "core_l4_clkdm",
2051 .recalc
= &followparent_recalc
,
2054 /* SSI_L4_ICK based clocks */
2056 static struct clk ssi_l4_ick
= {
2057 .name
= "ssi_l4_ick",
2058 .ops
= &clkops_null
,
2060 .clkdm_name
= "core_l4_clkdm",
2061 .recalc
= &followparent_recalc
,
2064 static struct clk ssi_ick_3430es1
= {
2066 .ops
= &clkops_omap2_iclk_dflt
,
2067 .parent
= &ssi_l4_ick
,
2068 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2069 .enable_bit
= OMAP3430_EN_SSI_SHIFT
,
2070 .clkdm_name
= "core_l4_clkdm",
2071 .recalc
= &followparent_recalc
,
2074 static struct clk ssi_ick_3430es2
= {
2076 .ops
= &clkops_omap3430es2_iclk_ssi_wait
,
2077 .parent
= &ssi_l4_ick
,
2078 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2079 .enable_bit
= OMAP3430_EN_SSI_SHIFT
,
2080 .clkdm_name
= "core_l4_clkdm",
2081 .recalc
= &followparent_recalc
,
2084 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2085 * but l4_ick makes more sense to me */
2087 static const struct clksel usb_l4_clksel
[] = {
2088 { .parent
= &l4_ick
, .rates
= div2_rates
},
2092 static struct clk usb_l4_ick
= {
2093 .name
= "usb_l4_ick",
2094 .ops
= &clkops_omap2_iclk_dflt_wait
,
2096 .init
= &omap2_init_clksel_parent
,
2097 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2098 .enable_bit
= OMAP3430ES1_EN_FSHOSTUSB_SHIFT
,
2099 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
2100 .clksel_mask
= OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK
,
2101 .clksel
= usb_l4_clksel
,
2102 .clkdm_name
= "core_l4_clkdm",
2103 .recalc
= &omap2_clksel_recalc
,
2106 /* SECURITY_L4_ICK2 based clocks */
2108 static struct clk security_l4_ick2
= {
2109 .name
= "security_l4_ick2",
2110 .ops
= &clkops_null
,
2112 .recalc
= &followparent_recalc
,
2115 static struct clk aes1_ick
= {
2117 .ops
= &clkops_omap2_iclk_dflt_wait
,
2118 .parent
= &security_l4_ick2
,
2119 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
2120 .enable_bit
= OMAP3430_EN_AES1_SHIFT
,
2121 .recalc
= &followparent_recalc
,
2124 static struct clk rng_ick
= {
2126 .ops
= &clkops_omap2_iclk_dflt_wait
,
2127 .parent
= &security_l4_ick2
,
2128 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
2129 .enable_bit
= OMAP3430_EN_RNG_SHIFT
,
2130 .recalc
= &followparent_recalc
,
2133 static struct clk sha11_ick
= {
2134 .name
= "sha11_ick",
2135 .ops
= &clkops_omap2_iclk_dflt_wait
,
2136 .parent
= &security_l4_ick2
,
2137 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
2138 .enable_bit
= OMAP3430_EN_SHA11_SHIFT
,
2139 .recalc
= &followparent_recalc
,
2142 static struct clk des1_ick
= {
2144 .ops
= &clkops_omap2_iclk_dflt_wait
,
2145 .parent
= &security_l4_ick2
,
2146 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
2147 .enable_bit
= OMAP3430_EN_DES1_SHIFT
,
2148 .recalc
= &followparent_recalc
,
2152 static struct clk dss1_alwon_fck_3430es1
= {
2153 .name
= "dss1_alwon_fck",
2154 .ops
= &clkops_omap2_dflt
,
2155 .parent
= &dpll4_m4x2_ck
,
2156 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
2157 .enable_bit
= OMAP3430_EN_DSS1_SHIFT
,
2158 .clkdm_name
= "dss_clkdm",
2159 .recalc
= &followparent_recalc
,
2162 static struct clk dss1_alwon_fck_3430es2
= {
2163 .name
= "dss1_alwon_fck",
2164 .ops
= &clkops_omap3430es2_dss_usbhost_wait
,
2165 .parent
= &dpll4_m4x2_ck
,
2166 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
2167 .enable_bit
= OMAP3430_EN_DSS1_SHIFT
,
2168 .clkdm_name
= "dss_clkdm",
2169 .recalc
= &followparent_recalc
,
2172 static struct clk dss_tv_fck
= {
2173 .name
= "dss_tv_fck",
2174 .ops
= &clkops_omap2_dflt
,
2175 .parent
= &omap_54m_fck
,
2176 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
2177 .enable_bit
= OMAP3430_EN_TV_SHIFT
,
2178 .clkdm_name
= "dss_clkdm",
2179 .recalc
= &followparent_recalc
,
2182 static struct clk dss_96m_fck
= {
2183 .name
= "dss_96m_fck",
2184 .ops
= &clkops_omap2_dflt
,
2185 .parent
= &omap_96m_fck
,
2186 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
2187 .enable_bit
= OMAP3430_EN_TV_SHIFT
,
2188 .clkdm_name
= "dss_clkdm",
2189 .recalc
= &followparent_recalc
,
2192 static struct clk dss2_alwon_fck
= {
2193 .name
= "dss2_alwon_fck",
2194 .ops
= &clkops_omap2_dflt
,
2196 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
2197 .enable_bit
= OMAP3430_EN_DSS2_SHIFT
,
2198 .clkdm_name
= "dss_clkdm",
2199 .recalc
= &followparent_recalc
,
2202 static struct clk dss_ick_3430es1
= {
2203 /* Handles both L3 and L4 clocks */
2205 .ops
= &clkops_omap2_iclk_dflt
,
2207 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_ICLKEN
),
2208 .enable_bit
= OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT
,
2209 .clkdm_name
= "dss_clkdm",
2210 .recalc
= &followparent_recalc
,
2213 static struct clk dss_ick_3430es2
= {
2214 /* Handles both L3 and L4 clocks */
2216 .ops
= &clkops_omap3430es2_iclk_dss_usbhost_wait
,
2218 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_ICLKEN
),
2219 .enable_bit
= OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT
,
2220 .clkdm_name
= "dss_clkdm",
2221 .recalc
= &followparent_recalc
,
2226 static struct clk cam_mclk
= {
2228 .ops
= &clkops_omap2_dflt
,
2229 .parent
= &dpll4_m5x2_ck
,
2230 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_FCLKEN
),
2231 .enable_bit
= OMAP3430_EN_CAM_SHIFT
,
2232 .clkdm_name
= "cam_clkdm",
2233 .recalc
= &followparent_recalc
,
2236 static struct clk cam_ick
= {
2237 /* Handles both L3 and L4 clocks */
2239 .ops
= &clkops_omap2_iclk_dflt
,
2241 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_ICLKEN
),
2242 .enable_bit
= OMAP3430_EN_CAM_SHIFT
,
2243 .clkdm_name
= "cam_clkdm",
2244 .recalc
= &followparent_recalc
,
2247 static struct clk csi2_96m_fck
= {
2248 .name
= "csi2_96m_fck",
2249 .ops
= &clkops_omap2_dflt
,
2250 .parent
= &core_96m_fck
,
2251 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_FCLKEN
),
2252 .enable_bit
= OMAP3430_EN_CSI2_SHIFT
,
2253 .clkdm_name
= "cam_clkdm",
2254 .recalc
= &followparent_recalc
,
2257 /* USBHOST - 3430ES2 only */
2259 static struct clk usbhost_120m_fck
= {
2260 .name
= "usbhost_120m_fck",
2261 .ops
= &clkops_omap2_dflt
,
2262 .parent
= &dpll5_m2_ck
,
2263 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD
, CM_FCLKEN
),
2264 .enable_bit
= OMAP3430ES2_EN_USBHOST2_SHIFT
,
2265 .clkdm_name
= "usbhost_clkdm",
2266 .recalc
= &followparent_recalc
,
2269 static struct clk usbhost_48m_fck
= {
2270 .name
= "usbhost_48m_fck",
2271 .ops
= &clkops_omap3430es2_dss_usbhost_wait
,
2272 .parent
= &omap_48m_fck
,
2273 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD
, CM_FCLKEN
),
2274 .enable_bit
= OMAP3430ES2_EN_USBHOST1_SHIFT
,
2275 .clkdm_name
= "usbhost_clkdm",
2276 .recalc
= &followparent_recalc
,
2279 static struct clk usbhost_ick
= {
2280 /* Handles both L3 and L4 clocks */
2281 .name
= "usbhost_ick",
2282 .ops
= &clkops_omap3430es2_iclk_dss_usbhost_wait
,
2284 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD
, CM_ICLKEN
),
2285 .enable_bit
= OMAP3430ES2_EN_USBHOST_SHIFT
,
2286 .clkdm_name
= "usbhost_clkdm",
2287 .recalc
= &followparent_recalc
,
2292 static const struct clksel_rate usim_96m_rates
[] = {
2293 { .div
= 2, .val
= 3, .flags
= RATE_IN_3XXX
},
2294 { .div
= 4, .val
= 4, .flags
= RATE_IN_3XXX
},
2295 { .div
= 8, .val
= 5, .flags
= RATE_IN_3XXX
},
2296 { .div
= 10, .val
= 6, .flags
= RATE_IN_3XXX
},
2300 static const struct clksel_rate usim_120m_rates
[] = {
2301 { .div
= 4, .val
= 7, .flags
= RATE_IN_3XXX
},
2302 { .div
= 8, .val
= 8, .flags
= RATE_IN_3XXX
},
2303 { .div
= 16, .val
= 9, .flags
= RATE_IN_3XXX
},
2304 { .div
= 20, .val
= 10, .flags
= RATE_IN_3XXX
},
2308 static const struct clksel usim_clksel
[] = {
2309 { .parent
= &omap_96m_fck
, .rates
= usim_96m_rates
},
2310 { .parent
= &dpll5_m2_ck
, .rates
= usim_120m_rates
},
2311 { .parent
= &sys_ck
, .rates
= div2_rates
},
2316 static struct clk usim_fck
= {
2318 .ops
= &clkops_omap2_dflt_wait
,
2319 .init
= &omap2_init_clksel_parent
,
2320 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
2321 .enable_bit
= OMAP3430ES2_EN_USIMOCP_SHIFT
,
2322 .clksel_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_CLKSEL
),
2323 .clksel_mask
= OMAP3430ES2_CLKSEL_USIMOCP_MASK
,
2324 .clksel
= usim_clksel
,
2325 .recalc
= &omap2_clksel_recalc
,
2328 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2329 static struct clk gpt1_fck
= {
2331 .ops
= &clkops_omap2_dflt_wait
,
2332 .init
= &omap2_init_clksel_parent
,
2333 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
2334 .enable_bit
= OMAP3430_EN_GPT1_SHIFT
,
2335 .clksel_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_CLKSEL
),
2336 .clksel_mask
= OMAP3430_CLKSEL_GPT1_MASK
,
2337 .clksel
= omap343x_gpt_clksel
,
2338 .clkdm_name
= "wkup_clkdm",
2339 .recalc
= &omap2_clksel_recalc
,
2342 static struct clk wkup_32k_fck
= {
2343 .name
= "wkup_32k_fck",
2344 .ops
= &clkops_null
,
2345 .parent
= &omap_32k_fck
,
2346 .clkdm_name
= "wkup_clkdm",
2347 .recalc
= &followparent_recalc
,
2350 static struct clk gpio1_dbck
= {
2351 .name
= "gpio1_dbck",
2352 .ops
= &clkops_omap2_dflt
,
2353 .parent
= &wkup_32k_fck
,
2354 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
2355 .enable_bit
= OMAP3430_EN_GPIO1_SHIFT
,
2356 .clkdm_name
= "wkup_clkdm",
2357 .recalc
= &followparent_recalc
,
2360 static struct clk wdt2_fck
= {
2362 .ops
= &clkops_omap2_dflt_wait
,
2363 .parent
= &wkup_32k_fck
,
2364 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
2365 .enable_bit
= OMAP3430_EN_WDT2_SHIFT
,
2366 .clkdm_name
= "wkup_clkdm",
2367 .recalc
= &followparent_recalc
,
2370 static struct clk wkup_l4_ick
= {
2371 .name
= "wkup_l4_ick",
2372 .ops
= &clkops_null
,
2374 .clkdm_name
= "wkup_clkdm",
2375 .recalc
= &followparent_recalc
,
2379 /* Never specifically named in the TRM, so we have to infer a likely name */
2380 static struct clk usim_ick
= {
2382 .ops
= &clkops_omap2_iclk_dflt_wait
,
2383 .parent
= &wkup_l4_ick
,
2384 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2385 .enable_bit
= OMAP3430ES2_EN_USIMOCP_SHIFT
,
2386 .clkdm_name
= "wkup_clkdm",
2387 .recalc
= &followparent_recalc
,
2390 static struct clk wdt2_ick
= {
2392 .ops
= &clkops_omap2_iclk_dflt_wait
,
2393 .parent
= &wkup_l4_ick
,
2394 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2395 .enable_bit
= OMAP3430_EN_WDT2_SHIFT
,
2396 .clkdm_name
= "wkup_clkdm",
2397 .recalc
= &followparent_recalc
,
2400 static struct clk wdt1_ick
= {
2402 .ops
= &clkops_omap2_iclk_dflt_wait
,
2403 .parent
= &wkup_l4_ick
,
2404 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2405 .enable_bit
= OMAP3430_EN_WDT1_SHIFT
,
2406 .clkdm_name
= "wkup_clkdm",
2407 .recalc
= &followparent_recalc
,
2410 static struct clk gpio1_ick
= {
2411 .name
= "gpio1_ick",
2412 .ops
= &clkops_omap2_iclk_dflt_wait
,
2413 .parent
= &wkup_l4_ick
,
2414 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2415 .enable_bit
= OMAP3430_EN_GPIO1_SHIFT
,
2416 .clkdm_name
= "wkup_clkdm",
2417 .recalc
= &followparent_recalc
,
2420 static struct clk omap_32ksync_ick
= {
2421 .name
= "omap_32ksync_ick",
2422 .ops
= &clkops_omap2_iclk_dflt_wait
,
2423 .parent
= &wkup_l4_ick
,
2424 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2425 .enable_bit
= OMAP3430_EN_32KSYNC_SHIFT
,
2426 .clkdm_name
= "wkup_clkdm",
2427 .recalc
= &followparent_recalc
,
2430 /* XXX This clock no longer exists in 3430 TRM rev F */
2431 static struct clk gpt12_ick
= {
2432 .name
= "gpt12_ick",
2433 .ops
= &clkops_omap2_iclk_dflt_wait
,
2434 .parent
= &wkup_l4_ick
,
2435 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2436 .enable_bit
= OMAP3430_EN_GPT12_SHIFT
,
2437 .clkdm_name
= "wkup_clkdm",
2438 .recalc
= &followparent_recalc
,
2441 static struct clk gpt1_ick
= {
2443 .ops
= &clkops_omap2_iclk_dflt_wait
,
2444 .parent
= &wkup_l4_ick
,
2445 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2446 .enable_bit
= OMAP3430_EN_GPT1_SHIFT
,
2447 .clkdm_name
= "wkup_clkdm",
2448 .recalc
= &followparent_recalc
,
2453 /* PER clock domain */
2455 static struct clk per_96m_fck
= {
2456 .name
= "per_96m_fck",
2457 .ops
= &clkops_null
,
2458 .parent
= &omap_96m_alwon_fck
,
2459 .clkdm_name
= "per_clkdm",
2460 .recalc
= &followparent_recalc
,
2463 static struct clk per_48m_fck
= {
2464 .name
= "per_48m_fck",
2465 .ops
= &clkops_null
,
2466 .parent
= &omap_48m_fck
,
2467 .clkdm_name
= "per_clkdm",
2468 .recalc
= &followparent_recalc
,
2471 static struct clk uart3_fck
= {
2472 .name
= "uart3_fck",
2473 .ops
= &clkops_omap2_dflt_wait
,
2474 .parent
= &per_48m_fck
,
2475 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2476 .enable_bit
= OMAP3430_EN_UART3_SHIFT
,
2477 .clkdm_name
= "per_clkdm",
2478 .recalc
= &followparent_recalc
,
2481 static struct clk uart4_fck
= {
2482 .name
= "uart4_fck",
2483 .ops
= &clkops_omap2_dflt_wait
,
2484 .parent
= &per_48m_fck
,
2485 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2486 .enable_bit
= OMAP3630_EN_UART4_SHIFT
,
2487 .clkdm_name
= "per_clkdm",
2488 .recalc
= &followparent_recalc
,
2491 static struct clk uart4_fck_am35xx
= {
2492 .name
= "uart4_fck",
2493 .ops
= &clkops_omap2_dflt_wait
,
2494 .parent
= &per_48m_fck
,
2495 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2496 .enable_bit
= OMAP3430_EN_UART4_SHIFT
,
2497 .clkdm_name
= "core_l4_clkdm",
2498 .recalc
= &followparent_recalc
,
2501 static struct clk gpt2_fck
= {
2503 .ops
= &clkops_omap2_dflt_wait
,
2504 .init
= &omap2_init_clksel_parent
,
2505 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2506 .enable_bit
= OMAP3430_EN_GPT2_SHIFT
,
2507 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2508 .clksel_mask
= OMAP3430_CLKSEL_GPT2_MASK
,
2509 .clksel
= omap343x_gpt_clksel
,
2510 .clkdm_name
= "per_clkdm",
2511 .recalc
= &omap2_clksel_recalc
,
2514 static struct clk gpt3_fck
= {
2516 .ops
= &clkops_omap2_dflt_wait
,
2517 .init
= &omap2_init_clksel_parent
,
2518 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2519 .enable_bit
= OMAP3430_EN_GPT3_SHIFT
,
2520 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2521 .clksel_mask
= OMAP3430_CLKSEL_GPT3_MASK
,
2522 .clksel
= omap343x_gpt_clksel
,
2523 .clkdm_name
= "per_clkdm",
2524 .recalc
= &omap2_clksel_recalc
,
2527 static struct clk gpt4_fck
= {
2529 .ops
= &clkops_omap2_dflt_wait
,
2530 .init
= &omap2_init_clksel_parent
,
2531 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2532 .enable_bit
= OMAP3430_EN_GPT4_SHIFT
,
2533 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2534 .clksel_mask
= OMAP3430_CLKSEL_GPT4_MASK
,
2535 .clksel
= omap343x_gpt_clksel
,
2536 .clkdm_name
= "per_clkdm",
2537 .recalc
= &omap2_clksel_recalc
,
2540 static struct clk gpt5_fck
= {
2542 .ops
= &clkops_omap2_dflt_wait
,
2543 .init
= &omap2_init_clksel_parent
,
2544 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2545 .enable_bit
= OMAP3430_EN_GPT5_SHIFT
,
2546 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2547 .clksel_mask
= OMAP3430_CLKSEL_GPT5_MASK
,
2548 .clksel
= omap343x_gpt_clksel
,
2549 .clkdm_name
= "per_clkdm",
2550 .recalc
= &omap2_clksel_recalc
,
2553 static struct clk gpt6_fck
= {
2555 .ops
= &clkops_omap2_dflt_wait
,
2556 .init
= &omap2_init_clksel_parent
,
2557 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2558 .enable_bit
= OMAP3430_EN_GPT6_SHIFT
,
2559 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2560 .clksel_mask
= OMAP3430_CLKSEL_GPT6_MASK
,
2561 .clksel
= omap343x_gpt_clksel
,
2562 .clkdm_name
= "per_clkdm",
2563 .recalc
= &omap2_clksel_recalc
,
2566 static struct clk gpt7_fck
= {
2568 .ops
= &clkops_omap2_dflt_wait
,
2569 .init
= &omap2_init_clksel_parent
,
2570 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2571 .enable_bit
= OMAP3430_EN_GPT7_SHIFT
,
2572 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2573 .clksel_mask
= OMAP3430_CLKSEL_GPT7_MASK
,
2574 .clksel
= omap343x_gpt_clksel
,
2575 .clkdm_name
= "per_clkdm",
2576 .recalc
= &omap2_clksel_recalc
,
2579 static struct clk gpt8_fck
= {
2581 .ops
= &clkops_omap2_dflt_wait
,
2582 .init
= &omap2_init_clksel_parent
,
2583 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2584 .enable_bit
= OMAP3430_EN_GPT8_SHIFT
,
2585 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2586 .clksel_mask
= OMAP3430_CLKSEL_GPT8_MASK
,
2587 .clksel
= omap343x_gpt_clksel
,
2588 .clkdm_name
= "per_clkdm",
2589 .recalc
= &omap2_clksel_recalc
,
2592 static struct clk gpt9_fck
= {
2594 .ops
= &clkops_omap2_dflt_wait
,
2595 .init
= &omap2_init_clksel_parent
,
2596 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2597 .enable_bit
= OMAP3430_EN_GPT9_SHIFT
,
2598 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
2599 .clksel_mask
= OMAP3430_CLKSEL_GPT9_MASK
,
2600 .clksel
= omap343x_gpt_clksel
,
2601 .clkdm_name
= "per_clkdm",
2602 .recalc
= &omap2_clksel_recalc
,
2605 static struct clk per_32k_alwon_fck
= {
2606 .name
= "per_32k_alwon_fck",
2607 .ops
= &clkops_null
,
2608 .parent
= &omap_32k_fck
,
2609 .clkdm_name
= "per_clkdm",
2610 .recalc
= &followparent_recalc
,
2613 static struct clk gpio6_dbck
= {
2614 .name
= "gpio6_dbck",
2615 .ops
= &clkops_omap2_dflt
,
2616 .parent
= &per_32k_alwon_fck
,
2617 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2618 .enable_bit
= OMAP3430_EN_GPIO6_SHIFT
,
2619 .clkdm_name
= "per_clkdm",
2620 .recalc
= &followparent_recalc
,
2623 static struct clk gpio5_dbck
= {
2624 .name
= "gpio5_dbck",
2625 .ops
= &clkops_omap2_dflt
,
2626 .parent
= &per_32k_alwon_fck
,
2627 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2628 .enable_bit
= OMAP3430_EN_GPIO5_SHIFT
,
2629 .clkdm_name
= "per_clkdm",
2630 .recalc
= &followparent_recalc
,
2633 static struct clk gpio4_dbck
= {
2634 .name
= "gpio4_dbck",
2635 .ops
= &clkops_omap2_dflt
,
2636 .parent
= &per_32k_alwon_fck
,
2637 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2638 .enable_bit
= OMAP3430_EN_GPIO4_SHIFT
,
2639 .clkdm_name
= "per_clkdm",
2640 .recalc
= &followparent_recalc
,
2643 static struct clk gpio3_dbck
= {
2644 .name
= "gpio3_dbck",
2645 .ops
= &clkops_omap2_dflt
,
2646 .parent
= &per_32k_alwon_fck
,
2647 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2648 .enable_bit
= OMAP3430_EN_GPIO3_SHIFT
,
2649 .clkdm_name
= "per_clkdm",
2650 .recalc
= &followparent_recalc
,
2653 static struct clk gpio2_dbck
= {
2654 .name
= "gpio2_dbck",
2655 .ops
= &clkops_omap2_dflt
,
2656 .parent
= &per_32k_alwon_fck
,
2657 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2658 .enable_bit
= OMAP3430_EN_GPIO2_SHIFT
,
2659 .clkdm_name
= "per_clkdm",
2660 .recalc
= &followparent_recalc
,
2663 static struct clk wdt3_fck
= {
2665 .ops
= &clkops_omap2_dflt_wait
,
2666 .parent
= &per_32k_alwon_fck
,
2667 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2668 .enable_bit
= OMAP3430_EN_WDT3_SHIFT
,
2669 .clkdm_name
= "per_clkdm",
2670 .recalc
= &followparent_recalc
,
2673 static struct clk per_l4_ick
= {
2674 .name
= "per_l4_ick",
2675 .ops
= &clkops_null
,
2677 .clkdm_name
= "per_clkdm",
2678 .recalc
= &followparent_recalc
,
2681 static struct clk gpio6_ick
= {
2682 .name
= "gpio6_ick",
2683 .ops
= &clkops_omap2_iclk_dflt_wait
,
2684 .parent
= &per_l4_ick
,
2685 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2686 .enable_bit
= OMAP3430_EN_GPIO6_SHIFT
,
2687 .clkdm_name
= "per_clkdm",
2688 .recalc
= &followparent_recalc
,
2691 static struct clk gpio5_ick
= {
2692 .name
= "gpio5_ick",
2693 .ops
= &clkops_omap2_iclk_dflt_wait
,
2694 .parent
= &per_l4_ick
,
2695 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2696 .enable_bit
= OMAP3430_EN_GPIO5_SHIFT
,
2697 .clkdm_name
= "per_clkdm",
2698 .recalc
= &followparent_recalc
,
2701 static struct clk gpio4_ick
= {
2702 .name
= "gpio4_ick",
2703 .ops
= &clkops_omap2_iclk_dflt_wait
,
2704 .parent
= &per_l4_ick
,
2705 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2706 .enable_bit
= OMAP3430_EN_GPIO4_SHIFT
,
2707 .clkdm_name
= "per_clkdm",
2708 .recalc
= &followparent_recalc
,
2711 static struct clk gpio3_ick
= {
2712 .name
= "gpio3_ick",
2713 .ops
= &clkops_omap2_iclk_dflt_wait
,
2714 .parent
= &per_l4_ick
,
2715 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2716 .enable_bit
= OMAP3430_EN_GPIO3_SHIFT
,
2717 .clkdm_name
= "per_clkdm",
2718 .recalc
= &followparent_recalc
,
2721 static struct clk gpio2_ick
= {
2722 .name
= "gpio2_ick",
2723 .ops
= &clkops_omap2_iclk_dflt_wait
,
2724 .parent
= &per_l4_ick
,
2725 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2726 .enable_bit
= OMAP3430_EN_GPIO2_SHIFT
,
2727 .clkdm_name
= "per_clkdm",
2728 .recalc
= &followparent_recalc
,
2731 static struct clk wdt3_ick
= {
2733 .ops
= &clkops_omap2_iclk_dflt_wait
,
2734 .parent
= &per_l4_ick
,
2735 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2736 .enable_bit
= OMAP3430_EN_WDT3_SHIFT
,
2737 .clkdm_name
= "per_clkdm",
2738 .recalc
= &followparent_recalc
,
2741 static struct clk uart3_ick
= {
2742 .name
= "uart3_ick",
2743 .ops
= &clkops_omap2_iclk_dflt_wait
,
2744 .parent
= &per_l4_ick
,
2745 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2746 .enable_bit
= OMAP3430_EN_UART3_SHIFT
,
2747 .clkdm_name
= "per_clkdm",
2748 .recalc
= &followparent_recalc
,
2751 static struct clk uart4_ick
= {
2752 .name
= "uart4_ick",
2753 .ops
= &clkops_omap2_iclk_dflt_wait
,
2754 .parent
= &per_l4_ick
,
2755 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2756 .enable_bit
= OMAP3630_EN_UART4_SHIFT
,
2757 .clkdm_name
= "per_clkdm",
2758 .recalc
= &followparent_recalc
,
2761 static struct clk gpt9_ick
= {
2763 .ops
= &clkops_omap2_iclk_dflt_wait
,
2764 .parent
= &per_l4_ick
,
2765 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2766 .enable_bit
= OMAP3430_EN_GPT9_SHIFT
,
2767 .clkdm_name
= "per_clkdm",
2768 .recalc
= &followparent_recalc
,
2771 static struct clk gpt8_ick
= {
2773 .ops
= &clkops_omap2_iclk_dflt_wait
,
2774 .parent
= &per_l4_ick
,
2775 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2776 .enable_bit
= OMAP3430_EN_GPT8_SHIFT
,
2777 .clkdm_name
= "per_clkdm",
2778 .recalc
= &followparent_recalc
,
2781 static struct clk gpt7_ick
= {
2783 .ops
= &clkops_omap2_iclk_dflt_wait
,
2784 .parent
= &per_l4_ick
,
2785 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2786 .enable_bit
= OMAP3430_EN_GPT7_SHIFT
,
2787 .clkdm_name
= "per_clkdm",
2788 .recalc
= &followparent_recalc
,
2791 static struct clk gpt6_ick
= {
2793 .ops
= &clkops_omap2_iclk_dflt_wait
,
2794 .parent
= &per_l4_ick
,
2795 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2796 .enable_bit
= OMAP3430_EN_GPT6_SHIFT
,
2797 .clkdm_name
= "per_clkdm",
2798 .recalc
= &followparent_recalc
,
2801 static struct clk gpt5_ick
= {
2803 .ops
= &clkops_omap2_iclk_dflt_wait
,
2804 .parent
= &per_l4_ick
,
2805 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2806 .enable_bit
= OMAP3430_EN_GPT5_SHIFT
,
2807 .clkdm_name
= "per_clkdm",
2808 .recalc
= &followparent_recalc
,
2811 static struct clk gpt4_ick
= {
2813 .ops
= &clkops_omap2_iclk_dflt_wait
,
2814 .parent
= &per_l4_ick
,
2815 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2816 .enable_bit
= OMAP3430_EN_GPT4_SHIFT
,
2817 .clkdm_name
= "per_clkdm",
2818 .recalc
= &followparent_recalc
,
2821 static struct clk gpt3_ick
= {
2823 .ops
= &clkops_omap2_iclk_dflt_wait
,
2824 .parent
= &per_l4_ick
,
2825 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2826 .enable_bit
= OMAP3430_EN_GPT3_SHIFT
,
2827 .clkdm_name
= "per_clkdm",
2828 .recalc
= &followparent_recalc
,
2831 static struct clk gpt2_ick
= {
2833 .ops
= &clkops_omap2_iclk_dflt_wait
,
2834 .parent
= &per_l4_ick
,
2835 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2836 .enable_bit
= OMAP3430_EN_GPT2_SHIFT
,
2837 .clkdm_name
= "per_clkdm",
2838 .recalc
= &followparent_recalc
,
2841 static struct clk mcbsp2_ick
= {
2842 .name
= "mcbsp2_ick",
2843 .ops
= &clkops_omap2_iclk_dflt_wait
,
2844 .parent
= &per_l4_ick
,
2845 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2846 .enable_bit
= OMAP3430_EN_MCBSP2_SHIFT
,
2847 .clkdm_name
= "per_clkdm",
2848 .recalc
= &followparent_recalc
,
2851 static struct clk mcbsp3_ick
= {
2852 .name
= "mcbsp3_ick",
2853 .ops
= &clkops_omap2_iclk_dflt_wait
,
2854 .parent
= &per_l4_ick
,
2855 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2856 .enable_bit
= OMAP3430_EN_MCBSP3_SHIFT
,
2857 .clkdm_name
= "per_clkdm",
2858 .recalc
= &followparent_recalc
,
2861 static struct clk mcbsp4_ick
= {
2862 .name
= "mcbsp4_ick",
2863 .ops
= &clkops_omap2_iclk_dflt_wait
,
2864 .parent
= &per_l4_ick
,
2865 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2866 .enable_bit
= OMAP3430_EN_MCBSP4_SHIFT
,
2867 .clkdm_name
= "per_clkdm",
2868 .recalc
= &followparent_recalc
,
2871 static const struct clksel mcbsp_234_clksel
[] = {
2872 { .parent
= &per_96m_fck
, .rates
= common_mcbsp_96m_rates
},
2873 { .parent
= &mcbsp_clks
, .rates
= common_mcbsp_mcbsp_rates
},
2877 static struct clk mcbsp2_fck
= {
2878 .name
= "mcbsp2_fck",
2879 .ops
= &clkops_omap2_dflt_wait
,
2880 .init
= &omap2_init_clksel_parent
,
2881 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2882 .enable_bit
= OMAP3430_EN_MCBSP2_SHIFT
,
2883 .clksel_reg
= OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0
),
2884 .clksel_mask
= OMAP2_MCBSP2_CLKS_MASK
,
2885 .clksel
= mcbsp_234_clksel
,
2886 .clkdm_name
= "per_clkdm",
2887 .recalc
= &omap2_clksel_recalc
,
2890 static struct clk mcbsp3_fck
= {
2891 .name
= "mcbsp3_fck",
2892 .ops
= &clkops_omap2_dflt_wait
,
2893 .init
= &omap2_init_clksel_parent
,
2894 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2895 .enable_bit
= OMAP3430_EN_MCBSP3_SHIFT
,
2896 .clksel_reg
= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1
),
2897 .clksel_mask
= OMAP2_MCBSP3_CLKS_MASK
,
2898 .clksel
= mcbsp_234_clksel
,
2899 .clkdm_name
= "per_clkdm",
2900 .recalc
= &omap2_clksel_recalc
,
2903 static struct clk mcbsp4_fck
= {
2904 .name
= "mcbsp4_fck",
2905 .ops
= &clkops_omap2_dflt_wait
,
2906 .init
= &omap2_init_clksel_parent
,
2907 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2908 .enable_bit
= OMAP3430_EN_MCBSP4_SHIFT
,
2909 .clksel_reg
= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1
),
2910 .clksel_mask
= OMAP2_MCBSP4_CLKS_MASK
,
2911 .clksel
= mcbsp_234_clksel
,
2912 .clkdm_name
= "per_clkdm",
2913 .recalc
= &omap2_clksel_recalc
,
2918 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2920 static const struct clksel_rate emu_src_sys_rates
[] = {
2921 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
2925 static const struct clksel_rate emu_src_core_rates
[] = {
2926 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
2930 static const struct clksel_rate emu_src_per_rates
[] = {
2931 { .div
= 1, .val
= 2, .flags
= RATE_IN_3XXX
},
2935 static const struct clksel_rate emu_src_mpu_rates
[] = {
2936 { .div
= 1, .val
= 3, .flags
= RATE_IN_3XXX
},
2940 static const struct clksel emu_src_clksel
[] = {
2941 { .parent
= &sys_ck
, .rates
= emu_src_sys_rates
},
2942 { .parent
= &emu_core_alwon_ck
, .rates
= emu_src_core_rates
},
2943 { .parent
= &emu_per_alwon_ck
, .rates
= emu_src_per_rates
},
2944 { .parent
= &emu_mpu_alwon_ck
, .rates
= emu_src_mpu_rates
},
2949 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2950 * to switch the source of some of the EMU clocks.
2951 * XXX Are there CLKEN bits for these EMU clks?
2953 static struct clk emu_src_ck
= {
2954 .name
= "emu_src_ck",
2955 .ops
= &clkops_null
,
2956 .init
= &omap2_init_clksel_parent
,
2957 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2958 .clksel_mask
= OMAP3430_MUX_CTRL_MASK
,
2959 .clksel
= emu_src_clksel
,
2960 .clkdm_name
= "emu_clkdm",
2961 .recalc
= &omap2_clksel_recalc
,
2964 static const struct clksel_rate pclk_emu_rates
[] = {
2965 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
2966 { .div
= 3, .val
= 3, .flags
= RATE_IN_3XXX
},
2967 { .div
= 4, .val
= 4, .flags
= RATE_IN_3XXX
},
2968 { .div
= 6, .val
= 6, .flags
= RATE_IN_3XXX
},
2972 static const struct clksel pclk_emu_clksel
[] = {
2973 { .parent
= &emu_src_ck
, .rates
= pclk_emu_rates
},
2977 static struct clk pclk_fck
= {
2979 .ops
= &clkops_null
,
2980 .init
= &omap2_init_clksel_parent
,
2981 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2982 .clksel_mask
= OMAP3430_CLKSEL_PCLK_MASK
,
2983 .clksel
= pclk_emu_clksel
,
2984 .clkdm_name
= "emu_clkdm",
2985 .recalc
= &omap2_clksel_recalc
,
2988 static const struct clksel_rate pclkx2_emu_rates
[] = {
2989 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
2990 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
2991 { .div
= 3, .val
= 3, .flags
= RATE_IN_3XXX
},
2995 static const struct clksel pclkx2_emu_clksel
[] = {
2996 { .parent
= &emu_src_ck
, .rates
= pclkx2_emu_rates
},
3000 static struct clk pclkx2_fck
= {
3001 .name
= "pclkx2_fck",
3002 .ops
= &clkops_null
,
3003 .init
= &omap2_init_clksel_parent
,
3004 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
3005 .clksel_mask
= OMAP3430_CLKSEL_PCLKX2_MASK
,
3006 .clksel
= pclkx2_emu_clksel
,
3007 .clkdm_name
= "emu_clkdm",
3008 .recalc
= &omap2_clksel_recalc
,
3011 static const struct clksel atclk_emu_clksel
[] = {
3012 { .parent
= &emu_src_ck
, .rates
= div2_rates
},
3016 static struct clk atclk_fck
= {
3017 .name
= "atclk_fck",
3018 .ops
= &clkops_null
,
3019 .init
= &omap2_init_clksel_parent
,
3020 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
3021 .clksel_mask
= OMAP3430_CLKSEL_ATCLK_MASK
,
3022 .clksel
= atclk_emu_clksel
,
3023 .clkdm_name
= "emu_clkdm",
3024 .recalc
= &omap2_clksel_recalc
,
3027 static struct clk traceclk_src_fck
= {
3028 .name
= "traceclk_src_fck",
3029 .ops
= &clkops_null
,
3030 .init
= &omap2_init_clksel_parent
,
3031 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
3032 .clksel_mask
= OMAP3430_TRACE_MUX_CTRL_MASK
,
3033 .clksel
= emu_src_clksel
,
3034 .clkdm_name
= "emu_clkdm",
3035 .recalc
= &omap2_clksel_recalc
,
3038 static const struct clksel_rate traceclk_rates
[] = {
3039 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
3040 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
3041 { .div
= 4, .val
= 4, .flags
= RATE_IN_3XXX
},
3045 static const struct clksel traceclk_clksel
[] = {
3046 { .parent
= &traceclk_src_fck
, .rates
= traceclk_rates
},
3050 static struct clk traceclk_fck
= {
3051 .name
= "traceclk_fck",
3052 .ops
= &clkops_null
,
3053 .init
= &omap2_init_clksel_parent
,
3054 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
3055 .clksel_mask
= OMAP3430_CLKSEL_TRACECLK_MASK
,
3056 .clksel
= traceclk_clksel
,
3057 .clkdm_name
= "emu_clkdm",
3058 .recalc
= &omap2_clksel_recalc
,
3063 /* SmartReflex fclk (VDD1) */
3064 static struct clk sr1_fck
= {
3066 .ops
= &clkops_omap2_dflt_wait
,
3068 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
3069 .enable_bit
= OMAP3430_EN_SR1_SHIFT
,
3070 .clkdm_name
= "wkup_clkdm",
3071 .recalc
= &followparent_recalc
,
3074 /* SmartReflex fclk (VDD2) */
3075 static struct clk sr2_fck
= {
3077 .ops
= &clkops_omap2_dflt_wait
,
3079 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
3080 .enable_bit
= OMAP3430_EN_SR2_SHIFT
,
3081 .clkdm_name
= "wkup_clkdm",
3082 .recalc
= &followparent_recalc
,
3085 static struct clk sr_l4_ick
= {
3086 .name
= "sr_l4_ick",
3087 .ops
= &clkops_null
, /* RMK: missing? */
3089 .clkdm_name
= "core_l4_clkdm",
3090 .recalc
= &followparent_recalc
,
3093 /* SECURE_32K_FCK clocks */
3095 static struct clk gpt12_fck
= {
3096 .name
= "gpt12_fck",
3097 .ops
= &clkops_null
,
3098 .parent
= &secure_32k_fck
,
3099 .clkdm_name
= "wkup_clkdm",
3100 .recalc
= &followparent_recalc
,
3103 static struct clk wdt1_fck
= {
3105 .ops
= &clkops_null
,
3106 .parent
= &secure_32k_fck
,
3107 .clkdm_name
= "wkup_clkdm",
3108 .recalc
= &followparent_recalc
,
3111 /* Clocks for AM35XX */
3112 static struct clk ipss_ick
= {
3114 .ops
= &clkops_am35xx_ipss_wait
,
3115 .parent
= &core_l3_ick
,
3116 .clkdm_name
= "core_l3_clkdm",
3117 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
3118 .enable_bit
= AM35XX_EN_IPSS_SHIFT
,
3119 .recalc
= &followparent_recalc
,
3122 static struct clk emac_ick
= {
3124 .ops
= &clkops_am35xx_ipss_module_wait
,
3125 .parent
= &ipss_ick
,
3126 .clkdm_name
= "core_l3_clkdm",
3127 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
3128 .enable_bit
= AM35XX_CPGMAC_VBUSP_CLK_SHIFT
,
3129 .recalc
= &followparent_recalc
,
3132 static struct clk rmii_ck
= {
3134 .ops
= &clkops_null
,
3138 static struct clk emac_fck
= {
3140 .ops
= &clkops_omap2_dflt
,
3142 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
3143 .enable_bit
= AM35XX_CPGMAC_FCLK_SHIFT
,
3144 .recalc
= &followparent_recalc
,
3147 static struct clk hsotgusb_ick_am35xx
= {
3148 .name
= "hsotgusb_ick",
3149 .ops
= &clkops_am35xx_ipss_module_wait
,
3150 .parent
= &ipss_ick
,
3151 .clkdm_name
= "core_l3_clkdm",
3152 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
3153 .enable_bit
= AM35XX_USBOTG_VBUSP_CLK_SHIFT
,
3154 .recalc
= &followparent_recalc
,
3157 static struct clk hsotgusb_fck_am35xx
= {
3158 .name
= "hsotgusb_fck",
3159 .ops
= &clkops_omap2_dflt
,
3161 .clkdm_name
= "core_l3_clkdm",
3162 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
3163 .enable_bit
= AM35XX_USBOTG_FCLK_SHIFT
,
3164 .recalc
= &followparent_recalc
,
3167 static struct clk hecc_ck
= {
3169 .ops
= &clkops_am35xx_ipss_module_wait
,
3171 .clkdm_name
= "core_l3_clkdm",
3172 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
3173 .enable_bit
= AM35XX_HECC_VBUSP_CLK_SHIFT
,
3174 .recalc
= &followparent_recalc
,
3177 static struct clk vpfe_ick
= {
3179 .ops
= &clkops_am35xx_ipss_module_wait
,
3180 .parent
= &ipss_ick
,
3181 .clkdm_name
= "core_l3_clkdm",
3182 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
3183 .enable_bit
= AM35XX_VPFE_VBUSP_CLK_SHIFT
,
3184 .recalc
= &followparent_recalc
,
3187 static struct clk pclk_ck
= {
3189 .ops
= &clkops_null
,
3193 static struct clk vpfe_fck
= {
3195 .ops
= &clkops_omap2_dflt
,
3197 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
3198 .enable_bit
= AM35XX_VPFE_FCLK_SHIFT
,
3199 .recalc
= &followparent_recalc
,
3203 * The UART1/2 functional clock acts as the functional
3204 * clock for UART4. No separate fclk control available.
3206 static struct clk uart4_ick_am35xx
= {
3207 .name
= "uart4_ick",
3208 .ops
= &clkops_omap2_iclk_dflt_wait
,
3209 .parent
= &core_l4_ick
,
3210 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
3211 .enable_bit
= AM35XX_EN_UART4_SHIFT
,
3212 .clkdm_name
= "core_l4_clkdm",
3213 .recalc
= &followparent_recalc
,
3216 static struct clk dummy_apb_pclk
= {
3218 .ops
= &clkops_null
,
3225 /* XXX At some point we should rename this file to clock3xxx_data.c */
3226 static struct omap_clk omap3xxx_clks
[] = {
3227 CLK(NULL
, "apb_pclk", &dummy_apb_pclk
, CK_3XXX
),
3228 CLK(NULL
, "omap_32k_fck", &omap_32k_fck
, CK_3XXX
),
3229 CLK(NULL
, "virt_12m_ck", &virt_12m_ck
, CK_3XXX
),
3230 CLK(NULL
, "virt_13m_ck", &virt_13m_ck
, CK_3XXX
),
3231 CLK(NULL
, "virt_16_8m_ck", &virt_16_8m_ck
, CK_3430ES2PLUS
| CK_AM35XX
| CK_36XX
),
3232 CLK(NULL
, "virt_19_2m_ck", &virt_19_2m_ck
, CK_3XXX
),
3233 CLK(NULL
, "virt_26m_ck", &virt_26m_ck
, CK_3XXX
),
3234 CLK(NULL
, "virt_38_4m_ck", &virt_38_4m_ck
, CK_3XXX
),
3235 CLK(NULL
, "osc_sys_ck", &osc_sys_ck
, CK_3XXX
),
3236 CLK(NULL
, "sys_ck", &sys_ck
, CK_3XXX
),
3237 CLK(NULL
, "sys_altclk", &sys_altclk
, CK_3XXX
),
3238 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks
, CK_3XXX
),
3239 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks
, CK_3XXX
),
3240 CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks
, CK_3XXX
),
3241 CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks
, CK_3XXX
),
3242 CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks
, CK_3XXX
),
3243 CLK(NULL
, "mcbsp_clks", &mcbsp_clks
, CK_3XXX
),
3244 CLK(NULL
, "sys_clkout1", &sys_clkout1
, CK_3XXX
),
3245 CLK(NULL
, "dpll1_ck", &dpll1_ck
, CK_3XXX
),
3246 CLK(NULL
, "dpll1_x2_ck", &dpll1_x2_ck
, CK_3XXX
),
3247 CLK(NULL
, "dpll1_x2m2_ck", &dpll1_x2m2_ck
, CK_3XXX
),
3248 CLK(NULL
, "dpll2_ck", &dpll2_ck
, CK_34XX
| CK_36XX
),
3249 CLK(NULL
, "dpll2_m2_ck", &dpll2_m2_ck
, CK_34XX
| CK_36XX
),
3250 CLK(NULL
, "dpll3_ck", &dpll3_ck
, CK_3XXX
),
3251 CLK(NULL
, "core_ck", &core_ck
, CK_3XXX
),
3252 CLK(NULL
, "dpll3_x2_ck", &dpll3_x2_ck
, CK_3XXX
),
3253 CLK(NULL
, "dpll3_m2_ck", &dpll3_m2_ck
, CK_3XXX
),
3254 CLK(NULL
, "dpll3_m2x2_ck", &dpll3_m2x2_ck
, CK_3XXX
),
3255 CLK(NULL
, "dpll3_m3_ck", &dpll3_m3_ck
, CK_3XXX
),
3256 CLK(NULL
, "dpll3_m3x2_ck", &dpll3_m3x2_ck
, CK_3XXX
),
3257 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck
, CK_3XXX
),
3258 CLK(NULL
, "dpll4_ck", &dpll4_ck
, CK_3XXX
),
3259 CLK(NULL
, "dpll4_x2_ck", &dpll4_x2_ck
, CK_3XXX
),
3260 CLK(NULL
, "omap_192m_alwon_fck", &omap_192m_alwon_fck
, CK_36XX
),
3261 CLK(NULL
, "omap_96m_alwon_fck", &omap_96m_alwon_fck
, CK_3XXX
),
3262 CLK(NULL
, "omap_96m_fck", &omap_96m_fck
, CK_3XXX
),
3263 CLK(NULL
, "cm_96m_fck", &cm_96m_fck
, CK_3XXX
),
3264 CLK(NULL
, "omap_54m_fck", &omap_54m_fck
, CK_3XXX
),
3265 CLK(NULL
, "omap_48m_fck", &omap_48m_fck
, CK_3XXX
),
3266 CLK(NULL
, "omap_12m_fck", &omap_12m_fck
, CK_3XXX
),
3267 CLK(NULL
, "dpll4_m2_ck", &dpll4_m2_ck
, CK_3XXX
),
3268 CLK(NULL
, "dpll4_m2x2_ck", &dpll4_m2x2_ck
, CK_3XXX
),
3269 CLK(NULL
, "dpll4_m3_ck", &dpll4_m3_ck
, CK_3XXX
),
3270 CLK(NULL
, "dpll4_m3x2_ck", &dpll4_m3x2_ck
, CK_3XXX
),
3271 CLK(NULL
, "dpll4_m4_ck", &dpll4_m4_ck
, CK_3XXX
),
3272 CLK(NULL
, "dpll4_m4x2_ck", &dpll4_m4x2_ck
, CK_3XXX
),
3273 CLK(NULL
, "dpll4_m5_ck", &dpll4_m5_ck
, CK_3XXX
),
3274 CLK(NULL
, "dpll4_m5x2_ck", &dpll4_m5x2_ck
, CK_3XXX
),
3275 CLK(NULL
, "dpll4_m6_ck", &dpll4_m6_ck
, CK_3XXX
),
3276 CLK(NULL
, "dpll4_m6x2_ck", &dpll4_m6x2_ck
, CK_3XXX
),
3277 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck
, CK_3XXX
),
3278 CLK(NULL
, "dpll5_ck", &dpll5_ck
, CK_3430ES2PLUS
| CK_AM35XX
| CK_36XX
),
3279 CLK(NULL
, "dpll5_m2_ck", &dpll5_m2_ck
, CK_3430ES2PLUS
| CK_AM35XX
| CK_36XX
),
3280 CLK(NULL
, "clkout2_src_ck", &clkout2_src_ck
, CK_3XXX
),
3281 CLK(NULL
, "sys_clkout2", &sys_clkout2
, CK_3XXX
),
3282 CLK(NULL
, "corex2_fck", &corex2_fck
, CK_3XXX
),
3283 CLK(NULL
, "dpll1_fck", &dpll1_fck
, CK_3XXX
),
3284 CLK(NULL
, "mpu_ck", &mpu_ck
, CK_3XXX
),
3285 CLK(NULL
, "arm_fck", &arm_fck
, CK_3XXX
),
3286 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck
, CK_3XXX
),
3287 CLK(NULL
, "dpll2_fck", &dpll2_fck
, CK_34XX
| CK_36XX
),
3288 CLK(NULL
, "iva2_ck", &iva2_ck
, CK_34XX
| CK_36XX
),
3289 CLK(NULL
, "l3_ick", &l3_ick
, CK_3XXX
),
3290 CLK(NULL
, "l4_ick", &l4_ick
, CK_3XXX
),
3291 CLK(NULL
, "rm_ick", &rm_ick
, CK_3XXX
),
3292 CLK(NULL
, "gfx_l3_ck", &gfx_l3_ck
, CK_3430ES1
),
3293 CLK(NULL
, "gfx_l3_fck", &gfx_l3_fck
, CK_3430ES1
),
3294 CLK(NULL
, "gfx_l3_ick", &gfx_l3_ick
, CK_3430ES1
),
3295 CLK(NULL
, "gfx_cg1_ck", &gfx_cg1_ck
, CK_3430ES1
),
3296 CLK(NULL
, "gfx_cg2_ck", &gfx_cg2_ck
, CK_3430ES1
),
3297 CLK(NULL
, "sgx_fck", &sgx_fck
, CK_3430ES2PLUS
| CK_AM35XX
| CK_36XX
),
3298 CLK(NULL
, "sgx_ick", &sgx_ick
, CK_3430ES2PLUS
| CK_AM35XX
| CK_36XX
),
3299 CLK(NULL
, "d2d_26m_fck", &d2d_26m_fck
, CK_3430ES1
),
3300 CLK(NULL
, "modem_fck", &modem_fck
, CK_34XX
| CK_36XX
),
3301 CLK(NULL
, "sad2d_ick", &sad2d_ick
, CK_34XX
| CK_36XX
),
3302 CLK(NULL
, "mad2d_ick", &mad2d_ick
, CK_34XX
| CK_36XX
),
3303 CLK(NULL
, "gpt10_fck", &gpt10_fck
, CK_3XXX
),
3304 CLK(NULL
, "gpt11_fck", &gpt11_fck
, CK_3XXX
),
3305 CLK(NULL
, "cpefuse_fck", &cpefuse_fck
, CK_3430ES2PLUS
| CK_AM35XX
| CK_36XX
),
3306 CLK(NULL
, "ts_fck", &ts_fck
, CK_3430ES2PLUS
| CK_AM35XX
| CK_36XX
),
3307 CLK(NULL
, "usbtll_fck", &usbtll_fck
, CK_3430ES2PLUS
| CK_AM35XX
| CK_36XX
),
3308 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck
, CK_3430ES2PLUS
| CK_AM35XX
| CK_36XX
),
3309 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck
, CK_3XXX
),
3310 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck
, CK_3XXX
),
3311 CLK(NULL
, "core_96m_fck", &core_96m_fck
, CK_3XXX
),
3312 CLK(NULL
, "mmchs3_fck", &mmchs3_fck
, CK_3430ES2PLUS
| CK_AM35XX
| CK_36XX
),
3313 CLK(NULL
, "mmchs2_fck", &mmchs2_fck
, CK_3XXX
),
3314 CLK(NULL
, "mspro_fck", &mspro_fck
, CK_34XX
| CK_36XX
),
3315 CLK(NULL
, "mmchs1_fck", &mmchs1_fck
, CK_3XXX
),
3316 CLK(NULL
, "i2c3_fck", &i2c3_fck
, CK_3XXX
),
3317 CLK(NULL
, "i2c2_fck", &i2c2_fck
, CK_3XXX
),
3318 CLK(NULL
, "i2c1_fck", &i2c1_fck
, CK_3XXX
),
3319 CLK(NULL
, "mcbsp5_fck", &mcbsp5_fck
, CK_3XXX
),
3320 CLK(NULL
, "mcbsp1_fck", &mcbsp1_fck
, CK_3XXX
),
3321 CLK(NULL
, "core_48m_fck", &core_48m_fck
, CK_3XXX
),
3322 CLK(NULL
, "mcspi4_fck", &mcspi4_fck
, CK_3XXX
),
3323 CLK(NULL
, "mcspi3_fck", &mcspi3_fck
, CK_3XXX
),
3324 CLK(NULL
, "mcspi2_fck", &mcspi2_fck
, CK_3XXX
),
3325 CLK(NULL
, "mcspi1_fck", &mcspi1_fck
, CK_3XXX
),
3326 CLK(NULL
, "uart2_fck", &uart2_fck
, CK_3XXX
),
3327 CLK(NULL
, "uart1_fck", &uart1_fck
, CK_3XXX
),
3328 CLK(NULL
, "fshostusb_fck", &fshostusb_fck
, CK_3430ES1
),
3329 CLK(NULL
, "core_12m_fck", &core_12m_fck
, CK_3XXX
),
3330 CLK("omap_hdq.0", "fck", &hdq_fck
, CK_3XXX
),
3331 CLK(NULL
, "ssi_ssr_fck", &ssi_ssr_fck_3430es1
, CK_3430ES1
),
3332 CLK(NULL
, "ssi_ssr_fck", &ssi_ssr_fck_3430es2
, CK_3430ES2PLUS
| CK_36XX
),
3333 CLK(NULL
, "ssi_sst_fck", &ssi_sst_fck_3430es1
, CK_3430ES1
),
3334 CLK(NULL
, "ssi_sst_fck", &ssi_sst_fck_3430es2
, CK_3430ES2PLUS
| CK_36XX
),
3335 CLK(NULL
, "core_l3_ick", &core_l3_ick
, CK_3XXX
),
3336 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1
, CK_3430ES1
),
3337 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2
, CK_3430ES2PLUS
| CK_36XX
),
3338 CLK(NULL
, "sdrc_ick", &sdrc_ick
, CK_3XXX
),
3339 CLK(NULL
, "gpmc_fck", &gpmc_fck
, CK_3XXX
),
3340 CLK(NULL
, "security_l3_ick", &security_l3_ick
, CK_34XX
| CK_36XX
),
3341 CLK(NULL
, "pka_ick", &pka_ick
, CK_34XX
| CK_36XX
),
3342 CLK(NULL
, "core_l4_ick", &core_l4_ick
, CK_3XXX
),
3343 CLK(NULL
, "usbtll_ick", &usbtll_ick
, CK_3430ES2PLUS
| CK_AM35XX
| CK_36XX
),
3344 CLK("usbhs_omap", "usbtll_ick", &usbtll_ick
, CK_3430ES2PLUS
| CK_AM35XX
| CK_36XX
),
3345 CLK("omap_hsmmc.2", "ick", &mmchs3_ick
, CK_3430ES2PLUS
| CK_AM35XX
| CK_36XX
),
3346 CLK(NULL
, "icr_ick", &icr_ick
, CK_34XX
| CK_36XX
),
3347 CLK("omap-aes", "ick", &aes2_ick
, CK_34XX
| CK_36XX
),
3348 CLK("omap-sham", "ick", &sha12_ick
, CK_34XX
| CK_36XX
),
3349 CLK(NULL
, "des2_ick", &des2_ick
, CK_34XX
| CK_36XX
),
3350 CLK("omap_hsmmc.1", "ick", &mmchs2_ick
, CK_3XXX
),
3351 CLK("omap_hsmmc.0", "ick", &mmchs1_ick
, CK_3XXX
),
3352 CLK(NULL
, "mspro_ick", &mspro_ick
, CK_34XX
| CK_36XX
),
3353 CLK("omap_hdq.0", "ick", &hdq_ick
, CK_3XXX
),
3354 CLK("omap2_mcspi.4", "ick", &mcspi4_ick
, CK_3XXX
),
3355 CLK("omap2_mcspi.3", "ick", &mcspi3_ick
, CK_3XXX
),
3356 CLK("omap2_mcspi.2", "ick", &mcspi2_ick
, CK_3XXX
),
3357 CLK("omap2_mcspi.1", "ick", &mcspi1_ick
, CK_3XXX
),
3358 CLK("omap_i2c.3", "ick", &i2c3_ick
, CK_3XXX
),
3359 CLK("omap_i2c.2", "ick", &i2c2_ick
, CK_3XXX
),
3360 CLK("omap_i2c.1", "ick", &i2c1_ick
, CK_3XXX
),
3361 CLK(NULL
, "uart2_ick", &uart2_ick
, CK_3XXX
),
3362 CLK(NULL
, "uart1_ick", &uart1_ick
, CK_3XXX
),
3363 CLK(NULL
, "gpt11_ick", &gpt11_ick
, CK_3XXX
),
3364 CLK(NULL
, "gpt10_ick", &gpt10_ick
, CK_3XXX
),
3365 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick
, CK_3XXX
),
3366 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick
, CK_3XXX
),
3367 CLK(NULL
, "fac_ick", &fac_ick
, CK_3430ES1
),
3368 CLK(NULL
, "mailboxes_ick", &mailboxes_ick
, CK_34XX
| CK_36XX
),
3369 CLK(NULL
, "omapctrl_ick", &omapctrl_ick
, CK_3XXX
),
3370 CLK(NULL
, "ssi_l4_ick", &ssi_l4_ick
, CK_34XX
| CK_36XX
),
3371 CLK(NULL
, "ssi_ick", &ssi_ick_3430es1
, CK_3430ES1
),
3372 CLK(NULL
, "ssi_ick", &ssi_ick_3430es2
, CK_3430ES2PLUS
| CK_36XX
),
3373 CLK(NULL
, "usb_l4_ick", &usb_l4_ick
, CK_3430ES1
),
3374 CLK(NULL
, "security_l4_ick2", &security_l4_ick2
, CK_34XX
| CK_36XX
),
3375 CLK(NULL
, "aes1_ick", &aes1_ick
, CK_34XX
| CK_36XX
),
3376 CLK("omap_rng", "ick", &rng_ick
, CK_34XX
| CK_36XX
),
3377 CLK(NULL
, "sha11_ick", &sha11_ick
, CK_34XX
| CK_36XX
),
3378 CLK(NULL
, "des1_ick", &des1_ick
, CK_34XX
| CK_36XX
),
3379 CLK(NULL
, "dss1_alwon_fck", &dss1_alwon_fck_3430es1
, CK_3430ES1
),
3380 CLK(NULL
, "dss1_alwon_fck", &dss1_alwon_fck_3430es2
, CK_3430ES2PLUS
| CK_AM35XX
| CK_36XX
),
3381 CLK(NULL
, "dss_tv_fck", &dss_tv_fck
, CK_3XXX
),
3382 CLK(NULL
, "dss_96m_fck", &dss_96m_fck
, CK_3XXX
),
3383 CLK(NULL
, "dss2_alwon_fck", &dss2_alwon_fck
, CK_3XXX
),
3384 CLK("omapdss_dss", "ick", &dss_ick_3430es1
, CK_3430ES1
),
3385 CLK("omapdss_dss", "ick", &dss_ick_3430es2
, CK_3430ES2PLUS
| CK_AM35XX
| CK_36XX
),
3386 CLK(NULL
, "cam_mclk", &cam_mclk
, CK_34XX
| CK_36XX
),
3387 CLK(NULL
, "cam_ick", &cam_ick
, CK_34XX
| CK_36XX
),
3388 CLK(NULL
, "csi2_96m_fck", &csi2_96m_fck
, CK_34XX
| CK_36XX
),
3389 CLK(NULL
, "usbhost_120m_fck", &usbhost_120m_fck
, CK_3430ES2PLUS
| CK_AM35XX
| CK_36XX
),
3390 CLK(NULL
, "usbhost_48m_fck", &usbhost_48m_fck
, CK_3430ES2PLUS
| CK_AM35XX
| CK_36XX
),
3391 CLK(NULL
, "usbhost_ick", &usbhost_ick
, CK_3430ES2PLUS
| CK_AM35XX
| CK_36XX
),
3392 CLK("usbhs_omap", "usbhost_ick", &usbhost_ick
, CK_3430ES2PLUS
| CK_AM35XX
| CK_36XX
),
3393 CLK("usbhs_omap", "utmi_p1_gfclk", &dummy_ck
, CK_3XXX
),
3394 CLK("usbhs_omap", "utmi_p2_gfclk", &dummy_ck
, CK_3XXX
),
3395 CLK("usbhs_omap", "xclk60mhsp1_ck", &dummy_ck
, CK_3XXX
),
3396 CLK("usbhs_omap", "xclk60mhsp2_ck", &dummy_ck
, CK_3XXX
),
3397 CLK("usbhs_omap", "usb_host_hs_utmi_p1_clk", &dummy_ck
, CK_3XXX
),
3398 CLK("usbhs_omap", "usb_host_hs_utmi_p2_clk", &dummy_ck
, CK_3XXX
),
3399 CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck
, CK_3XXX
),
3400 CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck
, CK_3XXX
),
3401 CLK("usbhs_omap", "init_60m_fclk", &dummy_ck
, CK_3XXX
),
3402 CLK(NULL
, "usim_fck", &usim_fck
, CK_3430ES2PLUS
| CK_36XX
),
3403 CLK(NULL
, "gpt1_fck", &gpt1_fck
, CK_3XXX
),
3404 CLK(NULL
, "wkup_32k_fck", &wkup_32k_fck
, CK_3XXX
),
3405 CLK(NULL
, "gpio1_dbck", &gpio1_dbck
, CK_3XXX
),
3406 CLK(NULL
, "wdt2_fck", &wdt2_fck
, CK_3XXX
),
3407 CLK(NULL
, "wkup_l4_ick", &wkup_l4_ick
, CK_34XX
| CK_36XX
),
3408 CLK(NULL
, "usim_ick", &usim_ick
, CK_3430ES2PLUS
| CK_36XX
),
3409 CLK("omap_wdt", "ick", &wdt2_ick
, CK_3XXX
),
3410 CLK(NULL
, "wdt1_ick", &wdt1_ick
, CK_3XXX
),
3411 CLK(NULL
, "gpio1_ick", &gpio1_ick
, CK_3XXX
),
3412 CLK(NULL
, "omap_32ksync_ick", &omap_32ksync_ick
, CK_3XXX
),
3413 CLK(NULL
, "gpt12_ick", &gpt12_ick
, CK_3XXX
),
3414 CLK(NULL
, "gpt1_ick", &gpt1_ick
, CK_3XXX
),
3415 CLK("omap-mcbsp.2", "prcm_fck", &per_96m_fck
, CK_3XXX
),
3416 CLK("omap-mcbsp.3", "prcm_fck", &per_96m_fck
, CK_3XXX
),
3417 CLK("omap-mcbsp.4", "prcm_fck", &per_96m_fck
, CK_3XXX
),
3418 CLK(NULL
, "per_96m_fck", &per_96m_fck
, CK_3XXX
),
3419 CLK(NULL
, "per_48m_fck", &per_48m_fck
, CK_3XXX
),
3420 CLK(NULL
, "uart3_fck", &uart3_fck
, CK_3XXX
),
3421 CLK(NULL
, "uart4_fck", &uart4_fck
, CK_36XX
),
3422 CLK(NULL
, "uart4_fck", &uart4_fck_am35xx
, CK_AM35XX
),
3423 CLK(NULL
, "gpt2_fck", &gpt2_fck
, CK_3XXX
),
3424 CLK(NULL
, "gpt3_fck", &gpt3_fck
, CK_3XXX
),
3425 CLK(NULL
, "gpt4_fck", &gpt4_fck
, CK_3XXX
),
3426 CLK(NULL
, "gpt5_fck", &gpt5_fck
, CK_3XXX
),
3427 CLK(NULL
, "gpt6_fck", &gpt6_fck
, CK_3XXX
),
3428 CLK(NULL
, "gpt7_fck", &gpt7_fck
, CK_3XXX
),
3429 CLK(NULL
, "gpt8_fck", &gpt8_fck
, CK_3XXX
),
3430 CLK(NULL
, "gpt9_fck", &gpt9_fck
, CK_3XXX
),
3431 CLK(NULL
, "per_32k_alwon_fck", &per_32k_alwon_fck
, CK_3XXX
),
3432 CLK(NULL
, "gpio6_dbck", &gpio6_dbck
, CK_3XXX
),
3433 CLK(NULL
, "gpio5_dbck", &gpio5_dbck
, CK_3XXX
),
3434 CLK(NULL
, "gpio4_dbck", &gpio4_dbck
, CK_3XXX
),
3435 CLK(NULL
, "gpio3_dbck", &gpio3_dbck
, CK_3XXX
),
3436 CLK(NULL
, "gpio2_dbck", &gpio2_dbck
, CK_3XXX
),
3437 CLK(NULL
, "wdt3_fck", &wdt3_fck
, CK_3XXX
),
3438 CLK(NULL
, "per_l4_ick", &per_l4_ick
, CK_3XXX
),
3439 CLK(NULL
, "gpio6_ick", &gpio6_ick
, CK_3XXX
),
3440 CLK(NULL
, "gpio5_ick", &gpio5_ick
, CK_3XXX
),
3441 CLK(NULL
, "gpio4_ick", &gpio4_ick
, CK_3XXX
),
3442 CLK(NULL
, "gpio3_ick", &gpio3_ick
, CK_3XXX
),
3443 CLK(NULL
, "gpio2_ick", &gpio2_ick
, CK_3XXX
),
3444 CLK(NULL
, "wdt3_ick", &wdt3_ick
, CK_3XXX
),
3445 CLK(NULL
, "uart3_ick", &uart3_ick
, CK_3XXX
),
3446 CLK(NULL
, "uart4_ick", &uart4_ick
, CK_36XX
),
3447 CLK(NULL
, "gpt9_ick", &gpt9_ick
, CK_3XXX
),
3448 CLK(NULL
, "gpt8_ick", &gpt8_ick
, CK_3XXX
),
3449 CLK(NULL
, "gpt7_ick", &gpt7_ick
, CK_3XXX
),
3450 CLK(NULL
, "gpt6_ick", &gpt6_ick
, CK_3XXX
),
3451 CLK(NULL
, "gpt5_ick", &gpt5_ick
, CK_3XXX
),
3452 CLK(NULL
, "gpt4_ick", &gpt4_ick
, CK_3XXX
),
3453 CLK(NULL
, "gpt3_ick", &gpt3_ick
, CK_3XXX
),
3454 CLK(NULL
, "gpt2_ick", &gpt2_ick
, CK_3XXX
),
3455 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick
, CK_3XXX
),
3456 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick
, CK_3XXX
),
3457 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick
, CK_3XXX
),
3458 CLK(NULL
, "mcbsp2_fck", &mcbsp2_fck
, CK_3XXX
),
3459 CLK(NULL
, "mcbsp3_fck", &mcbsp3_fck
, CK_3XXX
),
3460 CLK(NULL
, "mcbsp4_fck", &mcbsp4_fck
, CK_3XXX
),
3461 CLK("etb", "emu_src_ck", &emu_src_ck
, CK_3XXX
),
3462 CLK(NULL
, "pclk_fck", &pclk_fck
, CK_3XXX
),
3463 CLK(NULL
, "pclkx2_fck", &pclkx2_fck
, CK_3XXX
),
3464 CLK(NULL
, "atclk_fck", &atclk_fck
, CK_3XXX
),
3465 CLK(NULL
, "traceclk_src_fck", &traceclk_src_fck
, CK_3XXX
),
3466 CLK(NULL
, "traceclk_fck", &traceclk_fck
, CK_3XXX
),
3467 CLK(NULL
, "sr1_fck", &sr1_fck
, CK_34XX
| CK_36XX
),
3468 CLK(NULL
, "sr2_fck", &sr2_fck
, CK_34XX
| CK_36XX
),
3469 CLK(NULL
, "sr_l4_ick", &sr_l4_ick
, CK_34XX
| CK_36XX
),
3470 CLK(NULL
, "secure_32k_fck", &secure_32k_fck
, CK_3XXX
),
3471 CLK(NULL
, "gpt12_fck", &gpt12_fck
, CK_3XXX
),
3472 CLK(NULL
, "wdt1_fck", &wdt1_fck
, CK_3XXX
),
3473 CLK(NULL
, "ipss_ick", &ipss_ick
, CK_AM35XX
),
3474 CLK(NULL
, "rmii_ck", &rmii_ck
, CK_AM35XX
),
3475 CLK(NULL
, "pclk_ck", &pclk_ck
, CK_AM35XX
),
3476 CLK("davinci_emac", NULL
, &emac_ick
, CK_AM35XX
),
3477 CLK("davinci_mdio.0", NULL
, &emac_fck
, CK_AM35XX
),
3478 CLK("vpfe-capture", "master", &vpfe_ick
, CK_AM35XX
),
3479 CLK("vpfe-capture", "slave", &vpfe_fck
, CK_AM35XX
),
3480 CLK("musb-am35x", "ick", &hsotgusb_ick_am35xx
, CK_AM35XX
),
3481 CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx
, CK_AM35XX
),
3482 CLK(NULL
, "hecc_ck", &hecc_ck
, CK_AM35XX
),
3483 CLK(NULL
, "uart4_ick", &uart4_ick_am35xx
, CK_AM35XX
),
3484 CLK("omap_timer.1", "32k_ck", &omap_32k_fck
, CK_3XXX
),
3485 CLK("omap_timer.2", "32k_ck", &omap_32k_fck
, CK_3XXX
),
3486 CLK("omap_timer.3", "32k_ck", &omap_32k_fck
, CK_3XXX
),
3487 CLK("omap_timer.4", "32k_ck", &omap_32k_fck
, CK_3XXX
),
3488 CLK("omap_timer.5", "32k_ck", &omap_32k_fck
, CK_3XXX
),
3489 CLK("omap_timer.6", "32k_ck", &omap_32k_fck
, CK_3XXX
),
3490 CLK("omap_timer.7", "32k_ck", &omap_32k_fck
, CK_3XXX
),
3491 CLK("omap_timer.8", "32k_ck", &omap_32k_fck
, CK_3XXX
),
3492 CLK("omap_timer.9", "32k_ck", &omap_32k_fck
, CK_3XXX
),
3493 CLK("omap_timer.10", "32k_ck", &omap_32k_fck
, CK_3XXX
),
3494 CLK("omap_timer.11", "32k_ck", &omap_32k_fck
, CK_3XXX
),
3495 CLK("omap_timer.12", "32k_ck", &omap_32k_fck
, CK_3XXX
),
3496 CLK("omap_timer.1", "sys_ck", &sys_ck
, CK_3XXX
),
3497 CLK("omap_timer.2", "sys_ck", &sys_ck
, CK_3XXX
),
3498 CLK("omap_timer.3", "sys_ck", &sys_ck
, CK_3XXX
),
3499 CLK("omap_timer.4", "sys_ck", &sys_ck
, CK_3XXX
),
3500 CLK("omap_timer.5", "sys_ck", &sys_ck
, CK_3XXX
),
3501 CLK("omap_timer.6", "sys_ck", &sys_ck
, CK_3XXX
),
3502 CLK("omap_timer.7", "sys_ck", &sys_ck
, CK_3XXX
),
3503 CLK("omap_timer.8", "sys_ck", &sys_ck
, CK_3XXX
),
3504 CLK("omap_timer.9", "sys_ck", &sys_ck
, CK_3XXX
),
3505 CLK("omap_timer.10", "sys_ck", &sys_ck
, CK_3XXX
),
3506 CLK("omap_timer.11", "sys_ck", &sys_ck
, CK_3XXX
),
3507 CLK("omap_timer.12", "sys_ck", &sys_ck
, CK_3XXX
),
3511 int __init
omap3xxx_clk_init(void)
3516 if (cpu_is_omap3517()) {
3517 cpu_mask
= RATE_IN_34XX
;
3518 cpu_clkflg
= CK_AM35XX
;
3519 } else if (cpu_is_omap3630()) {
3520 cpu_mask
= (RATE_IN_34XX
| RATE_IN_36XX
);
3521 cpu_clkflg
= CK_36XX
;
3522 } else if (cpu_is_ti816x()) {
3523 cpu_mask
= RATE_IN_TI816X
;
3524 cpu_clkflg
= CK_TI816X
;
3525 } else if (cpu_is_am33xx()) {
3526 cpu_mask
= RATE_IN_AM33XX
;
3527 } else if (cpu_is_ti814x()) {
3528 cpu_mask
= RATE_IN_TI814X
;
3529 } else if (cpu_is_omap34xx()) {
3530 if (omap_rev() == OMAP3430_REV_ES1_0
) {
3531 cpu_mask
= RATE_IN_3430ES1
;
3532 cpu_clkflg
= CK_3430ES1
;
3535 * Assume that anything that we haven't matched yet
3536 * has 3430ES2-type clocks.
3538 cpu_mask
= RATE_IN_3430ES2PLUS
;
3539 cpu_clkflg
= CK_3430ES2PLUS
;
3542 WARN(1, "clock: could not identify OMAP3 variant\n");
3545 if (omap3_has_192mhz_clk())
3546 omap_96m_alwon_fck
= omap_96m_alwon_fck_3630
;
3548 if (cpu_is_omap3630()) {
3550 * XXX This type of dynamic rewriting of the clock tree is
3551 * deprecated and should be revised soon.
3553 * For 3630: override clkops_omap2_dflt_wait for the
3554 * clocks affected from PWRDN reset Limitation
3557 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore
;
3559 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore
;
3561 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore
;
3563 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore
;
3565 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore
;
3567 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore
;
3571 * XXX This type of dynamic rewriting of the clock tree is
3572 * deprecated and should be revised soon.
3574 if (cpu_is_omap3630())
3575 dpll4_dd
= dpll4_dd_3630
;
3577 dpll4_dd
= dpll4_dd_34xx
;
3579 clk_init(&omap2_clk_functions
);
3581 for (c
= omap3xxx_clks
; c
< omap3xxx_clks
+ ARRAY_SIZE(omap3xxx_clks
);
3583 clk_preinit(c
->lk
.clk
);
3585 for (c
= omap3xxx_clks
; c
< omap3xxx_clks
+ ARRAY_SIZE(omap3xxx_clks
);
3587 if (c
->cpu
& cpu_clkflg
) {
3589 clk_register(c
->lk
.clk
);
3590 omap2_init_clk_clkdm(c
->lk
.clk
);
3593 /* Disable autoidle on all clocks; let the PM code enable it later */
3594 omap_clk_disable_autoidle_all();
3596 recalculate_root_clocks();
3598 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3599 (osc_sys_ck
.rate
/ 1000000), (osc_sys_ck
.rate
/ 100000) % 10,
3600 (core_ck
.rate
/ 1000000), (arm_fck
.rate
/ 1000000));
3603 * Only enable those clocks we will need, let the drivers
3604 * enable other clocks as necessary
3606 clk_enable_init_clocks();
3609 * Lock DPLL5 -- here only until other device init code can
3612 if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0
))
3613 omap3_clk_lock_dpll5();
3615 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3616 sdrc_ick_p
= clk_get(NULL
, "sdrc_ick");
3617 arm_fck_p
= clk_get(NULL
, "arm_fck");