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x86: Move call to print_modules() out of show_regs()
[deliverable/linux.git] / arch / arm / mach-omap2 / clock44xx_data.c
1 /*
2 * OMAP4 Clock data
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 * XXX Some of the ES1 clocks have been removed/changed; once support
22 * is added for discriminating clocks by ES level, these should be added back
23 * in.
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/list.h>
28 #include <linux/clk.h>
29 #include <linux/io.h>
30
31 #include <plat/hardware.h>
32 #include <plat/clkdev_omap.h>
33
34 #include "iomap.h"
35 #include "clock.h"
36 #include "clock44xx.h"
37 #include "cm1_44xx.h"
38 #include "cm2_44xx.h"
39 #include "cm-regbits-44xx.h"
40 #include "prm44xx.h"
41 #include "prm-regbits-44xx.h"
42 #include "control.h"
43 #include "scrm44xx.h"
44
45 /* OMAP4 modulemode control */
46 #define OMAP4430_MODULEMODE_HWCTRL 0
47 #define OMAP4430_MODULEMODE_SWCTRL 1
48
49 /* Root clocks */
50
51 static struct clk extalt_clkin_ck = {
52 .name = "extalt_clkin_ck",
53 .rate = 59000000,
54 .ops = &clkops_null,
55 };
56
57 static struct clk pad_clks_ck = {
58 .name = "pad_clks_ck",
59 .rate = 12000000,
60 .ops = &clkops_omap2_dflt,
61 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
62 .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
63 };
64
65 static struct clk pad_slimbus_core_clks_ck = {
66 .name = "pad_slimbus_core_clks_ck",
67 .rate = 12000000,
68 .ops = &clkops_null,
69 };
70
71 static struct clk secure_32k_clk_src_ck = {
72 .name = "secure_32k_clk_src_ck",
73 .rate = 32768,
74 .ops = &clkops_null,
75 };
76
77 static struct clk slimbus_clk = {
78 .name = "slimbus_clk",
79 .rate = 12000000,
80 .ops = &clkops_omap2_dflt,
81 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
82 .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
83 };
84
85 static struct clk sys_32k_ck = {
86 .name = "sys_32k_ck",
87 .rate = 32768,
88 .ops = &clkops_null,
89 };
90
91 static struct clk virt_12000000_ck = {
92 .name = "virt_12000000_ck",
93 .ops = &clkops_null,
94 .rate = 12000000,
95 };
96
97 static struct clk virt_13000000_ck = {
98 .name = "virt_13000000_ck",
99 .ops = &clkops_null,
100 .rate = 13000000,
101 };
102
103 static struct clk virt_16800000_ck = {
104 .name = "virt_16800000_ck",
105 .ops = &clkops_null,
106 .rate = 16800000,
107 };
108
109 static struct clk virt_19200000_ck = {
110 .name = "virt_19200000_ck",
111 .ops = &clkops_null,
112 .rate = 19200000,
113 };
114
115 static struct clk virt_26000000_ck = {
116 .name = "virt_26000000_ck",
117 .ops = &clkops_null,
118 .rate = 26000000,
119 };
120
121 static struct clk virt_27000000_ck = {
122 .name = "virt_27000000_ck",
123 .ops = &clkops_null,
124 .rate = 27000000,
125 };
126
127 static struct clk virt_38400000_ck = {
128 .name = "virt_38400000_ck",
129 .ops = &clkops_null,
130 .rate = 38400000,
131 };
132
133 static const struct clksel_rate div_1_0_rates[] = {
134 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
135 { .div = 0 },
136 };
137
138 static const struct clksel_rate div_1_1_rates[] = {
139 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
140 { .div = 0 },
141 };
142
143 static const struct clksel_rate div_1_2_rates[] = {
144 { .div = 1, .val = 2, .flags = RATE_IN_4430 },
145 { .div = 0 },
146 };
147
148 static const struct clksel_rate div_1_3_rates[] = {
149 { .div = 1, .val = 3, .flags = RATE_IN_4430 },
150 { .div = 0 },
151 };
152
153 static const struct clksel_rate div_1_4_rates[] = {
154 { .div = 1, .val = 4, .flags = RATE_IN_4430 },
155 { .div = 0 },
156 };
157
158 static const struct clksel_rate div_1_5_rates[] = {
159 { .div = 1, .val = 5, .flags = RATE_IN_4430 },
160 { .div = 0 },
161 };
162
163 static const struct clksel_rate div_1_6_rates[] = {
164 { .div = 1, .val = 6, .flags = RATE_IN_4430 },
165 { .div = 0 },
166 };
167
168 static const struct clksel_rate div_1_7_rates[] = {
169 { .div = 1, .val = 7, .flags = RATE_IN_4430 },
170 { .div = 0 },
171 };
172
173 static const struct clksel sys_clkin_sel[] = {
174 { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
175 { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
176 { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
177 { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
178 { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
179 { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
180 { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
181 { .parent = NULL },
182 };
183
184 static struct clk sys_clkin_ck = {
185 .name = "sys_clkin_ck",
186 .rate = 38400000,
187 .clksel = sys_clkin_sel,
188 .init = &omap2_init_clksel_parent,
189 .clksel_reg = OMAP4430_CM_SYS_CLKSEL,
190 .clksel_mask = OMAP4430_SYS_CLKSEL_MASK,
191 .ops = &clkops_null,
192 .recalc = &omap2_clksel_recalc,
193 };
194
195 static struct clk tie_low_clock_ck = {
196 .name = "tie_low_clock_ck",
197 .rate = 0,
198 .ops = &clkops_null,
199 };
200
201 static struct clk utmi_phy_clkout_ck = {
202 .name = "utmi_phy_clkout_ck",
203 .rate = 60000000,
204 .ops = &clkops_null,
205 };
206
207 static struct clk xclk60mhsp1_ck = {
208 .name = "xclk60mhsp1_ck",
209 .rate = 60000000,
210 .ops = &clkops_null,
211 };
212
213 static struct clk xclk60mhsp2_ck = {
214 .name = "xclk60mhsp2_ck",
215 .rate = 60000000,
216 .ops = &clkops_null,
217 };
218
219 static struct clk xclk60motg_ck = {
220 .name = "xclk60motg_ck",
221 .rate = 60000000,
222 .ops = &clkops_null,
223 };
224
225 /* Module clocks and DPLL outputs */
226
227 static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
228 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
229 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
230 { .parent = NULL },
231 };
232
233 static struct clk abe_dpll_bypass_clk_mux_ck = {
234 .name = "abe_dpll_bypass_clk_mux_ck",
235 .parent = &sys_clkin_ck,
236 .ops = &clkops_null,
237 .recalc = &followparent_recalc,
238 };
239
240 static struct clk abe_dpll_refclk_mux_ck = {
241 .name = "abe_dpll_refclk_mux_ck",
242 .parent = &sys_clkin_ck,
243 .clksel = abe_dpll_bypass_clk_mux_sel,
244 .init = &omap2_init_clksel_parent,
245 .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
246 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
247 .ops = &clkops_null,
248 .recalc = &omap2_clksel_recalc,
249 };
250
251 /* DPLL_ABE */
252 static struct dpll_data dpll_abe_dd = {
253 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
254 .clk_bypass = &abe_dpll_bypass_clk_mux_ck,
255 .clk_ref = &abe_dpll_refclk_mux_ck,
256 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
257 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
258 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
259 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE,
260 .mult_mask = OMAP4430_DPLL_MULT_MASK,
261 .div1_mask = OMAP4430_DPLL_DIV_MASK,
262 .enable_mask = OMAP4430_DPLL_EN_MASK,
263 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
264 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
265 .max_multiplier = 2047,
266 .max_divider = 128,
267 .min_divider = 1,
268 };
269
270
271 static struct clk dpll_abe_ck = {
272 .name = "dpll_abe_ck",
273 .parent = &abe_dpll_refclk_mux_ck,
274 .dpll_data = &dpll_abe_dd,
275 .init = &omap2_init_dpll_parent,
276 .ops = &clkops_omap3_noncore_dpll_ops,
277 .recalc = &omap4_dpll_regm4xen_recalc,
278 .round_rate = &omap4_dpll_regm4xen_round_rate,
279 .set_rate = &omap3_noncore_dpll_set_rate,
280 };
281
282 static struct clk dpll_abe_x2_ck = {
283 .name = "dpll_abe_x2_ck",
284 .parent = &dpll_abe_ck,
285 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
286 .flags = CLOCK_CLKOUTX2,
287 .ops = &clkops_omap4_dpllmx_ops,
288 .recalc = &omap3_clkoutx2_recalc,
289 };
290
291 static const struct clksel_rate div31_1to31_rates[] = {
292 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
293 { .div = 2, .val = 2, .flags = RATE_IN_4430 },
294 { .div = 3, .val = 3, .flags = RATE_IN_4430 },
295 { .div = 4, .val = 4, .flags = RATE_IN_4430 },
296 { .div = 5, .val = 5, .flags = RATE_IN_4430 },
297 { .div = 6, .val = 6, .flags = RATE_IN_4430 },
298 { .div = 7, .val = 7, .flags = RATE_IN_4430 },
299 { .div = 8, .val = 8, .flags = RATE_IN_4430 },
300 { .div = 9, .val = 9, .flags = RATE_IN_4430 },
301 { .div = 10, .val = 10, .flags = RATE_IN_4430 },
302 { .div = 11, .val = 11, .flags = RATE_IN_4430 },
303 { .div = 12, .val = 12, .flags = RATE_IN_4430 },
304 { .div = 13, .val = 13, .flags = RATE_IN_4430 },
305 { .div = 14, .val = 14, .flags = RATE_IN_4430 },
306 { .div = 15, .val = 15, .flags = RATE_IN_4430 },
307 { .div = 16, .val = 16, .flags = RATE_IN_4430 },
308 { .div = 17, .val = 17, .flags = RATE_IN_4430 },
309 { .div = 18, .val = 18, .flags = RATE_IN_4430 },
310 { .div = 19, .val = 19, .flags = RATE_IN_4430 },
311 { .div = 20, .val = 20, .flags = RATE_IN_4430 },
312 { .div = 21, .val = 21, .flags = RATE_IN_4430 },
313 { .div = 22, .val = 22, .flags = RATE_IN_4430 },
314 { .div = 23, .val = 23, .flags = RATE_IN_4430 },
315 { .div = 24, .val = 24, .flags = RATE_IN_4430 },
316 { .div = 25, .val = 25, .flags = RATE_IN_4430 },
317 { .div = 26, .val = 26, .flags = RATE_IN_4430 },
318 { .div = 27, .val = 27, .flags = RATE_IN_4430 },
319 { .div = 28, .val = 28, .flags = RATE_IN_4430 },
320 { .div = 29, .val = 29, .flags = RATE_IN_4430 },
321 { .div = 30, .val = 30, .flags = RATE_IN_4430 },
322 { .div = 31, .val = 31, .flags = RATE_IN_4430 },
323 { .div = 0 },
324 };
325
326 static const struct clksel dpll_abe_m2x2_div[] = {
327 { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
328 { .parent = NULL },
329 };
330
331 static struct clk dpll_abe_m2x2_ck = {
332 .name = "dpll_abe_m2x2_ck",
333 .parent = &dpll_abe_x2_ck,
334 .clksel = dpll_abe_m2x2_div,
335 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
336 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
337 .ops = &clkops_omap4_dpllmx_ops,
338 .recalc = &omap2_clksel_recalc,
339 .round_rate = &omap2_clksel_round_rate,
340 .set_rate = &omap2_clksel_set_rate,
341 };
342
343 static struct clk abe_24m_fclk = {
344 .name = "abe_24m_fclk",
345 .parent = &dpll_abe_m2x2_ck,
346 .ops = &clkops_null,
347 .fixed_div = 8,
348 .recalc = &omap_fixed_divisor_recalc,
349 };
350
351 static const struct clksel_rate div3_1to4_rates[] = {
352 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
353 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
354 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
355 { .div = 0 },
356 };
357
358 static const struct clksel abe_clk_div[] = {
359 { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
360 { .parent = NULL },
361 };
362
363 static struct clk abe_clk = {
364 .name = "abe_clk",
365 .parent = &dpll_abe_m2x2_ck,
366 .clksel = abe_clk_div,
367 .clksel_reg = OMAP4430_CM_CLKSEL_ABE,
368 .clksel_mask = OMAP4430_CLKSEL_OPP_MASK,
369 .ops = &clkops_null,
370 .recalc = &omap2_clksel_recalc,
371 .round_rate = &omap2_clksel_round_rate,
372 .set_rate = &omap2_clksel_set_rate,
373 };
374
375 static const struct clksel_rate div2_1to2_rates[] = {
376 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
377 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
378 { .div = 0 },
379 };
380
381 static const struct clksel aess_fclk_div[] = {
382 { .parent = &abe_clk, .rates = div2_1to2_rates },
383 { .parent = NULL },
384 };
385
386 static struct clk aess_fclk = {
387 .name = "aess_fclk",
388 .parent = &abe_clk,
389 .clksel = aess_fclk_div,
390 .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
391 .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
392 .ops = &clkops_null,
393 .recalc = &omap2_clksel_recalc,
394 .round_rate = &omap2_clksel_round_rate,
395 .set_rate = &omap2_clksel_set_rate,
396 };
397
398 static struct clk dpll_abe_m3x2_ck = {
399 .name = "dpll_abe_m3x2_ck",
400 .parent = &dpll_abe_x2_ck,
401 .clksel = dpll_abe_m2x2_div,
402 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
403 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
404 .ops = &clkops_omap4_dpllmx_ops,
405 .recalc = &omap2_clksel_recalc,
406 .round_rate = &omap2_clksel_round_rate,
407 .set_rate = &omap2_clksel_set_rate,
408 };
409
410 static const struct clksel core_hsd_byp_clk_mux_sel[] = {
411 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
412 { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
413 { .parent = NULL },
414 };
415
416 static struct clk core_hsd_byp_clk_mux_ck = {
417 .name = "core_hsd_byp_clk_mux_ck",
418 .parent = &sys_clkin_ck,
419 .clksel = core_hsd_byp_clk_mux_sel,
420 .init = &omap2_init_clksel_parent,
421 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
422 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
423 .ops = &clkops_null,
424 .recalc = &omap2_clksel_recalc,
425 };
426
427 /* DPLL_CORE */
428 static struct dpll_data dpll_core_dd = {
429 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
430 .clk_bypass = &core_hsd_byp_clk_mux_ck,
431 .clk_ref = &sys_clkin_ck,
432 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
433 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
434 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
435 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE,
436 .mult_mask = OMAP4430_DPLL_MULT_MASK,
437 .div1_mask = OMAP4430_DPLL_DIV_MASK,
438 .enable_mask = OMAP4430_DPLL_EN_MASK,
439 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
440 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
441 .max_multiplier = 2047,
442 .max_divider = 128,
443 .min_divider = 1,
444 };
445
446
447 static struct clk dpll_core_ck = {
448 .name = "dpll_core_ck",
449 .parent = &sys_clkin_ck,
450 .dpll_data = &dpll_core_dd,
451 .init = &omap2_init_dpll_parent,
452 .ops = &clkops_omap3_core_dpll_ops,
453 .recalc = &omap3_dpll_recalc,
454 };
455
456 static struct clk dpll_core_x2_ck = {
457 .name = "dpll_core_x2_ck",
458 .parent = &dpll_core_ck,
459 .flags = CLOCK_CLKOUTX2,
460 .ops = &clkops_null,
461 .recalc = &omap3_clkoutx2_recalc,
462 };
463
464 static const struct clksel dpll_core_m6x2_div[] = {
465 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
466 { .parent = NULL },
467 };
468
469 static struct clk dpll_core_m6x2_ck = {
470 .name = "dpll_core_m6x2_ck",
471 .parent = &dpll_core_x2_ck,
472 .clksel = dpll_core_m6x2_div,
473 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
474 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
475 .ops = &clkops_omap4_dpllmx_ops,
476 .recalc = &omap2_clksel_recalc,
477 .round_rate = &omap2_clksel_round_rate,
478 .set_rate = &omap2_clksel_set_rate,
479 };
480
481 static const struct clksel dbgclk_mux_sel[] = {
482 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
483 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
484 { .parent = NULL },
485 };
486
487 static struct clk dbgclk_mux_ck = {
488 .name = "dbgclk_mux_ck",
489 .parent = &sys_clkin_ck,
490 .ops = &clkops_null,
491 .recalc = &followparent_recalc,
492 };
493
494 static const struct clksel dpll_core_m2_div[] = {
495 { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
496 { .parent = NULL },
497 };
498
499 static struct clk dpll_core_m2_ck = {
500 .name = "dpll_core_m2_ck",
501 .parent = &dpll_core_ck,
502 .clksel = dpll_core_m2_div,
503 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
504 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
505 .ops = &clkops_omap4_dpllmx_ops,
506 .recalc = &omap2_clksel_recalc,
507 .round_rate = &omap2_clksel_round_rate,
508 .set_rate = &omap2_clksel_set_rate,
509 };
510
511 static struct clk ddrphy_ck = {
512 .name = "ddrphy_ck",
513 .parent = &dpll_core_m2_ck,
514 .ops = &clkops_null,
515 .fixed_div = 2,
516 .recalc = &omap_fixed_divisor_recalc,
517 };
518
519 static struct clk dpll_core_m5x2_ck = {
520 .name = "dpll_core_m5x2_ck",
521 .parent = &dpll_core_x2_ck,
522 .clksel = dpll_core_m6x2_div,
523 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
524 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
525 .ops = &clkops_omap4_dpllmx_ops,
526 .recalc = &omap2_clksel_recalc,
527 .round_rate = &omap2_clksel_round_rate,
528 .set_rate = &omap2_clksel_set_rate,
529 };
530
531 static const struct clksel div_core_div[] = {
532 { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
533 { .parent = NULL },
534 };
535
536 static struct clk div_core_ck = {
537 .name = "div_core_ck",
538 .parent = &dpll_core_m5x2_ck,
539 .clksel = div_core_div,
540 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
541 .clksel_mask = OMAP4430_CLKSEL_CORE_MASK,
542 .ops = &clkops_null,
543 .recalc = &omap2_clksel_recalc,
544 .round_rate = &omap2_clksel_round_rate,
545 .set_rate = &omap2_clksel_set_rate,
546 };
547
548 static const struct clksel_rate div4_1to8_rates[] = {
549 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
550 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
551 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
552 { .div = 8, .val = 3, .flags = RATE_IN_4430 },
553 { .div = 0 },
554 };
555
556 static const struct clksel div_iva_hs_clk_div[] = {
557 { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
558 { .parent = NULL },
559 };
560
561 static struct clk div_iva_hs_clk = {
562 .name = "div_iva_hs_clk",
563 .parent = &dpll_core_m5x2_ck,
564 .clksel = div_iva_hs_clk_div,
565 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA,
566 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
567 .ops = &clkops_null,
568 .recalc = &omap2_clksel_recalc,
569 .round_rate = &omap2_clksel_round_rate,
570 .set_rate = &omap2_clksel_set_rate,
571 };
572
573 static struct clk div_mpu_hs_clk = {
574 .name = "div_mpu_hs_clk",
575 .parent = &dpll_core_m5x2_ck,
576 .clksel = div_iva_hs_clk_div,
577 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU,
578 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
579 .ops = &clkops_null,
580 .recalc = &omap2_clksel_recalc,
581 .round_rate = &omap2_clksel_round_rate,
582 .set_rate = &omap2_clksel_set_rate,
583 };
584
585 static struct clk dpll_core_m4x2_ck = {
586 .name = "dpll_core_m4x2_ck",
587 .parent = &dpll_core_x2_ck,
588 .clksel = dpll_core_m6x2_div,
589 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
590 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
591 .ops = &clkops_omap4_dpllmx_ops,
592 .recalc = &omap2_clksel_recalc,
593 .round_rate = &omap2_clksel_round_rate,
594 .set_rate = &omap2_clksel_set_rate,
595 };
596
597 static struct clk dll_clk_div_ck = {
598 .name = "dll_clk_div_ck",
599 .parent = &dpll_core_m4x2_ck,
600 .ops = &clkops_null,
601 .fixed_div = 2,
602 .recalc = &omap_fixed_divisor_recalc,
603 };
604
605 static const struct clksel dpll_abe_m2_div[] = {
606 { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
607 { .parent = NULL },
608 };
609
610 static struct clk dpll_abe_m2_ck = {
611 .name = "dpll_abe_m2_ck",
612 .parent = &dpll_abe_ck,
613 .clksel = dpll_abe_m2_div,
614 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
615 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
616 .ops = &clkops_omap4_dpllmx_ops,
617 .recalc = &omap2_clksel_recalc,
618 .round_rate = &omap2_clksel_round_rate,
619 .set_rate = &omap2_clksel_set_rate,
620 };
621
622 static struct clk dpll_core_m3x2_ck = {
623 .name = "dpll_core_m3x2_ck",
624 .parent = &dpll_core_x2_ck,
625 .clksel = dpll_core_m6x2_div,
626 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
627 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
628 .ops = &clkops_omap2_dflt,
629 .recalc = &omap2_clksel_recalc,
630 .round_rate = &omap2_clksel_round_rate,
631 .set_rate = &omap2_clksel_set_rate,
632 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
633 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
634 };
635
636 static struct clk dpll_core_m7x2_ck = {
637 .name = "dpll_core_m7x2_ck",
638 .parent = &dpll_core_x2_ck,
639 .clksel = dpll_core_m6x2_div,
640 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
641 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
642 .ops = &clkops_omap4_dpllmx_ops,
643 .recalc = &omap2_clksel_recalc,
644 .round_rate = &omap2_clksel_round_rate,
645 .set_rate = &omap2_clksel_set_rate,
646 };
647
648 static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
649 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
650 { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
651 { .parent = NULL },
652 };
653
654 static struct clk iva_hsd_byp_clk_mux_ck = {
655 .name = "iva_hsd_byp_clk_mux_ck",
656 .parent = &sys_clkin_ck,
657 .clksel = iva_hsd_byp_clk_mux_sel,
658 .init = &omap2_init_clksel_parent,
659 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
660 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
661 .ops = &clkops_null,
662 .recalc = &omap2_clksel_recalc,
663 };
664
665 /* DPLL_IVA */
666 static struct dpll_data dpll_iva_dd = {
667 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
668 .clk_bypass = &iva_hsd_byp_clk_mux_ck,
669 .clk_ref = &sys_clkin_ck,
670 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
671 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
672 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
673 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA,
674 .mult_mask = OMAP4430_DPLL_MULT_MASK,
675 .div1_mask = OMAP4430_DPLL_DIV_MASK,
676 .enable_mask = OMAP4430_DPLL_EN_MASK,
677 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
678 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
679 .max_multiplier = 2047,
680 .max_divider = 128,
681 .min_divider = 1,
682 };
683
684
685 static struct clk dpll_iva_ck = {
686 .name = "dpll_iva_ck",
687 .parent = &sys_clkin_ck,
688 .dpll_data = &dpll_iva_dd,
689 .init = &omap2_init_dpll_parent,
690 .ops = &clkops_omap3_noncore_dpll_ops,
691 .recalc = &omap3_dpll_recalc,
692 .round_rate = &omap2_dpll_round_rate,
693 .set_rate = &omap3_noncore_dpll_set_rate,
694 };
695
696 static struct clk dpll_iva_x2_ck = {
697 .name = "dpll_iva_x2_ck",
698 .parent = &dpll_iva_ck,
699 .flags = CLOCK_CLKOUTX2,
700 .ops = &clkops_null,
701 .recalc = &omap3_clkoutx2_recalc,
702 };
703
704 static const struct clksel dpll_iva_m4x2_div[] = {
705 { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
706 { .parent = NULL },
707 };
708
709 static struct clk dpll_iva_m4x2_ck = {
710 .name = "dpll_iva_m4x2_ck",
711 .parent = &dpll_iva_x2_ck,
712 .clksel = dpll_iva_m4x2_div,
713 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
714 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
715 .ops = &clkops_omap4_dpllmx_ops,
716 .recalc = &omap2_clksel_recalc,
717 .round_rate = &omap2_clksel_round_rate,
718 .set_rate = &omap2_clksel_set_rate,
719 };
720
721 static struct clk dpll_iva_m5x2_ck = {
722 .name = "dpll_iva_m5x2_ck",
723 .parent = &dpll_iva_x2_ck,
724 .clksel = dpll_iva_m4x2_div,
725 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
726 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
727 .ops = &clkops_omap4_dpllmx_ops,
728 .recalc = &omap2_clksel_recalc,
729 .round_rate = &omap2_clksel_round_rate,
730 .set_rate = &omap2_clksel_set_rate,
731 };
732
733 /* DPLL_MPU */
734 static struct dpll_data dpll_mpu_dd = {
735 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
736 .clk_bypass = &div_mpu_hs_clk,
737 .clk_ref = &sys_clkin_ck,
738 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
739 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
740 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
741 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU,
742 .mult_mask = OMAP4430_DPLL_MULT_MASK,
743 .div1_mask = OMAP4430_DPLL_DIV_MASK,
744 .enable_mask = OMAP4430_DPLL_EN_MASK,
745 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
746 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
747 .max_multiplier = 2047,
748 .max_divider = 128,
749 .min_divider = 1,
750 };
751
752
753 static struct clk dpll_mpu_ck = {
754 .name = "dpll_mpu_ck",
755 .parent = &sys_clkin_ck,
756 .dpll_data = &dpll_mpu_dd,
757 .init = &omap2_init_dpll_parent,
758 .ops = &clkops_omap3_noncore_dpll_ops,
759 .recalc = &omap3_dpll_recalc,
760 .round_rate = &omap2_dpll_round_rate,
761 .set_rate = &omap3_noncore_dpll_set_rate,
762 };
763
764 static const struct clksel dpll_mpu_m2_div[] = {
765 { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
766 { .parent = NULL },
767 };
768
769 static struct clk dpll_mpu_m2_ck = {
770 .name = "dpll_mpu_m2_ck",
771 .parent = &dpll_mpu_ck,
772 .clksel = dpll_mpu_m2_div,
773 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
774 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
775 .ops = &clkops_omap4_dpllmx_ops,
776 .recalc = &omap2_clksel_recalc,
777 .round_rate = &omap2_clksel_round_rate,
778 .set_rate = &omap2_clksel_set_rate,
779 };
780
781 static struct clk per_hs_clk_div_ck = {
782 .name = "per_hs_clk_div_ck",
783 .parent = &dpll_abe_m3x2_ck,
784 .ops = &clkops_null,
785 .fixed_div = 2,
786 .recalc = &omap_fixed_divisor_recalc,
787 };
788
789 static const struct clksel per_hsd_byp_clk_mux_sel[] = {
790 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
791 { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
792 { .parent = NULL },
793 };
794
795 static struct clk per_hsd_byp_clk_mux_ck = {
796 .name = "per_hsd_byp_clk_mux_ck",
797 .parent = &sys_clkin_ck,
798 .clksel = per_hsd_byp_clk_mux_sel,
799 .init = &omap2_init_clksel_parent,
800 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
801 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
802 .ops = &clkops_null,
803 .recalc = &omap2_clksel_recalc,
804 };
805
806 /* DPLL_PER */
807 static struct dpll_data dpll_per_dd = {
808 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
809 .clk_bypass = &per_hsd_byp_clk_mux_ck,
810 .clk_ref = &sys_clkin_ck,
811 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
812 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
813 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
814 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER,
815 .mult_mask = OMAP4430_DPLL_MULT_MASK,
816 .div1_mask = OMAP4430_DPLL_DIV_MASK,
817 .enable_mask = OMAP4430_DPLL_EN_MASK,
818 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
819 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
820 .max_multiplier = 2047,
821 .max_divider = 128,
822 .min_divider = 1,
823 };
824
825
826 static struct clk dpll_per_ck = {
827 .name = "dpll_per_ck",
828 .parent = &sys_clkin_ck,
829 .dpll_data = &dpll_per_dd,
830 .init = &omap2_init_dpll_parent,
831 .ops = &clkops_omap3_noncore_dpll_ops,
832 .recalc = &omap3_dpll_recalc,
833 .round_rate = &omap2_dpll_round_rate,
834 .set_rate = &omap3_noncore_dpll_set_rate,
835 };
836
837 static const struct clksel dpll_per_m2_div[] = {
838 { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
839 { .parent = NULL },
840 };
841
842 static struct clk dpll_per_m2_ck = {
843 .name = "dpll_per_m2_ck",
844 .parent = &dpll_per_ck,
845 .clksel = dpll_per_m2_div,
846 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
847 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
848 .ops = &clkops_omap4_dpllmx_ops,
849 .recalc = &omap2_clksel_recalc,
850 .round_rate = &omap2_clksel_round_rate,
851 .set_rate = &omap2_clksel_set_rate,
852 };
853
854 static struct clk dpll_per_x2_ck = {
855 .name = "dpll_per_x2_ck",
856 .parent = &dpll_per_ck,
857 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
858 .flags = CLOCK_CLKOUTX2,
859 .ops = &clkops_omap4_dpllmx_ops,
860 .recalc = &omap3_clkoutx2_recalc,
861 };
862
863 static const struct clksel dpll_per_m2x2_div[] = {
864 { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
865 { .parent = NULL },
866 };
867
868 static struct clk dpll_per_m2x2_ck = {
869 .name = "dpll_per_m2x2_ck",
870 .parent = &dpll_per_x2_ck,
871 .clksel = dpll_per_m2x2_div,
872 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
873 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
874 .ops = &clkops_omap4_dpllmx_ops,
875 .recalc = &omap2_clksel_recalc,
876 .round_rate = &omap2_clksel_round_rate,
877 .set_rate = &omap2_clksel_set_rate,
878 };
879
880 static struct clk dpll_per_m3x2_ck = {
881 .name = "dpll_per_m3x2_ck",
882 .parent = &dpll_per_x2_ck,
883 .clksel = dpll_per_m2x2_div,
884 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
885 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
886 .ops = &clkops_omap2_dflt,
887 .recalc = &omap2_clksel_recalc,
888 .round_rate = &omap2_clksel_round_rate,
889 .set_rate = &omap2_clksel_set_rate,
890 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
891 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
892 };
893
894 static struct clk dpll_per_m4x2_ck = {
895 .name = "dpll_per_m4x2_ck",
896 .parent = &dpll_per_x2_ck,
897 .clksel = dpll_per_m2x2_div,
898 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
899 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
900 .ops = &clkops_omap4_dpllmx_ops,
901 .recalc = &omap2_clksel_recalc,
902 .round_rate = &omap2_clksel_round_rate,
903 .set_rate = &omap2_clksel_set_rate,
904 };
905
906 static struct clk dpll_per_m5x2_ck = {
907 .name = "dpll_per_m5x2_ck",
908 .parent = &dpll_per_x2_ck,
909 .clksel = dpll_per_m2x2_div,
910 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
911 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
912 .ops = &clkops_omap4_dpllmx_ops,
913 .recalc = &omap2_clksel_recalc,
914 .round_rate = &omap2_clksel_round_rate,
915 .set_rate = &omap2_clksel_set_rate,
916 };
917
918 static struct clk dpll_per_m6x2_ck = {
919 .name = "dpll_per_m6x2_ck",
920 .parent = &dpll_per_x2_ck,
921 .clksel = dpll_per_m2x2_div,
922 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
923 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
924 .ops = &clkops_omap4_dpllmx_ops,
925 .recalc = &omap2_clksel_recalc,
926 .round_rate = &omap2_clksel_round_rate,
927 .set_rate = &omap2_clksel_set_rate,
928 };
929
930 static struct clk dpll_per_m7x2_ck = {
931 .name = "dpll_per_m7x2_ck",
932 .parent = &dpll_per_x2_ck,
933 .clksel = dpll_per_m2x2_div,
934 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
935 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
936 .ops = &clkops_omap4_dpllmx_ops,
937 .recalc = &omap2_clksel_recalc,
938 .round_rate = &omap2_clksel_round_rate,
939 .set_rate = &omap2_clksel_set_rate,
940 };
941
942 static struct clk usb_hs_clk_div_ck = {
943 .name = "usb_hs_clk_div_ck",
944 .parent = &dpll_abe_m3x2_ck,
945 .ops = &clkops_null,
946 .fixed_div = 3,
947 .recalc = &omap_fixed_divisor_recalc,
948 };
949
950 /* DPLL_USB */
951 static struct dpll_data dpll_usb_dd = {
952 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
953 .clk_bypass = &usb_hs_clk_div_ck,
954 .flags = DPLL_J_TYPE,
955 .clk_ref = &sys_clkin_ck,
956 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
957 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
958 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
959 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB,
960 .mult_mask = OMAP4430_DPLL_MULT_USB_MASK,
961 .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK,
962 .enable_mask = OMAP4430_DPLL_EN_MASK,
963 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
964 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
965 .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
966 .max_multiplier = 4095,
967 .max_divider = 256,
968 .min_divider = 1,
969 };
970
971
972 static struct clk dpll_usb_ck = {
973 .name = "dpll_usb_ck",
974 .parent = &sys_clkin_ck,
975 .dpll_data = &dpll_usb_dd,
976 .init = &omap2_init_dpll_parent,
977 .ops = &clkops_omap3_noncore_dpll_ops,
978 .recalc = &omap3_dpll_recalc,
979 .round_rate = &omap2_dpll_round_rate,
980 .set_rate = &omap3_noncore_dpll_set_rate,
981 .clkdm_name = "l3_init_clkdm",
982 };
983
984 static struct clk dpll_usb_clkdcoldo_ck = {
985 .name = "dpll_usb_clkdcoldo_ck",
986 .parent = &dpll_usb_ck,
987 .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
988 .ops = &clkops_omap4_dpllmx_ops,
989 .recalc = &followparent_recalc,
990 };
991
992 static const struct clksel dpll_usb_m2_div[] = {
993 { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
994 { .parent = NULL },
995 };
996
997 static struct clk dpll_usb_m2_ck = {
998 .name = "dpll_usb_m2_ck",
999 .parent = &dpll_usb_ck,
1000 .clksel = dpll_usb_m2_div,
1001 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB,
1002 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
1003 .ops = &clkops_omap4_dpllmx_ops,
1004 .recalc = &omap2_clksel_recalc,
1005 .round_rate = &omap2_clksel_round_rate,
1006 .set_rate = &omap2_clksel_set_rate,
1007 };
1008
1009 static const struct clksel ducati_clk_mux_sel[] = {
1010 { .parent = &div_core_ck, .rates = div_1_0_rates },
1011 { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
1012 { .parent = NULL },
1013 };
1014
1015 static struct clk ducati_clk_mux_ck = {
1016 .name = "ducati_clk_mux_ck",
1017 .parent = &div_core_ck,
1018 .clksel = ducati_clk_mux_sel,
1019 .init = &omap2_init_clksel_parent,
1020 .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
1021 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1022 .ops = &clkops_null,
1023 .recalc = &omap2_clksel_recalc,
1024 };
1025
1026 static struct clk func_12m_fclk = {
1027 .name = "func_12m_fclk",
1028 .parent = &dpll_per_m2x2_ck,
1029 .ops = &clkops_null,
1030 .fixed_div = 16,
1031 .recalc = &omap_fixed_divisor_recalc,
1032 };
1033
1034 static struct clk func_24m_clk = {
1035 .name = "func_24m_clk",
1036 .parent = &dpll_per_m2_ck,
1037 .ops = &clkops_null,
1038 .fixed_div = 4,
1039 .recalc = &omap_fixed_divisor_recalc,
1040 };
1041
1042 static struct clk func_24mc_fclk = {
1043 .name = "func_24mc_fclk",
1044 .parent = &dpll_per_m2x2_ck,
1045 .ops = &clkops_null,
1046 .fixed_div = 8,
1047 .recalc = &omap_fixed_divisor_recalc,
1048 };
1049
1050 static const struct clksel_rate div2_4to8_rates[] = {
1051 { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1052 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1053 { .div = 0 },
1054 };
1055
1056 static const struct clksel func_48m_fclk_div[] = {
1057 { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1058 { .parent = NULL },
1059 };
1060
1061 static struct clk func_48m_fclk = {
1062 .name = "func_48m_fclk",
1063 .parent = &dpll_per_m2x2_ck,
1064 .clksel = func_48m_fclk_div,
1065 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1066 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1067 .ops = &clkops_null,
1068 .recalc = &omap2_clksel_recalc,
1069 .round_rate = &omap2_clksel_round_rate,
1070 .set_rate = &omap2_clksel_set_rate,
1071 };
1072
1073 static struct clk func_48mc_fclk = {
1074 .name = "func_48mc_fclk",
1075 .parent = &dpll_per_m2x2_ck,
1076 .ops = &clkops_null,
1077 .fixed_div = 4,
1078 .recalc = &omap_fixed_divisor_recalc,
1079 };
1080
1081 static const struct clksel_rate div2_2to4_rates[] = {
1082 { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1083 { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1084 { .div = 0 },
1085 };
1086
1087 static const struct clksel func_64m_fclk_div[] = {
1088 { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
1089 { .parent = NULL },
1090 };
1091
1092 static struct clk func_64m_fclk = {
1093 .name = "func_64m_fclk",
1094 .parent = &dpll_per_m4x2_ck,
1095 .clksel = func_64m_fclk_div,
1096 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1097 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1098 .ops = &clkops_null,
1099 .recalc = &omap2_clksel_recalc,
1100 .round_rate = &omap2_clksel_round_rate,
1101 .set_rate = &omap2_clksel_set_rate,
1102 };
1103
1104 static const struct clksel func_96m_fclk_div[] = {
1105 { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1106 { .parent = NULL },
1107 };
1108
1109 static struct clk func_96m_fclk = {
1110 .name = "func_96m_fclk",
1111 .parent = &dpll_per_m2x2_ck,
1112 .clksel = func_96m_fclk_div,
1113 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1114 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1115 .ops = &clkops_null,
1116 .recalc = &omap2_clksel_recalc,
1117 .round_rate = &omap2_clksel_round_rate,
1118 .set_rate = &omap2_clksel_set_rate,
1119 };
1120
1121 static const struct clksel_rate div2_1to8_rates[] = {
1122 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1123 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1124 { .div = 0 },
1125 };
1126
1127 static const struct clksel init_60m_fclk_div[] = {
1128 { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1129 { .parent = NULL },
1130 };
1131
1132 static struct clk init_60m_fclk = {
1133 .name = "init_60m_fclk",
1134 .parent = &dpll_usb_m2_ck,
1135 .clksel = init_60m_fclk_div,
1136 .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ,
1137 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1138 .ops = &clkops_null,
1139 .recalc = &omap2_clksel_recalc,
1140 .round_rate = &omap2_clksel_round_rate,
1141 .set_rate = &omap2_clksel_set_rate,
1142 };
1143
1144 static const struct clksel l3_div_div[] = {
1145 { .parent = &div_core_ck, .rates = div2_1to2_rates },
1146 { .parent = NULL },
1147 };
1148
1149 static struct clk l3_div_ck = {
1150 .name = "l3_div_ck",
1151 .parent = &div_core_ck,
1152 .clksel = l3_div_div,
1153 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1154 .clksel_mask = OMAP4430_CLKSEL_L3_MASK,
1155 .ops = &clkops_null,
1156 .recalc = &omap2_clksel_recalc,
1157 .round_rate = &omap2_clksel_round_rate,
1158 .set_rate = &omap2_clksel_set_rate,
1159 };
1160
1161 static const struct clksel l4_div_div[] = {
1162 { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1163 { .parent = NULL },
1164 };
1165
1166 static struct clk l4_div_ck = {
1167 .name = "l4_div_ck",
1168 .parent = &l3_div_ck,
1169 .clksel = l4_div_div,
1170 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1171 .clksel_mask = OMAP4430_CLKSEL_L4_MASK,
1172 .ops = &clkops_null,
1173 .recalc = &omap2_clksel_recalc,
1174 .round_rate = &omap2_clksel_round_rate,
1175 .set_rate = &omap2_clksel_set_rate,
1176 };
1177
1178 static struct clk lp_clk_div_ck = {
1179 .name = "lp_clk_div_ck",
1180 .parent = &dpll_abe_m2x2_ck,
1181 .ops = &clkops_null,
1182 .fixed_div = 16,
1183 .recalc = &omap_fixed_divisor_recalc,
1184 };
1185
1186 static const struct clksel l4_wkup_clk_mux_sel[] = {
1187 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1188 { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1189 { .parent = NULL },
1190 };
1191
1192 static struct clk l4_wkup_clk_mux_ck = {
1193 .name = "l4_wkup_clk_mux_ck",
1194 .parent = &sys_clkin_ck,
1195 .clksel = l4_wkup_clk_mux_sel,
1196 .init = &omap2_init_clksel_parent,
1197 .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL,
1198 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1199 .ops = &clkops_null,
1200 .recalc = &omap2_clksel_recalc,
1201 };
1202
1203 static const struct clksel_rate div2_2to1_rates[] = {
1204 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
1205 { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1206 { .div = 0 },
1207 };
1208
1209 static const struct clksel ocp_abe_iclk_div[] = {
1210 { .parent = &aess_fclk, .rates = div2_2to1_rates },
1211 { .parent = NULL },
1212 };
1213
1214 static struct clk mpu_periphclk = {
1215 .name = "mpu_periphclk",
1216 .parent = &dpll_mpu_ck,
1217 .ops = &clkops_null,
1218 .fixed_div = 2,
1219 .recalc = &omap_fixed_divisor_recalc,
1220 };
1221
1222 static struct clk ocp_abe_iclk = {
1223 .name = "ocp_abe_iclk",
1224 .parent = &aess_fclk,
1225 .clksel = ocp_abe_iclk_div,
1226 .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1227 .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
1228 .ops = &clkops_null,
1229 .recalc = &omap2_clksel_recalc,
1230 };
1231
1232 static struct clk per_abe_24m_fclk = {
1233 .name = "per_abe_24m_fclk",
1234 .parent = &dpll_abe_m2_ck,
1235 .ops = &clkops_null,
1236 .fixed_div = 4,
1237 .recalc = &omap_fixed_divisor_recalc,
1238 };
1239
1240 static const struct clksel per_abe_nc_fclk_div[] = {
1241 { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1242 { .parent = NULL },
1243 };
1244
1245 static struct clk per_abe_nc_fclk = {
1246 .name = "per_abe_nc_fclk",
1247 .parent = &dpll_abe_m2_ck,
1248 .clksel = per_abe_nc_fclk_div,
1249 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1250 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1251 .ops = &clkops_null,
1252 .recalc = &omap2_clksel_recalc,
1253 .round_rate = &omap2_clksel_round_rate,
1254 .set_rate = &omap2_clksel_set_rate,
1255 };
1256
1257 static const struct clksel pmd_stm_clock_mux_sel[] = {
1258 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1259 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
1260 { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1261 { .parent = NULL },
1262 };
1263
1264 static struct clk pmd_stm_clock_mux_ck = {
1265 .name = "pmd_stm_clock_mux_ck",
1266 .parent = &sys_clkin_ck,
1267 .ops = &clkops_null,
1268 .recalc = &followparent_recalc,
1269 };
1270
1271 static struct clk pmd_trace_clk_mux_ck = {
1272 .name = "pmd_trace_clk_mux_ck",
1273 .parent = &sys_clkin_ck,
1274 .ops = &clkops_null,
1275 .recalc = &followparent_recalc,
1276 };
1277
1278 static const struct clksel syc_clk_div_div[] = {
1279 { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1280 { .parent = NULL },
1281 };
1282
1283 static struct clk syc_clk_div_ck = {
1284 .name = "syc_clk_div_ck",
1285 .parent = &sys_clkin_ck,
1286 .clksel = syc_clk_div_div,
1287 .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1288 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1289 .ops = &clkops_null,
1290 .recalc = &omap2_clksel_recalc,
1291 .round_rate = &omap2_clksel_round_rate,
1292 .set_rate = &omap2_clksel_set_rate,
1293 };
1294
1295 /* Leaf clocks controlled by modules */
1296
1297 static struct clk aes1_fck = {
1298 .name = "aes1_fck",
1299 .ops = &clkops_omap2_dflt,
1300 .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1301 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1302 .clkdm_name = "l4_secure_clkdm",
1303 .parent = &l3_div_ck,
1304 .recalc = &followparent_recalc,
1305 };
1306
1307 static struct clk aes2_fck = {
1308 .name = "aes2_fck",
1309 .ops = &clkops_omap2_dflt,
1310 .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1311 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1312 .clkdm_name = "l4_secure_clkdm",
1313 .parent = &l3_div_ck,
1314 .recalc = &followparent_recalc,
1315 };
1316
1317 static struct clk aess_fck = {
1318 .name = "aess_fck",
1319 .ops = &clkops_omap2_dflt,
1320 .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1321 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1322 .clkdm_name = "abe_clkdm",
1323 .parent = &aess_fclk,
1324 .recalc = &followparent_recalc,
1325 };
1326
1327 static struct clk bandgap_fclk = {
1328 .name = "bandgap_fclk",
1329 .ops = &clkops_omap2_dflt,
1330 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1331 .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1332 .clkdm_name = "l4_wkup_clkdm",
1333 .parent = &sys_32k_ck,
1334 .recalc = &followparent_recalc,
1335 };
1336
1337 static struct clk des3des_fck = {
1338 .name = "des3des_fck",
1339 .ops = &clkops_omap2_dflt,
1340 .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1341 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1342 .clkdm_name = "l4_secure_clkdm",
1343 .parent = &l4_div_ck,
1344 .recalc = &followparent_recalc,
1345 };
1346
1347 static const struct clksel dmic_sync_mux_sel[] = {
1348 { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1349 { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1350 { .parent = &func_24m_clk, .rates = div_1_2_rates },
1351 { .parent = NULL },
1352 };
1353
1354 static struct clk dmic_sync_mux_ck = {
1355 .name = "dmic_sync_mux_ck",
1356 .parent = &abe_24m_fclk,
1357 .clksel = dmic_sync_mux_sel,
1358 .init = &omap2_init_clksel_parent,
1359 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1360 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1361 .ops = &clkops_null,
1362 .recalc = &omap2_clksel_recalc,
1363 };
1364
1365 static const struct clksel func_dmic_abe_gfclk_sel[] = {
1366 { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1367 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1368 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1369 { .parent = NULL },
1370 };
1371
1372 /* Merged func_dmic_abe_gfclk into dmic */
1373 static struct clk dmic_fck = {
1374 .name = "dmic_fck",
1375 .parent = &dmic_sync_mux_ck,
1376 .clksel = func_dmic_abe_gfclk_sel,
1377 .init = &omap2_init_clksel_parent,
1378 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1379 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1380 .ops = &clkops_omap2_dflt,
1381 .recalc = &omap2_clksel_recalc,
1382 .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1383 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1384 .clkdm_name = "abe_clkdm",
1385 };
1386
1387 static struct clk dsp_fck = {
1388 .name = "dsp_fck",
1389 .ops = &clkops_omap2_dflt,
1390 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1391 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1392 .clkdm_name = "tesla_clkdm",
1393 .parent = &dpll_iva_m4x2_ck,
1394 .recalc = &followparent_recalc,
1395 };
1396
1397 static struct clk dss_sys_clk = {
1398 .name = "dss_sys_clk",
1399 .ops = &clkops_omap2_dflt,
1400 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1401 .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1402 .clkdm_name = "l3_dss_clkdm",
1403 .parent = &syc_clk_div_ck,
1404 .recalc = &followparent_recalc,
1405 };
1406
1407 static struct clk dss_tv_clk = {
1408 .name = "dss_tv_clk",
1409 .ops = &clkops_omap2_dflt,
1410 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1411 .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1412 .clkdm_name = "l3_dss_clkdm",
1413 .parent = &extalt_clkin_ck,
1414 .recalc = &followparent_recalc,
1415 };
1416
1417 static struct clk dss_dss_clk = {
1418 .name = "dss_dss_clk",
1419 .ops = &clkops_omap2_dflt,
1420 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1421 .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1422 .clkdm_name = "l3_dss_clkdm",
1423 .parent = &dpll_per_m5x2_ck,
1424 .recalc = &followparent_recalc,
1425 };
1426
1427 static const struct clksel_rate div3_8to32_rates[] = {
1428 { .div = 8, .val = 0, .flags = RATE_IN_4460 },
1429 { .div = 16, .val = 1, .flags = RATE_IN_4460 },
1430 { .div = 32, .val = 2, .flags = RATE_IN_4460 },
1431 { .div = 0 },
1432 };
1433
1434 static const struct clksel div_ts_div[] = {
1435 { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
1436 { .parent = NULL },
1437 };
1438
1439 static struct clk div_ts_ck = {
1440 .name = "div_ts_ck",
1441 .parent = &l4_wkup_clk_mux_ck,
1442 .clksel = div_ts_div,
1443 .clksel_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1444 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1445 .ops = &clkops_null,
1446 .recalc = &omap2_clksel_recalc,
1447 .round_rate = &omap2_clksel_round_rate,
1448 .set_rate = &omap2_clksel_set_rate,
1449 };
1450
1451 static struct clk bandgap_ts_fclk = {
1452 .name = "bandgap_ts_fclk",
1453 .ops = &clkops_omap2_dflt,
1454 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1455 .enable_bit = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
1456 .clkdm_name = "l4_wkup_clkdm",
1457 .parent = &div_ts_ck,
1458 .recalc = &followparent_recalc,
1459 };
1460
1461 static struct clk dss_48mhz_clk = {
1462 .name = "dss_48mhz_clk",
1463 .ops = &clkops_omap2_dflt,
1464 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1465 .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1466 .clkdm_name = "l3_dss_clkdm",
1467 .parent = &func_48mc_fclk,
1468 .recalc = &followparent_recalc,
1469 };
1470
1471 static struct clk dss_fck = {
1472 .name = "dss_fck",
1473 .ops = &clkops_omap2_dflt,
1474 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1475 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1476 .clkdm_name = "l3_dss_clkdm",
1477 .parent = &l3_div_ck,
1478 .recalc = &followparent_recalc,
1479 };
1480
1481 static struct clk efuse_ctrl_cust_fck = {
1482 .name = "efuse_ctrl_cust_fck",
1483 .ops = &clkops_omap2_dflt,
1484 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1485 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1486 .clkdm_name = "l4_cefuse_clkdm",
1487 .parent = &sys_clkin_ck,
1488 .recalc = &followparent_recalc,
1489 };
1490
1491 static struct clk emif1_fck = {
1492 .name = "emif1_fck",
1493 .ops = &clkops_omap2_dflt,
1494 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1495 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1496 .flags = ENABLE_ON_INIT,
1497 .clkdm_name = "l3_emif_clkdm",
1498 .parent = &ddrphy_ck,
1499 .recalc = &followparent_recalc,
1500 };
1501
1502 static struct clk emif2_fck = {
1503 .name = "emif2_fck",
1504 .ops = &clkops_omap2_dflt,
1505 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1506 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1507 .flags = ENABLE_ON_INIT,
1508 .clkdm_name = "l3_emif_clkdm",
1509 .parent = &ddrphy_ck,
1510 .recalc = &followparent_recalc,
1511 };
1512
1513 static const struct clksel fdif_fclk_div[] = {
1514 { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
1515 { .parent = NULL },
1516 };
1517
1518 /* Merged fdif_fclk into fdif */
1519 static struct clk fdif_fck = {
1520 .name = "fdif_fck",
1521 .parent = &dpll_per_m4x2_ck,
1522 .clksel = fdif_fclk_div,
1523 .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1524 .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK,
1525 .ops = &clkops_omap2_dflt,
1526 .recalc = &omap2_clksel_recalc,
1527 .round_rate = &omap2_clksel_round_rate,
1528 .set_rate = &omap2_clksel_set_rate,
1529 .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1530 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1531 .clkdm_name = "iss_clkdm",
1532 };
1533
1534 static struct clk fpka_fck = {
1535 .name = "fpka_fck",
1536 .ops = &clkops_omap2_dflt,
1537 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1538 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1539 .clkdm_name = "l4_secure_clkdm",
1540 .parent = &l4_div_ck,
1541 .recalc = &followparent_recalc,
1542 };
1543
1544 static struct clk gpio1_dbclk = {
1545 .name = "gpio1_dbclk",
1546 .ops = &clkops_omap2_dflt,
1547 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1548 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1549 .clkdm_name = "l4_wkup_clkdm",
1550 .parent = &sys_32k_ck,
1551 .recalc = &followparent_recalc,
1552 };
1553
1554 static struct clk gpio1_ick = {
1555 .name = "gpio1_ick",
1556 .ops = &clkops_omap2_dflt,
1557 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1558 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1559 .clkdm_name = "l4_wkup_clkdm",
1560 .parent = &l4_wkup_clk_mux_ck,
1561 .recalc = &followparent_recalc,
1562 };
1563
1564 static struct clk gpio2_dbclk = {
1565 .name = "gpio2_dbclk",
1566 .ops = &clkops_omap2_dflt,
1567 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1568 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1569 .clkdm_name = "l4_per_clkdm",
1570 .parent = &sys_32k_ck,
1571 .recalc = &followparent_recalc,
1572 };
1573
1574 static struct clk gpio2_ick = {
1575 .name = "gpio2_ick",
1576 .ops = &clkops_omap2_dflt,
1577 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1578 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1579 .clkdm_name = "l4_per_clkdm",
1580 .parent = &l4_div_ck,
1581 .recalc = &followparent_recalc,
1582 };
1583
1584 static struct clk gpio3_dbclk = {
1585 .name = "gpio3_dbclk",
1586 .ops = &clkops_omap2_dflt,
1587 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1588 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1589 .clkdm_name = "l4_per_clkdm",
1590 .parent = &sys_32k_ck,
1591 .recalc = &followparent_recalc,
1592 };
1593
1594 static struct clk gpio3_ick = {
1595 .name = "gpio3_ick",
1596 .ops = &clkops_omap2_dflt,
1597 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1598 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1599 .clkdm_name = "l4_per_clkdm",
1600 .parent = &l4_div_ck,
1601 .recalc = &followparent_recalc,
1602 };
1603
1604 static struct clk gpio4_dbclk = {
1605 .name = "gpio4_dbclk",
1606 .ops = &clkops_omap2_dflt,
1607 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1608 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1609 .clkdm_name = "l4_per_clkdm",
1610 .parent = &sys_32k_ck,
1611 .recalc = &followparent_recalc,
1612 };
1613
1614 static struct clk gpio4_ick = {
1615 .name = "gpio4_ick",
1616 .ops = &clkops_omap2_dflt,
1617 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1618 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1619 .clkdm_name = "l4_per_clkdm",
1620 .parent = &l4_div_ck,
1621 .recalc = &followparent_recalc,
1622 };
1623
1624 static struct clk gpio5_dbclk = {
1625 .name = "gpio5_dbclk",
1626 .ops = &clkops_omap2_dflt,
1627 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1628 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1629 .clkdm_name = "l4_per_clkdm",
1630 .parent = &sys_32k_ck,
1631 .recalc = &followparent_recalc,
1632 };
1633
1634 static struct clk gpio5_ick = {
1635 .name = "gpio5_ick",
1636 .ops = &clkops_omap2_dflt,
1637 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1638 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1639 .clkdm_name = "l4_per_clkdm",
1640 .parent = &l4_div_ck,
1641 .recalc = &followparent_recalc,
1642 };
1643
1644 static struct clk gpio6_dbclk = {
1645 .name = "gpio6_dbclk",
1646 .ops = &clkops_omap2_dflt,
1647 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1648 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1649 .clkdm_name = "l4_per_clkdm",
1650 .parent = &sys_32k_ck,
1651 .recalc = &followparent_recalc,
1652 };
1653
1654 static struct clk gpio6_ick = {
1655 .name = "gpio6_ick",
1656 .ops = &clkops_omap2_dflt,
1657 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1658 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1659 .clkdm_name = "l4_per_clkdm",
1660 .parent = &l4_div_ck,
1661 .recalc = &followparent_recalc,
1662 };
1663
1664 static struct clk gpmc_ick = {
1665 .name = "gpmc_ick",
1666 .ops = &clkops_omap2_dflt,
1667 .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1668 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1669 .flags = ENABLE_ON_INIT,
1670 .clkdm_name = "l3_2_clkdm",
1671 .parent = &l3_div_ck,
1672 .recalc = &followparent_recalc,
1673 };
1674
1675 static const struct clksel sgx_clk_mux_sel[] = {
1676 { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
1677 { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
1678 { .parent = NULL },
1679 };
1680
1681 /* Merged sgx_clk_mux into gpu */
1682 static struct clk gpu_fck = {
1683 .name = "gpu_fck",
1684 .parent = &dpll_core_m7x2_ck,
1685 .clksel = sgx_clk_mux_sel,
1686 .init = &omap2_init_clksel_parent,
1687 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1688 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1689 .ops = &clkops_omap2_dflt,
1690 .recalc = &omap2_clksel_recalc,
1691 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1692 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1693 .clkdm_name = "l3_gfx_clkdm",
1694 };
1695
1696 static struct clk hdq1w_fck = {
1697 .name = "hdq1w_fck",
1698 .ops = &clkops_omap2_dflt,
1699 .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1700 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1701 .clkdm_name = "l4_per_clkdm",
1702 .parent = &func_12m_fclk,
1703 .recalc = &followparent_recalc,
1704 };
1705
1706 static const struct clksel hsi_fclk_div[] = {
1707 { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1708 { .parent = NULL },
1709 };
1710
1711 /* Merged hsi_fclk into hsi */
1712 static struct clk hsi_fck = {
1713 .name = "hsi_fck",
1714 .parent = &dpll_per_m2x2_ck,
1715 .clksel = hsi_fclk_div,
1716 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1717 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1718 .ops = &clkops_omap2_dflt,
1719 .recalc = &omap2_clksel_recalc,
1720 .round_rate = &omap2_clksel_round_rate,
1721 .set_rate = &omap2_clksel_set_rate,
1722 .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1723 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1724 .clkdm_name = "l3_init_clkdm",
1725 };
1726
1727 static struct clk i2c1_fck = {
1728 .name = "i2c1_fck",
1729 .ops = &clkops_omap2_dflt,
1730 .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1731 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1732 .clkdm_name = "l4_per_clkdm",
1733 .parent = &func_96m_fclk,
1734 .recalc = &followparent_recalc,
1735 };
1736
1737 static struct clk i2c2_fck = {
1738 .name = "i2c2_fck",
1739 .ops = &clkops_omap2_dflt,
1740 .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1741 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1742 .clkdm_name = "l4_per_clkdm",
1743 .parent = &func_96m_fclk,
1744 .recalc = &followparent_recalc,
1745 };
1746
1747 static struct clk i2c3_fck = {
1748 .name = "i2c3_fck",
1749 .ops = &clkops_omap2_dflt,
1750 .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1751 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1752 .clkdm_name = "l4_per_clkdm",
1753 .parent = &func_96m_fclk,
1754 .recalc = &followparent_recalc,
1755 };
1756
1757 static struct clk i2c4_fck = {
1758 .name = "i2c4_fck",
1759 .ops = &clkops_omap2_dflt,
1760 .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1761 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1762 .clkdm_name = "l4_per_clkdm",
1763 .parent = &func_96m_fclk,
1764 .recalc = &followparent_recalc,
1765 };
1766
1767 static struct clk ipu_fck = {
1768 .name = "ipu_fck",
1769 .ops = &clkops_omap2_dflt,
1770 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1771 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1772 .clkdm_name = "ducati_clkdm",
1773 .parent = &ducati_clk_mux_ck,
1774 .recalc = &followparent_recalc,
1775 };
1776
1777 static struct clk iss_ctrlclk = {
1778 .name = "iss_ctrlclk",
1779 .ops = &clkops_omap2_dflt,
1780 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1781 .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1782 .clkdm_name = "iss_clkdm",
1783 .parent = &func_96m_fclk,
1784 .recalc = &followparent_recalc,
1785 };
1786
1787 static struct clk iss_fck = {
1788 .name = "iss_fck",
1789 .ops = &clkops_omap2_dflt,
1790 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1791 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1792 .clkdm_name = "iss_clkdm",
1793 .parent = &ducati_clk_mux_ck,
1794 .recalc = &followparent_recalc,
1795 };
1796
1797 static struct clk iva_fck = {
1798 .name = "iva_fck",
1799 .ops = &clkops_omap2_dflt,
1800 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1801 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1802 .clkdm_name = "ivahd_clkdm",
1803 .parent = &dpll_iva_m5x2_ck,
1804 .recalc = &followparent_recalc,
1805 };
1806
1807 static struct clk kbd_fck = {
1808 .name = "kbd_fck",
1809 .ops = &clkops_omap2_dflt,
1810 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1811 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1812 .clkdm_name = "l4_wkup_clkdm",
1813 .parent = &sys_32k_ck,
1814 .recalc = &followparent_recalc,
1815 };
1816
1817 static struct clk l3_instr_ick = {
1818 .name = "l3_instr_ick",
1819 .ops = &clkops_omap2_dflt,
1820 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1821 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1822 .flags = ENABLE_ON_INIT,
1823 .clkdm_name = "l3_instr_clkdm",
1824 .parent = &l3_div_ck,
1825 .recalc = &followparent_recalc,
1826 };
1827
1828 static struct clk l3_main_3_ick = {
1829 .name = "l3_main_3_ick",
1830 .ops = &clkops_omap2_dflt,
1831 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1832 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1833 .flags = ENABLE_ON_INIT,
1834 .clkdm_name = "l3_instr_clkdm",
1835 .parent = &l3_div_ck,
1836 .recalc = &followparent_recalc,
1837 };
1838
1839 static struct clk mcasp_sync_mux_ck = {
1840 .name = "mcasp_sync_mux_ck",
1841 .parent = &abe_24m_fclk,
1842 .clksel = dmic_sync_mux_sel,
1843 .init = &omap2_init_clksel_parent,
1844 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1845 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1846 .ops = &clkops_null,
1847 .recalc = &omap2_clksel_recalc,
1848 };
1849
1850 static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1851 { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1852 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1853 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1854 { .parent = NULL },
1855 };
1856
1857 /* Merged func_mcasp_abe_gfclk into mcasp */
1858 static struct clk mcasp_fck = {
1859 .name = "mcasp_fck",
1860 .parent = &mcasp_sync_mux_ck,
1861 .clksel = func_mcasp_abe_gfclk_sel,
1862 .init = &omap2_init_clksel_parent,
1863 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1864 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1865 .ops = &clkops_omap2_dflt,
1866 .recalc = &omap2_clksel_recalc,
1867 .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1868 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1869 .clkdm_name = "abe_clkdm",
1870 };
1871
1872 static struct clk mcbsp1_sync_mux_ck = {
1873 .name = "mcbsp1_sync_mux_ck",
1874 .parent = &abe_24m_fclk,
1875 .clksel = dmic_sync_mux_sel,
1876 .init = &omap2_init_clksel_parent,
1877 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1878 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1879 .ops = &clkops_null,
1880 .recalc = &omap2_clksel_recalc,
1881 };
1882
1883 static const struct clksel func_mcbsp1_gfclk_sel[] = {
1884 { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1885 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1886 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1887 { .parent = NULL },
1888 };
1889
1890 /* Merged func_mcbsp1_gfclk into mcbsp1 */
1891 static struct clk mcbsp1_fck = {
1892 .name = "mcbsp1_fck",
1893 .parent = &mcbsp1_sync_mux_ck,
1894 .clksel = func_mcbsp1_gfclk_sel,
1895 .init = &omap2_init_clksel_parent,
1896 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1897 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1898 .ops = &clkops_omap2_dflt,
1899 .recalc = &omap2_clksel_recalc,
1900 .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1901 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1902 .clkdm_name = "abe_clkdm",
1903 };
1904
1905 static struct clk mcbsp2_sync_mux_ck = {
1906 .name = "mcbsp2_sync_mux_ck",
1907 .parent = &abe_24m_fclk,
1908 .clksel = dmic_sync_mux_sel,
1909 .init = &omap2_init_clksel_parent,
1910 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1911 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1912 .ops = &clkops_null,
1913 .recalc = &omap2_clksel_recalc,
1914 };
1915
1916 static const struct clksel func_mcbsp2_gfclk_sel[] = {
1917 { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1918 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1919 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1920 { .parent = NULL },
1921 };
1922
1923 /* Merged func_mcbsp2_gfclk into mcbsp2 */
1924 static struct clk mcbsp2_fck = {
1925 .name = "mcbsp2_fck",
1926 .parent = &mcbsp2_sync_mux_ck,
1927 .clksel = func_mcbsp2_gfclk_sel,
1928 .init = &omap2_init_clksel_parent,
1929 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1930 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1931 .ops = &clkops_omap2_dflt,
1932 .recalc = &omap2_clksel_recalc,
1933 .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1934 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1935 .clkdm_name = "abe_clkdm",
1936 };
1937
1938 static struct clk mcbsp3_sync_mux_ck = {
1939 .name = "mcbsp3_sync_mux_ck",
1940 .parent = &abe_24m_fclk,
1941 .clksel = dmic_sync_mux_sel,
1942 .init = &omap2_init_clksel_parent,
1943 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1944 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1945 .ops = &clkops_null,
1946 .recalc = &omap2_clksel_recalc,
1947 };
1948
1949 static const struct clksel func_mcbsp3_gfclk_sel[] = {
1950 { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1951 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1952 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1953 { .parent = NULL },
1954 };
1955
1956 /* Merged func_mcbsp3_gfclk into mcbsp3 */
1957 static struct clk mcbsp3_fck = {
1958 .name = "mcbsp3_fck",
1959 .parent = &mcbsp3_sync_mux_ck,
1960 .clksel = func_mcbsp3_gfclk_sel,
1961 .init = &omap2_init_clksel_parent,
1962 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1963 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1964 .ops = &clkops_omap2_dflt,
1965 .recalc = &omap2_clksel_recalc,
1966 .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1967 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1968 .clkdm_name = "abe_clkdm",
1969 };
1970
1971 static const struct clksel mcbsp4_sync_mux_sel[] = {
1972 { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1973 { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1974 { .parent = NULL },
1975 };
1976
1977 static struct clk mcbsp4_sync_mux_ck = {
1978 .name = "mcbsp4_sync_mux_ck",
1979 .parent = &func_96m_fclk,
1980 .clksel = mcbsp4_sync_mux_sel,
1981 .init = &omap2_init_clksel_parent,
1982 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1983 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1984 .ops = &clkops_null,
1985 .recalc = &omap2_clksel_recalc,
1986 };
1987
1988 static const struct clksel per_mcbsp4_gfclk_sel[] = {
1989 { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1990 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1991 { .parent = NULL },
1992 };
1993
1994 /* Merged per_mcbsp4_gfclk into mcbsp4 */
1995 static struct clk mcbsp4_fck = {
1996 .name = "mcbsp4_fck",
1997 .parent = &mcbsp4_sync_mux_ck,
1998 .clksel = per_mcbsp4_gfclk_sel,
1999 .init = &omap2_init_clksel_parent,
2000 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2001 .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
2002 .ops = &clkops_omap2_dflt,
2003 .recalc = &omap2_clksel_recalc,
2004 .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2005 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2006 .clkdm_name = "l4_per_clkdm",
2007 };
2008
2009 static struct clk mcpdm_fck = {
2010 .name = "mcpdm_fck",
2011 .ops = &clkops_omap2_dflt,
2012 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
2013 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2014 .clkdm_name = "abe_clkdm",
2015 .parent = &pad_clks_ck,
2016 .recalc = &followparent_recalc,
2017 };
2018
2019 static struct clk mcspi1_fck = {
2020 .name = "mcspi1_fck",
2021 .ops = &clkops_omap2_dflt,
2022 .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
2023 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2024 .clkdm_name = "l4_per_clkdm",
2025 .parent = &func_48m_fclk,
2026 .recalc = &followparent_recalc,
2027 };
2028
2029 static struct clk mcspi2_fck = {
2030 .name = "mcspi2_fck",
2031 .ops = &clkops_omap2_dflt,
2032 .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2033 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2034 .clkdm_name = "l4_per_clkdm",
2035 .parent = &func_48m_fclk,
2036 .recalc = &followparent_recalc,
2037 };
2038
2039 static struct clk mcspi3_fck = {
2040 .name = "mcspi3_fck",
2041 .ops = &clkops_omap2_dflt,
2042 .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2043 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2044 .clkdm_name = "l4_per_clkdm",
2045 .parent = &func_48m_fclk,
2046 .recalc = &followparent_recalc,
2047 };
2048
2049 static struct clk mcspi4_fck = {
2050 .name = "mcspi4_fck",
2051 .ops = &clkops_omap2_dflt,
2052 .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2053 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2054 .clkdm_name = "l4_per_clkdm",
2055 .parent = &func_48m_fclk,
2056 .recalc = &followparent_recalc,
2057 };
2058
2059 static const struct clksel hsmmc1_fclk_sel[] = {
2060 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
2061 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
2062 { .parent = NULL },
2063 };
2064
2065 /* Merged hsmmc1_fclk into mmc1 */
2066 static struct clk mmc1_fck = {
2067 .name = "mmc1_fck",
2068 .parent = &func_64m_fclk,
2069 .clksel = hsmmc1_fclk_sel,
2070 .init = &omap2_init_clksel_parent,
2071 .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2072 .clksel_mask = OMAP4430_CLKSEL_MASK,
2073 .ops = &clkops_omap2_dflt,
2074 .recalc = &omap2_clksel_recalc,
2075 .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2076 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2077 .clkdm_name = "l3_init_clkdm",
2078 };
2079
2080 /* Merged hsmmc2_fclk into mmc2 */
2081 static struct clk mmc2_fck = {
2082 .name = "mmc2_fck",
2083 .parent = &func_64m_fclk,
2084 .clksel = hsmmc1_fclk_sel,
2085 .init = &omap2_init_clksel_parent,
2086 .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2087 .clksel_mask = OMAP4430_CLKSEL_MASK,
2088 .ops = &clkops_omap2_dflt,
2089 .recalc = &omap2_clksel_recalc,
2090 .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2091 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2092 .clkdm_name = "l3_init_clkdm",
2093 };
2094
2095 static struct clk mmc3_fck = {
2096 .name = "mmc3_fck",
2097 .ops = &clkops_omap2_dflt,
2098 .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2099 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2100 .clkdm_name = "l4_per_clkdm",
2101 .parent = &func_48m_fclk,
2102 .recalc = &followparent_recalc,
2103 };
2104
2105 static struct clk mmc4_fck = {
2106 .name = "mmc4_fck",
2107 .ops = &clkops_omap2_dflt,
2108 .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2109 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2110 .clkdm_name = "l4_per_clkdm",
2111 .parent = &func_48m_fclk,
2112 .recalc = &followparent_recalc,
2113 };
2114
2115 static struct clk mmc5_fck = {
2116 .name = "mmc5_fck",
2117 .ops = &clkops_omap2_dflt,
2118 .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2119 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2120 .clkdm_name = "l4_per_clkdm",
2121 .parent = &func_48m_fclk,
2122 .recalc = &followparent_recalc,
2123 };
2124
2125 static struct clk ocp2scp_usb_phy_phy_48m = {
2126 .name = "ocp2scp_usb_phy_phy_48m",
2127 .ops = &clkops_omap2_dflt,
2128 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2129 .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2130 .clkdm_name = "l3_init_clkdm",
2131 .parent = &func_48m_fclk,
2132 .recalc = &followparent_recalc,
2133 };
2134
2135 static struct clk ocp2scp_usb_phy_ick = {
2136 .name = "ocp2scp_usb_phy_ick",
2137 .ops = &clkops_omap2_dflt,
2138 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2139 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2140 .clkdm_name = "l3_init_clkdm",
2141 .parent = &l4_div_ck,
2142 .recalc = &followparent_recalc,
2143 };
2144
2145 static struct clk ocp_wp_noc_ick = {
2146 .name = "ocp_wp_noc_ick",
2147 .ops = &clkops_omap2_dflt,
2148 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2149 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2150 .flags = ENABLE_ON_INIT,
2151 .clkdm_name = "l3_instr_clkdm",
2152 .parent = &l3_div_ck,
2153 .recalc = &followparent_recalc,
2154 };
2155
2156 static struct clk rng_ick = {
2157 .name = "rng_ick",
2158 .ops = &clkops_omap2_dflt,
2159 .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2160 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2161 .clkdm_name = "l4_secure_clkdm",
2162 .parent = &l4_div_ck,
2163 .recalc = &followparent_recalc,
2164 };
2165
2166 static struct clk sha2md5_fck = {
2167 .name = "sha2md5_fck",
2168 .ops = &clkops_omap2_dflt,
2169 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2170 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2171 .clkdm_name = "l4_secure_clkdm",
2172 .parent = &l3_div_ck,
2173 .recalc = &followparent_recalc,
2174 };
2175
2176 static struct clk sl2if_ick = {
2177 .name = "sl2if_ick",
2178 .ops = &clkops_omap2_dflt,
2179 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2180 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2181 .clkdm_name = "ivahd_clkdm",
2182 .parent = &dpll_iva_m5x2_ck,
2183 .recalc = &followparent_recalc,
2184 };
2185
2186 static struct clk slimbus1_fclk_1 = {
2187 .name = "slimbus1_fclk_1",
2188 .ops = &clkops_omap2_dflt,
2189 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2190 .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2191 .clkdm_name = "abe_clkdm",
2192 .parent = &func_24m_clk,
2193 .recalc = &followparent_recalc,
2194 };
2195
2196 static struct clk slimbus1_fclk_0 = {
2197 .name = "slimbus1_fclk_0",
2198 .ops = &clkops_omap2_dflt,
2199 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2200 .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2201 .clkdm_name = "abe_clkdm",
2202 .parent = &abe_24m_fclk,
2203 .recalc = &followparent_recalc,
2204 };
2205
2206 static struct clk slimbus1_fclk_2 = {
2207 .name = "slimbus1_fclk_2",
2208 .ops = &clkops_omap2_dflt,
2209 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2210 .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2211 .clkdm_name = "abe_clkdm",
2212 .parent = &pad_clks_ck,
2213 .recalc = &followparent_recalc,
2214 };
2215
2216 static struct clk slimbus1_slimbus_clk = {
2217 .name = "slimbus1_slimbus_clk",
2218 .ops = &clkops_omap2_dflt,
2219 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2220 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2221 .clkdm_name = "abe_clkdm",
2222 .parent = &slimbus_clk,
2223 .recalc = &followparent_recalc,
2224 };
2225
2226 static struct clk slimbus1_fck = {
2227 .name = "slimbus1_fck",
2228 .ops = &clkops_omap2_dflt,
2229 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2230 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2231 .clkdm_name = "abe_clkdm",
2232 .parent = &ocp_abe_iclk,
2233 .recalc = &followparent_recalc,
2234 };
2235
2236 static struct clk slimbus2_fclk_1 = {
2237 .name = "slimbus2_fclk_1",
2238 .ops = &clkops_omap2_dflt,
2239 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2240 .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2241 .clkdm_name = "l4_per_clkdm",
2242 .parent = &per_abe_24m_fclk,
2243 .recalc = &followparent_recalc,
2244 };
2245
2246 static struct clk slimbus2_fclk_0 = {
2247 .name = "slimbus2_fclk_0",
2248 .ops = &clkops_omap2_dflt,
2249 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2250 .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2251 .clkdm_name = "l4_per_clkdm",
2252 .parent = &func_24mc_fclk,
2253 .recalc = &followparent_recalc,
2254 };
2255
2256 static struct clk slimbus2_slimbus_clk = {
2257 .name = "slimbus2_slimbus_clk",
2258 .ops = &clkops_omap2_dflt,
2259 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2260 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2261 .clkdm_name = "l4_per_clkdm",
2262 .parent = &pad_slimbus_core_clks_ck,
2263 .recalc = &followparent_recalc,
2264 };
2265
2266 static struct clk slimbus2_fck = {
2267 .name = "slimbus2_fck",
2268 .ops = &clkops_omap2_dflt,
2269 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2270 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2271 .clkdm_name = "l4_per_clkdm",
2272 .parent = &l4_div_ck,
2273 .recalc = &followparent_recalc,
2274 };
2275
2276 static struct clk smartreflex_core_fck = {
2277 .name = "smartreflex_core_fck",
2278 .ops = &clkops_omap2_dflt,
2279 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2280 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2281 .clkdm_name = "l4_ao_clkdm",
2282 .parent = &l4_wkup_clk_mux_ck,
2283 .recalc = &followparent_recalc,
2284 };
2285
2286 static struct clk smartreflex_iva_fck = {
2287 .name = "smartreflex_iva_fck",
2288 .ops = &clkops_omap2_dflt,
2289 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2290 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2291 .clkdm_name = "l4_ao_clkdm",
2292 .parent = &l4_wkup_clk_mux_ck,
2293 .recalc = &followparent_recalc,
2294 };
2295
2296 static struct clk smartreflex_mpu_fck = {
2297 .name = "smartreflex_mpu_fck",
2298 .ops = &clkops_omap2_dflt,
2299 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2300 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2301 .clkdm_name = "l4_ao_clkdm",
2302 .parent = &l4_wkup_clk_mux_ck,
2303 .recalc = &followparent_recalc,
2304 };
2305
2306 /* Merged dmt1_clk_mux into timer1 */
2307 static struct clk timer1_fck = {
2308 .name = "timer1_fck",
2309 .parent = &sys_clkin_ck,
2310 .clksel = abe_dpll_bypass_clk_mux_sel,
2311 .init = &omap2_init_clksel_parent,
2312 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2313 .clksel_mask = OMAP4430_CLKSEL_MASK,
2314 .ops = &clkops_omap2_dflt,
2315 .recalc = &omap2_clksel_recalc,
2316 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2317 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2318 .clkdm_name = "l4_wkup_clkdm",
2319 };
2320
2321 /* Merged cm2_dm10_mux into timer10 */
2322 static struct clk timer10_fck = {
2323 .name = "timer10_fck",
2324 .parent = &sys_clkin_ck,
2325 .clksel = abe_dpll_bypass_clk_mux_sel,
2326 .init = &omap2_init_clksel_parent,
2327 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2328 .clksel_mask = OMAP4430_CLKSEL_MASK,
2329 .ops = &clkops_omap2_dflt,
2330 .recalc = &omap2_clksel_recalc,
2331 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2332 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2333 .clkdm_name = "l4_per_clkdm",
2334 };
2335
2336 /* Merged cm2_dm11_mux into timer11 */
2337 static struct clk timer11_fck = {
2338 .name = "timer11_fck",
2339 .parent = &sys_clkin_ck,
2340 .clksel = abe_dpll_bypass_clk_mux_sel,
2341 .init = &omap2_init_clksel_parent,
2342 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2343 .clksel_mask = OMAP4430_CLKSEL_MASK,
2344 .ops = &clkops_omap2_dflt,
2345 .recalc = &omap2_clksel_recalc,
2346 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2347 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2348 .clkdm_name = "l4_per_clkdm",
2349 };
2350
2351 /* Merged cm2_dm2_mux into timer2 */
2352 static struct clk timer2_fck = {
2353 .name = "timer2_fck",
2354 .parent = &sys_clkin_ck,
2355 .clksel = abe_dpll_bypass_clk_mux_sel,
2356 .init = &omap2_init_clksel_parent,
2357 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2358 .clksel_mask = OMAP4430_CLKSEL_MASK,
2359 .ops = &clkops_omap2_dflt,
2360 .recalc = &omap2_clksel_recalc,
2361 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2362 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2363 .clkdm_name = "l4_per_clkdm",
2364 };
2365
2366 /* Merged cm2_dm3_mux into timer3 */
2367 static struct clk timer3_fck = {
2368 .name = "timer3_fck",
2369 .parent = &sys_clkin_ck,
2370 .clksel = abe_dpll_bypass_clk_mux_sel,
2371 .init = &omap2_init_clksel_parent,
2372 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2373 .clksel_mask = OMAP4430_CLKSEL_MASK,
2374 .ops = &clkops_omap2_dflt,
2375 .recalc = &omap2_clksel_recalc,
2376 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2377 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2378 .clkdm_name = "l4_per_clkdm",
2379 };
2380
2381 /* Merged cm2_dm4_mux into timer4 */
2382 static struct clk timer4_fck = {
2383 .name = "timer4_fck",
2384 .parent = &sys_clkin_ck,
2385 .clksel = abe_dpll_bypass_clk_mux_sel,
2386 .init = &omap2_init_clksel_parent,
2387 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2388 .clksel_mask = OMAP4430_CLKSEL_MASK,
2389 .ops = &clkops_omap2_dflt,
2390 .recalc = &omap2_clksel_recalc,
2391 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2392 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2393 .clkdm_name = "l4_per_clkdm",
2394 };
2395
2396 static const struct clksel timer5_sync_mux_sel[] = {
2397 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2398 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2399 { .parent = NULL },
2400 };
2401
2402 /* Merged timer5_sync_mux into timer5 */
2403 static struct clk timer5_fck = {
2404 .name = "timer5_fck",
2405 .parent = &syc_clk_div_ck,
2406 .clksel = timer5_sync_mux_sel,
2407 .init = &omap2_init_clksel_parent,
2408 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2409 .clksel_mask = OMAP4430_CLKSEL_MASK,
2410 .ops = &clkops_omap2_dflt,
2411 .recalc = &omap2_clksel_recalc,
2412 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2413 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2414 .clkdm_name = "abe_clkdm",
2415 };
2416
2417 /* Merged timer6_sync_mux into timer6 */
2418 static struct clk timer6_fck = {
2419 .name = "timer6_fck",
2420 .parent = &syc_clk_div_ck,
2421 .clksel = timer5_sync_mux_sel,
2422 .init = &omap2_init_clksel_parent,
2423 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2424 .clksel_mask = OMAP4430_CLKSEL_MASK,
2425 .ops = &clkops_omap2_dflt,
2426 .recalc = &omap2_clksel_recalc,
2427 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2428 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2429 .clkdm_name = "abe_clkdm",
2430 };
2431
2432 /* Merged timer7_sync_mux into timer7 */
2433 static struct clk timer7_fck = {
2434 .name = "timer7_fck",
2435 .parent = &syc_clk_div_ck,
2436 .clksel = timer5_sync_mux_sel,
2437 .init = &omap2_init_clksel_parent,
2438 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2439 .clksel_mask = OMAP4430_CLKSEL_MASK,
2440 .ops = &clkops_omap2_dflt,
2441 .recalc = &omap2_clksel_recalc,
2442 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2443 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2444 .clkdm_name = "abe_clkdm",
2445 };
2446
2447 /* Merged timer8_sync_mux into timer8 */
2448 static struct clk timer8_fck = {
2449 .name = "timer8_fck",
2450 .parent = &syc_clk_div_ck,
2451 .clksel = timer5_sync_mux_sel,
2452 .init = &omap2_init_clksel_parent,
2453 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2454 .clksel_mask = OMAP4430_CLKSEL_MASK,
2455 .ops = &clkops_omap2_dflt,
2456 .recalc = &omap2_clksel_recalc,
2457 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2458 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2459 .clkdm_name = "abe_clkdm",
2460 };
2461
2462 /* Merged cm2_dm9_mux into timer9 */
2463 static struct clk timer9_fck = {
2464 .name = "timer9_fck",
2465 .parent = &sys_clkin_ck,
2466 .clksel = abe_dpll_bypass_clk_mux_sel,
2467 .init = &omap2_init_clksel_parent,
2468 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2469 .clksel_mask = OMAP4430_CLKSEL_MASK,
2470 .ops = &clkops_omap2_dflt,
2471 .recalc = &omap2_clksel_recalc,
2472 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2473 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2474 .clkdm_name = "l4_per_clkdm",
2475 };
2476
2477 static struct clk uart1_fck = {
2478 .name = "uart1_fck",
2479 .ops = &clkops_omap2_dflt,
2480 .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2481 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2482 .clkdm_name = "l4_per_clkdm",
2483 .parent = &func_48m_fclk,
2484 .recalc = &followparent_recalc,
2485 };
2486
2487 static struct clk uart2_fck = {
2488 .name = "uart2_fck",
2489 .ops = &clkops_omap2_dflt,
2490 .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2491 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2492 .clkdm_name = "l4_per_clkdm",
2493 .parent = &func_48m_fclk,
2494 .recalc = &followparent_recalc,
2495 };
2496
2497 static struct clk uart3_fck = {
2498 .name = "uart3_fck",
2499 .ops = &clkops_omap2_dflt,
2500 .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2501 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2502 .clkdm_name = "l4_per_clkdm",
2503 .parent = &func_48m_fclk,
2504 .recalc = &followparent_recalc,
2505 };
2506
2507 static struct clk uart4_fck = {
2508 .name = "uart4_fck",
2509 .ops = &clkops_omap2_dflt,
2510 .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2511 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2512 .clkdm_name = "l4_per_clkdm",
2513 .parent = &func_48m_fclk,
2514 .recalc = &followparent_recalc,
2515 };
2516
2517 static struct clk usb_host_fs_fck = {
2518 .name = "usb_host_fs_fck",
2519 .ops = &clkops_omap2_dflt,
2520 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2521 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2522 .clkdm_name = "l3_init_clkdm",
2523 .parent = &func_48mc_fclk,
2524 .recalc = &followparent_recalc,
2525 };
2526
2527 static const struct clksel utmi_p1_gfclk_sel[] = {
2528 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2529 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2530 { .parent = NULL },
2531 };
2532
2533 static struct clk utmi_p1_gfclk = {
2534 .name = "utmi_p1_gfclk",
2535 .parent = &init_60m_fclk,
2536 .clksel = utmi_p1_gfclk_sel,
2537 .init = &omap2_init_clksel_parent,
2538 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2539 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
2540 .ops = &clkops_null,
2541 .recalc = &omap2_clksel_recalc,
2542 };
2543
2544 static struct clk usb_host_hs_utmi_p1_clk = {
2545 .name = "usb_host_hs_utmi_p1_clk",
2546 .ops = &clkops_omap2_dflt,
2547 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2548 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2549 .clkdm_name = "l3_init_clkdm",
2550 .parent = &utmi_p1_gfclk,
2551 .recalc = &followparent_recalc,
2552 };
2553
2554 static const struct clksel utmi_p2_gfclk_sel[] = {
2555 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2556 { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2557 { .parent = NULL },
2558 };
2559
2560 static struct clk utmi_p2_gfclk = {
2561 .name = "utmi_p2_gfclk",
2562 .parent = &init_60m_fclk,
2563 .clksel = utmi_p2_gfclk_sel,
2564 .init = &omap2_init_clksel_parent,
2565 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2566 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
2567 .ops = &clkops_null,
2568 .recalc = &omap2_clksel_recalc,
2569 };
2570
2571 static struct clk usb_host_hs_utmi_p2_clk = {
2572 .name = "usb_host_hs_utmi_p2_clk",
2573 .ops = &clkops_omap2_dflt,
2574 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2575 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2576 .clkdm_name = "l3_init_clkdm",
2577 .parent = &utmi_p2_gfclk,
2578 .recalc = &followparent_recalc,
2579 };
2580
2581 static struct clk usb_host_hs_utmi_p3_clk = {
2582 .name = "usb_host_hs_utmi_p3_clk",
2583 .ops = &clkops_omap2_dflt,
2584 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2585 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2586 .clkdm_name = "l3_init_clkdm",
2587 .parent = &init_60m_fclk,
2588 .recalc = &followparent_recalc,
2589 };
2590
2591 static struct clk usb_host_hs_hsic480m_p1_clk = {
2592 .name = "usb_host_hs_hsic480m_p1_clk",
2593 .ops = &clkops_omap2_dflt,
2594 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2595 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2596 .clkdm_name = "l3_init_clkdm",
2597 .parent = &dpll_usb_m2_ck,
2598 .recalc = &followparent_recalc,
2599 };
2600
2601 static struct clk usb_host_hs_hsic60m_p1_clk = {
2602 .name = "usb_host_hs_hsic60m_p1_clk",
2603 .ops = &clkops_omap2_dflt,
2604 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2605 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2606 .clkdm_name = "l3_init_clkdm",
2607 .parent = &init_60m_fclk,
2608 .recalc = &followparent_recalc,
2609 };
2610
2611 static struct clk usb_host_hs_hsic60m_p2_clk = {
2612 .name = "usb_host_hs_hsic60m_p2_clk",
2613 .ops = &clkops_omap2_dflt,
2614 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2615 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2616 .clkdm_name = "l3_init_clkdm",
2617 .parent = &init_60m_fclk,
2618 .recalc = &followparent_recalc,
2619 };
2620
2621 static struct clk usb_host_hs_hsic480m_p2_clk = {
2622 .name = "usb_host_hs_hsic480m_p2_clk",
2623 .ops = &clkops_omap2_dflt,
2624 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2625 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2626 .clkdm_name = "l3_init_clkdm",
2627 .parent = &dpll_usb_m2_ck,
2628 .recalc = &followparent_recalc,
2629 };
2630
2631 static struct clk usb_host_hs_func48mclk = {
2632 .name = "usb_host_hs_func48mclk",
2633 .ops = &clkops_omap2_dflt,
2634 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2635 .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2636 .clkdm_name = "l3_init_clkdm",
2637 .parent = &func_48mc_fclk,
2638 .recalc = &followparent_recalc,
2639 };
2640
2641 static struct clk usb_host_hs_fck = {
2642 .name = "usb_host_hs_fck",
2643 .ops = &clkops_omap2_dflt,
2644 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2645 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2646 .clkdm_name = "l3_init_clkdm",
2647 .parent = &init_60m_fclk,
2648 .recalc = &followparent_recalc,
2649 };
2650
2651 static const struct clksel otg_60m_gfclk_sel[] = {
2652 { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2653 { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2654 { .parent = NULL },
2655 };
2656
2657 static struct clk otg_60m_gfclk = {
2658 .name = "otg_60m_gfclk",
2659 .parent = &utmi_phy_clkout_ck,
2660 .clksel = otg_60m_gfclk_sel,
2661 .init = &omap2_init_clksel_parent,
2662 .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2663 .clksel_mask = OMAP4430_CLKSEL_60M_MASK,
2664 .ops = &clkops_null,
2665 .recalc = &omap2_clksel_recalc,
2666 };
2667
2668 static struct clk usb_otg_hs_xclk = {
2669 .name = "usb_otg_hs_xclk",
2670 .ops = &clkops_omap2_dflt,
2671 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2672 .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2673 .clkdm_name = "l3_init_clkdm",
2674 .parent = &otg_60m_gfclk,
2675 .recalc = &followparent_recalc,
2676 };
2677
2678 static struct clk usb_otg_hs_ick = {
2679 .name = "usb_otg_hs_ick",
2680 .ops = &clkops_omap2_dflt,
2681 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2682 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2683 .clkdm_name = "l3_init_clkdm",
2684 .parent = &l3_div_ck,
2685 .recalc = &followparent_recalc,
2686 };
2687
2688 static struct clk usb_phy_cm_clk32k = {
2689 .name = "usb_phy_cm_clk32k",
2690 .ops = &clkops_omap2_dflt,
2691 .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2692 .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2693 .clkdm_name = "l4_ao_clkdm",
2694 .parent = &sys_32k_ck,
2695 .recalc = &followparent_recalc,
2696 };
2697
2698 static struct clk usb_tll_hs_usb_ch2_clk = {
2699 .name = "usb_tll_hs_usb_ch2_clk",
2700 .ops = &clkops_omap2_dflt,
2701 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2702 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2703 .clkdm_name = "l3_init_clkdm",
2704 .parent = &init_60m_fclk,
2705 .recalc = &followparent_recalc,
2706 };
2707
2708 static struct clk usb_tll_hs_usb_ch0_clk = {
2709 .name = "usb_tll_hs_usb_ch0_clk",
2710 .ops = &clkops_omap2_dflt,
2711 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2712 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2713 .clkdm_name = "l3_init_clkdm",
2714 .parent = &init_60m_fclk,
2715 .recalc = &followparent_recalc,
2716 };
2717
2718 static struct clk usb_tll_hs_usb_ch1_clk = {
2719 .name = "usb_tll_hs_usb_ch1_clk",
2720 .ops = &clkops_omap2_dflt,
2721 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2722 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2723 .clkdm_name = "l3_init_clkdm",
2724 .parent = &init_60m_fclk,
2725 .recalc = &followparent_recalc,
2726 };
2727
2728 static struct clk usb_tll_hs_ick = {
2729 .name = "usb_tll_hs_ick",
2730 .ops = &clkops_omap2_dflt,
2731 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2732 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2733 .clkdm_name = "l3_init_clkdm",
2734 .parent = &l4_div_ck,
2735 .recalc = &followparent_recalc,
2736 };
2737
2738 static const struct clksel_rate div2_14to18_rates[] = {
2739 { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2740 { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2741 { .div = 0 },
2742 };
2743
2744 static const struct clksel usim_fclk_div[] = {
2745 { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
2746 { .parent = NULL },
2747 };
2748
2749 static struct clk usim_ck = {
2750 .name = "usim_ck",
2751 .parent = &dpll_per_m4x2_ck,
2752 .clksel = usim_fclk_div,
2753 .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2754 .clksel_mask = OMAP4430_CLKSEL_DIV_MASK,
2755 .ops = &clkops_null,
2756 .recalc = &omap2_clksel_recalc,
2757 .round_rate = &omap2_clksel_round_rate,
2758 .set_rate = &omap2_clksel_set_rate,
2759 };
2760
2761 static struct clk usim_fclk = {
2762 .name = "usim_fclk",
2763 .ops = &clkops_omap2_dflt,
2764 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2765 .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2766 .clkdm_name = "l4_wkup_clkdm",
2767 .parent = &usim_ck,
2768 .recalc = &followparent_recalc,
2769 };
2770
2771 static struct clk usim_fck = {
2772 .name = "usim_fck",
2773 .ops = &clkops_omap2_dflt,
2774 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2775 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2776 .clkdm_name = "l4_wkup_clkdm",
2777 .parent = &sys_32k_ck,
2778 .recalc = &followparent_recalc,
2779 };
2780
2781 static struct clk wd_timer2_fck = {
2782 .name = "wd_timer2_fck",
2783 .ops = &clkops_omap2_dflt,
2784 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2785 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2786 .clkdm_name = "l4_wkup_clkdm",
2787 .parent = &sys_32k_ck,
2788 .recalc = &followparent_recalc,
2789 };
2790
2791 static struct clk wd_timer3_fck = {
2792 .name = "wd_timer3_fck",
2793 .ops = &clkops_omap2_dflt,
2794 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2795 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2796 .clkdm_name = "abe_clkdm",
2797 .parent = &sys_32k_ck,
2798 .recalc = &followparent_recalc,
2799 };
2800
2801 /* Remaining optional clocks */
2802 static const struct clksel stm_clk_div_div[] = {
2803 { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2804 { .parent = NULL },
2805 };
2806
2807 static struct clk stm_clk_div_ck = {
2808 .name = "stm_clk_div_ck",
2809 .parent = &pmd_stm_clock_mux_ck,
2810 .clksel = stm_clk_div_div,
2811 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2812 .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2813 .ops = &clkops_null,
2814 .recalc = &omap2_clksel_recalc,
2815 .round_rate = &omap2_clksel_round_rate,
2816 .set_rate = &omap2_clksel_set_rate,
2817 };
2818
2819 static const struct clksel trace_clk_div_div[] = {
2820 { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2821 { .parent = NULL },
2822 };
2823
2824 static struct clk trace_clk_div_ck = {
2825 .name = "trace_clk_div_ck",
2826 .parent = &pmd_trace_clk_mux_ck,
2827 .clksel = trace_clk_div_div,
2828 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2829 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2830 .ops = &clkops_null,
2831 .recalc = &omap2_clksel_recalc,
2832 .round_rate = &omap2_clksel_round_rate,
2833 .set_rate = &omap2_clksel_set_rate,
2834 };
2835
2836 /* SCRM aux clk nodes */
2837
2838 static const struct clksel auxclk_src_sel[] = {
2839 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2840 { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2841 { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2842 { .parent = NULL },
2843 };
2844
2845 static const struct clksel_rate div16_1to16_rates[] = {
2846 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
2847 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
2848 { .div = 3, .val = 2, .flags = RATE_IN_4430 },
2849 { .div = 4, .val = 3, .flags = RATE_IN_4430 },
2850 { .div = 5, .val = 4, .flags = RATE_IN_4430 },
2851 { .div = 6, .val = 5, .flags = RATE_IN_4430 },
2852 { .div = 7, .val = 6, .flags = RATE_IN_4430 },
2853 { .div = 8, .val = 7, .flags = RATE_IN_4430 },
2854 { .div = 9, .val = 8, .flags = RATE_IN_4430 },
2855 { .div = 10, .val = 9, .flags = RATE_IN_4430 },
2856 { .div = 11, .val = 10, .flags = RATE_IN_4430 },
2857 { .div = 12, .val = 11, .flags = RATE_IN_4430 },
2858 { .div = 13, .val = 12, .flags = RATE_IN_4430 },
2859 { .div = 14, .val = 13, .flags = RATE_IN_4430 },
2860 { .div = 15, .val = 14, .flags = RATE_IN_4430 },
2861 { .div = 16, .val = 15, .flags = RATE_IN_4430 },
2862 { .div = 0 },
2863 };
2864
2865 static struct clk auxclk0_src_ck = {
2866 .name = "auxclk0_src_ck",
2867 .parent = &sys_clkin_ck,
2868 .init = &omap2_init_clksel_parent,
2869 .ops = &clkops_omap2_dflt,
2870 .clksel = auxclk_src_sel,
2871 .clksel_reg = OMAP4_SCRM_AUXCLK0,
2872 .clksel_mask = OMAP4_SRCSELECT_MASK,
2873 .recalc = &omap2_clksel_recalc,
2874 .enable_reg = OMAP4_SCRM_AUXCLK0,
2875 .enable_bit = OMAP4_ENABLE_SHIFT,
2876 };
2877
2878 static const struct clksel auxclk0_sel[] = {
2879 { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates },
2880 { .parent = NULL },
2881 };
2882
2883 static struct clk auxclk0_ck = {
2884 .name = "auxclk0_ck",
2885 .parent = &auxclk0_src_ck,
2886 .clksel = auxclk0_sel,
2887 .clksel_reg = OMAP4_SCRM_AUXCLK0,
2888 .clksel_mask = OMAP4_CLKDIV_MASK,
2889 .ops = &clkops_null,
2890 .recalc = &omap2_clksel_recalc,
2891 .round_rate = &omap2_clksel_round_rate,
2892 .set_rate = &omap2_clksel_set_rate,
2893 };
2894
2895 static struct clk auxclk1_src_ck = {
2896 .name = "auxclk1_src_ck",
2897 .parent = &sys_clkin_ck,
2898 .init = &omap2_init_clksel_parent,
2899 .ops = &clkops_omap2_dflt,
2900 .clksel = auxclk_src_sel,
2901 .clksel_reg = OMAP4_SCRM_AUXCLK1,
2902 .clksel_mask = OMAP4_SRCSELECT_MASK,
2903 .recalc = &omap2_clksel_recalc,
2904 .enable_reg = OMAP4_SCRM_AUXCLK1,
2905 .enable_bit = OMAP4_ENABLE_SHIFT,
2906 };
2907
2908 static const struct clksel auxclk1_sel[] = {
2909 { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates },
2910 { .parent = NULL },
2911 };
2912
2913 static struct clk auxclk1_ck = {
2914 .name = "auxclk1_ck",
2915 .parent = &auxclk1_src_ck,
2916 .clksel = auxclk1_sel,
2917 .clksel_reg = OMAP4_SCRM_AUXCLK1,
2918 .clksel_mask = OMAP4_CLKDIV_MASK,
2919 .ops = &clkops_null,
2920 .recalc = &omap2_clksel_recalc,
2921 .round_rate = &omap2_clksel_round_rate,
2922 .set_rate = &omap2_clksel_set_rate,
2923 };
2924
2925 static struct clk auxclk2_src_ck = {
2926 .name = "auxclk2_src_ck",
2927 .parent = &sys_clkin_ck,
2928 .init = &omap2_init_clksel_parent,
2929 .ops = &clkops_omap2_dflt,
2930 .clksel = auxclk_src_sel,
2931 .clksel_reg = OMAP4_SCRM_AUXCLK2,
2932 .clksel_mask = OMAP4_SRCSELECT_MASK,
2933 .recalc = &omap2_clksel_recalc,
2934 .enable_reg = OMAP4_SCRM_AUXCLK2,
2935 .enable_bit = OMAP4_ENABLE_SHIFT,
2936 };
2937
2938 static const struct clksel auxclk2_sel[] = {
2939 { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates },
2940 { .parent = NULL },
2941 };
2942
2943 static struct clk auxclk2_ck = {
2944 .name = "auxclk2_ck",
2945 .parent = &auxclk2_src_ck,
2946 .clksel = auxclk2_sel,
2947 .clksel_reg = OMAP4_SCRM_AUXCLK2,
2948 .clksel_mask = OMAP4_CLKDIV_MASK,
2949 .ops = &clkops_null,
2950 .recalc = &omap2_clksel_recalc,
2951 .round_rate = &omap2_clksel_round_rate,
2952 .set_rate = &omap2_clksel_set_rate,
2953 };
2954
2955 static struct clk auxclk3_src_ck = {
2956 .name = "auxclk3_src_ck",
2957 .parent = &sys_clkin_ck,
2958 .init = &omap2_init_clksel_parent,
2959 .ops = &clkops_omap2_dflt,
2960 .clksel = auxclk_src_sel,
2961 .clksel_reg = OMAP4_SCRM_AUXCLK3,
2962 .clksel_mask = OMAP4_SRCSELECT_MASK,
2963 .recalc = &omap2_clksel_recalc,
2964 .enable_reg = OMAP4_SCRM_AUXCLK3,
2965 .enable_bit = OMAP4_ENABLE_SHIFT,
2966 };
2967
2968 static const struct clksel auxclk3_sel[] = {
2969 { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates },
2970 { .parent = NULL },
2971 };
2972
2973 static struct clk auxclk3_ck = {
2974 .name = "auxclk3_ck",
2975 .parent = &auxclk3_src_ck,
2976 .clksel = auxclk3_sel,
2977 .clksel_reg = OMAP4_SCRM_AUXCLK3,
2978 .clksel_mask = OMAP4_CLKDIV_MASK,
2979 .ops = &clkops_null,
2980 .recalc = &omap2_clksel_recalc,
2981 .round_rate = &omap2_clksel_round_rate,
2982 .set_rate = &omap2_clksel_set_rate,
2983 };
2984
2985 static struct clk auxclk4_src_ck = {
2986 .name = "auxclk4_src_ck",
2987 .parent = &sys_clkin_ck,
2988 .init = &omap2_init_clksel_parent,
2989 .ops = &clkops_omap2_dflt,
2990 .clksel = auxclk_src_sel,
2991 .clksel_reg = OMAP4_SCRM_AUXCLK4,
2992 .clksel_mask = OMAP4_SRCSELECT_MASK,
2993 .recalc = &omap2_clksel_recalc,
2994 .enable_reg = OMAP4_SCRM_AUXCLK4,
2995 .enable_bit = OMAP4_ENABLE_SHIFT,
2996 };
2997
2998 static const struct clksel auxclk4_sel[] = {
2999 { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates },
3000 { .parent = NULL },
3001 };
3002
3003 static struct clk auxclk4_ck = {
3004 .name = "auxclk4_ck",
3005 .parent = &auxclk4_src_ck,
3006 .clksel = auxclk4_sel,
3007 .clksel_reg = OMAP4_SCRM_AUXCLK4,
3008 .clksel_mask = OMAP4_CLKDIV_MASK,
3009 .ops = &clkops_null,
3010 .recalc = &omap2_clksel_recalc,
3011 .round_rate = &omap2_clksel_round_rate,
3012 .set_rate = &omap2_clksel_set_rate,
3013 };
3014
3015 static struct clk auxclk5_src_ck = {
3016 .name = "auxclk5_src_ck",
3017 .parent = &sys_clkin_ck,
3018 .init = &omap2_init_clksel_parent,
3019 .ops = &clkops_omap2_dflt,
3020 .clksel = auxclk_src_sel,
3021 .clksel_reg = OMAP4_SCRM_AUXCLK5,
3022 .clksel_mask = OMAP4_SRCSELECT_MASK,
3023 .recalc = &omap2_clksel_recalc,
3024 .enable_reg = OMAP4_SCRM_AUXCLK5,
3025 .enable_bit = OMAP4_ENABLE_SHIFT,
3026 };
3027
3028 static const struct clksel auxclk5_sel[] = {
3029 { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates },
3030 { .parent = NULL },
3031 };
3032
3033 static struct clk auxclk5_ck = {
3034 .name = "auxclk5_ck",
3035 .parent = &auxclk5_src_ck,
3036 .clksel = auxclk5_sel,
3037 .clksel_reg = OMAP4_SCRM_AUXCLK5,
3038 .clksel_mask = OMAP4_CLKDIV_MASK,
3039 .ops = &clkops_null,
3040 .recalc = &omap2_clksel_recalc,
3041 .round_rate = &omap2_clksel_round_rate,
3042 .set_rate = &omap2_clksel_set_rate,
3043 };
3044
3045 static const struct clksel auxclkreq_sel[] = {
3046 { .parent = &auxclk0_ck, .rates = div_1_0_rates },
3047 { .parent = &auxclk1_ck, .rates = div_1_1_rates },
3048 { .parent = &auxclk2_ck, .rates = div_1_2_rates },
3049 { .parent = &auxclk3_ck, .rates = div_1_3_rates },
3050 { .parent = &auxclk4_ck, .rates = div_1_4_rates },
3051 { .parent = &auxclk5_ck, .rates = div_1_5_rates },
3052 { .parent = NULL },
3053 };
3054
3055 static struct clk auxclkreq0_ck = {
3056 .name = "auxclkreq0_ck",
3057 .parent = &auxclk0_ck,
3058 .init = &omap2_init_clksel_parent,
3059 .ops = &clkops_null,
3060 .clksel = auxclkreq_sel,
3061 .clksel_reg = OMAP4_SCRM_AUXCLKREQ0,
3062 .clksel_mask = OMAP4_MAPPING_MASK,
3063 .recalc = &omap2_clksel_recalc,
3064 };
3065
3066 static struct clk auxclkreq1_ck = {
3067 .name = "auxclkreq1_ck",
3068 .parent = &auxclk1_ck,
3069 .init = &omap2_init_clksel_parent,
3070 .ops = &clkops_null,
3071 .clksel = auxclkreq_sel,
3072 .clksel_reg = OMAP4_SCRM_AUXCLKREQ1,
3073 .clksel_mask = OMAP4_MAPPING_MASK,
3074 .recalc = &omap2_clksel_recalc,
3075 };
3076
3077 static struct clk auxclkreq2_ck = {
3078 .name = "auxclkreq2_ck",
3079 .parent = &auxclk2_ck,
3080 .init = &omap2_init_clksel_parent,
3081 .ops = &clkops_null,
3082 .clksel = auxclkreq_sel,
3083 .clksel_reg = OMAP4_SCRM_AUXCLKREQ2,
3084 .clksel_mask = OMAP4_MAPPING_MASK,
3085 .recalc = &omap2_clksel_recalc,
3086 };
3087
3088 static struct clk auxclkreq3_ck = {
3089 .name = "auxclkreq3_ck",
3090 .parent = &auxclk3_ck,
3091 .init = &omap2_init_clksel_parent,
3092 .ops = &clkops_null,
3093 .clksel = auxclkreq_sel,
3094 .clksel_reg = OMAP4_SCRM_AUXCLKREQ3,
3095 .clksel_mask = OMAP4_MAPPING_MASK,
3096 .recalc = &omap2_clksel_recalc,
3097 };
3098
3099 static struct clk auxclkreq4_ck = {
3100 .name = "auxclkreq4_ck",
3101 .parent = &auxclk4_ck,
3102 .init = &omap2_init_clksel_parent,
3103 .ops = &clkops_null,
3104 .clksel = auxclkreq_sel,
3105 .clksel_reg = OMAP4_SCRM_AUXCLKREQ4,
3106 .clksel_mask = OMAP4_MAPPING_MASK,
3107 .recalc = &omap2_clksel_recalc,
3108 };
3109
3110 static struct clk auxclkreq5_ck = {
3111 .name = "auxclkreq5_ck",
3112 .parent = &auxclk5_ck,
3113 .init = &omap2_init_clksel_parent,
3114 .ops = &clkops_null,
3115 .clksel = auxclkreq_sel,
3116 .clksel_reg = OMAP4_SCRM_AUXCLKREQ5,
3117 .clksel_mask = OMAP4_MAPPING_MASK,
3118 .recalc = &omap2_clksel_recalc,
3119 };
3120
3121 /*
3122 * clkdev
3123 */
3124
3125 static struct omap_clk omap44xx_clks[] = {
3126 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X),
3127 CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X),
3128 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X),
3129 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X),
3130 CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X),
3131 CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X),
3132 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X),
3133 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X),
3134 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X),
3135 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X),
3136 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X),
3137 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X),
3138 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X),
3139 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X),
3140 CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X),
3141 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X),
3142 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X),
3143 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X),
3144 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X),
3145 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X),
3146 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
3147 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
3148 CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X),
3149 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
3150 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X),
3151 CLK(NULL, "abe_clk", &abe_clk, CK_443X),
3152 CLK(NULL, "aess_fclk", &aess_fclk, CK_443X),
3153 CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X),
3154 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X),
3155 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X),
3156 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X),
3157 CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X),
3158 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X),
3159 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X),
3160 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X),
3161 CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X),
3162 CLK(NULL, "div_core_ck", &div_core_ck, CK_443X),
3163 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X),
3164 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X),
3165 CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X),
3166 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X),
3167 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X),
3168 CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X),
3169 CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X),
3170 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X),
3171 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X),
3172 CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X),
3173 CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X),
3174 CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X),
3175 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X),
3176 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X),
3177 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X),
3178 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X),
3179 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X),
3180 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X),
3181 CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X),
3182 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X),
3183 CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X),
3184 CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X),
3185 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
3186 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
3187 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
3188 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
3189 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
3190 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
3191 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X),
3192 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X),
3193 CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X),
3194 CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X),
3195 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X),
3196 CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X),
3197 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
3198 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
3199 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
3200 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
3201 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
3202 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
3203 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
3204 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
3205 CLK("smp_twd", NULL, &mpu_periphclk, CK_443X),
3206 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
3207 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
3208 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
3209 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
3210 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
3211 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
3212 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
3213 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
3214 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
3215 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
3216 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
3217 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
3218 CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
3219 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
3220 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
3221 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
3222 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
3223 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
3224 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
3225 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
3226 CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
3227 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
3228 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
3229 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
3230 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
3231 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
3232 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X),
3233 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
3234 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X),
3235 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
3236 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X),
3237 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
3238 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X),
3239 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
3240 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X),
3241 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
3242 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X),
3243 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
3244 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
3245 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
3246 CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X),
3247 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
3248 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X),
3249 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X),
3250 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X),
3251 CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X),
3252 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
3253 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
3254 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
3255 CLK(NULL, "iva_fck", &iva_fck, CK_443X),
3256 CLK(NULL, "kbd_fck", &kbd_fck, CK_443X),
3257 CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X),
3258 CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X),
3259 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
3260 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
3261 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
3262 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X),
3263 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
3264 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X),
3265 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
3266 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X),
3267 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
3268 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X),
3269 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
3270 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X),
3271 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X),
3272 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X),
3273 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X),
3274 CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X),
3275 CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X),
3276 CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X),
3277 CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X),
3278 CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X),
3279 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
3280 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
3281 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
3282 CLK("omap_rng", "ick", &rng_ick, CK_443X),
3283 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
3284 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
3285 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
3286 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
3287 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
3288 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
3289 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
3290 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
3291 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
3292 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
3293 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
3294 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
3295 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
3296 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
3297 CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X),
3298 CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X),
3299 CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X),
3300 CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X),
3301 CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X),
3302 CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X),
3303 CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X),
3304 CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X),
3305 CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X),
3306 CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X),
3307 CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X),
3308 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
3309 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
3310 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
3311 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
3312 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X),
3313 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
3314 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
3315 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
3316 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X),
3317 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
3318 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X),
3319 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
3320 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
3321 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
3322 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
3323 CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X),
3324 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
3325 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
3326 CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
3327 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X),
3328 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
3329 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
3330 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
3331 CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
3332 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
3333 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
3334 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
3335 CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X),
3336 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
3337 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
3338 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
3339 CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X),
3340 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
3341 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
3342 CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X),
3343 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
3344 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
3345 CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X),
3346 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
3347 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
3348 CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X),
3349 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
3350 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
3351 CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X),
3352 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
3353 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
3354 CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X),
3355 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
3356 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
3357 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
3358 CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X),
3359 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
3360 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
3361 CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
3362 CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
3363 CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
3364 CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
3365 CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
3366 CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X),
3367 CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X),
3368 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
3369 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
3370 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
3371 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
3372 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
3373 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
3374 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
3375 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
3376 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
3377 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
3378 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
3379 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
3380 CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X),
3381 CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X),
3382 CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
3383 CLK("omap_timer.1", "32k_ck", &sys_32k_ck, CK_443X),
3384 CLK("omap_timer.2", "32k_ck", &sys_32k_ck, CK_443X),
3385 CLK("omap_timer.3", "32k_ck", &sys_32k_ck, CK_443X),
3386 CLK("omap_timer.4", "32k_ck", &sys_32k_ck, CK_443X),
3387 CLK("omap_timer.5", "32k_ck", &sys_32k_ck, CK_443X),
3388 CLK("omap_timer.6", "32k_ck", &sys_32k_ck, CK_443X),
3389 CLK("omap_timer.7", "32k_ck", &sys_32k_ck, CK_443X),
3390 CLK("omap_timer.8", "32k_ck", &sys_32k_ck, CK_443X),
3391 CLK("omap_timer.9", "32k_ck", &sys_32k_ck, CK_443X),
3392 CLK("omap_timer.10", "32k_ck", &sys_32k_ck, CK_443X),
3393 CLK("omap_timer.11", "32k_ck", &sys_32k_ck, CK_443X),
3394 CLK("omap_timer.1", "sys_ck", &sys_clkin_ck, CK_443X),
3395 CLK("omap_timer.2", "sys_ck", &sys_clkin_ck, CK_443X),
3396 CLK("omap_timer.3", "sys_ck", &sys_clkin_ck, CK_443X),
3397 CLK("omap_timer.4", "sys_ck", &sys_clkin_ck, CK_443X),
3398 CLK("omap_timer.9", "sys_ck", &sys_clkin_ck, CK_443X),
3399 CLK("omap_timer.10", "sys_ck", &sys_clkin_ck, CK_443X),
3400 CLK("omap_timer.11", "sys_ck", &sys_clkin_ck, CK_443X),
3401 CLK("omap_timer.5", "sys_ck", &syc_clk_div_ck, CK_443X),
3402 CLK("omap_timer.6", "sys_ck", &syc_clk_div_ck, CK_443X),
3403 CLK("omap_timer.7", "sys_ck", &syc_clk_div_ck, CK_443X),
3404 CLK("omap_timer.8", "sys_ck", &syc_clk_div_ck, CK_443X),
3405 };
3406
3407 int __init omap4xxx_clk_init(void)
3408 {
3409 struct omap_clk *c;
3410 u32 cpu_clkflg;
3411
3412 if (cpu_is_omap443x()) {
3413 cpu_mask = RATE_IN_4430;
3414 cpu_clkflg = CK_443X;
3415 } else if (cpu_is_omap446x()) {
3416 cpu_mask = RATE_IN_4460 | RATE_IN_4430;
3417 cpu_clkflg = CK_446X | CK_443X;
3418 } else {
3419 return 0;
3420 }
3421
3422 clk_init(&omap2_clk_functions);
3423
3424 /*
3425 * Must stay commented until all OMAP SoC drivers are
3426 * converted to runtime PM, or drivers may start crashing
3427 *
3428 * omap2_clk_disable_clkdm_control();
3429 */
3430
3431 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3432 c++)
3433 clk_preinit(c->lk.clk);
3434
3435 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3436 c++)
3437 if (c->cpu & cpu_clkflg) {
3438 clkdev_add(&c->lk);
3439 clk_register(c->lk.clk);
3440 omap2_init_clk_clkdm(c->lk.clk);
3441 }
3442
3443 /* Disable autoidle on all clocks; let the PM code enable it later */
3444 omap_clk_disable_autoidle_all();
3445
3446 recalculate_root_clocks();
3447
3448 /*
3449 * Only enable those clocks we will need, let the drivers
3450 * enable other clocks as necessary
3451 */
3452 clk_enable_init_clocks();
3453
3454 return 0;
3455 }
Linux kernel - Deliverables
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