4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
21 * XXX Some of the ES1 clocks have been removed/changed; once support
22 * is added for discriminating clocks by ES level, these should be added back
26 #include <linux/kernel.h>
27 #include <linux/list.h>
28 #include <linux/clk.h>
31 #include <plat/hardware.h>
32 #include <plat/clkdev_omap.h>
36 #include "clock44xx.h"
39 #include "cm-regbits-44xx.h"
41 #include "prm-regbits-44xx.h"
45 /* OMAP4 modulemode control */
46 #define OMAP4430_MODULEMODE_HWCTRL 0
47 #define OMAP4430_MODULEMODE_SWCTRL 1
51 static struct clk extalt_clkin_ck
= {
52 .name
= "extalt_clkin_ck",
57 static struct clk pad_clks_ck
= {
58 .name
= "pad_clks_ck",
60 .ops
= &clkops_omap2_dflt
,
61 .enable_reg
= OMAP4430_CM_CLKSEL_ABE
,
62 .enable_bit
= OMAP4430_PAD_CLKS_GATE_SHIFT
,
65 static struct clk pad_slimbus_core_clks_ck
= {
66 .name
= "pad_slimbus_core_clks_ck",
71 static struct clk secure_32k_clk_src_ck
= {
72 .name
= "secure_32k_clk_src_ck",
77 static struct clk slimbus_clk
= {
78 .name
= "slimbus_clk",
80 .ops
= &clkops_omap2_dflt
,
81 .enable_reg
= OMAP4430_CM_CLKSEL_ABE
,
82 .enable_bit
= OMAP4430_SLIMBUS_CLK_GATE_SHIFT
,
85 static struct clk sys_32k_ck
= {
87 .clkdm_name
= "prm_clkdm",
92 static struct clk virt_12000000_ck
= {
93 .name
= "virt_12000000_ck",
98 static struct clk virt_13000000_ck
= {
99 .name
= "virt_13000000_ck",
104 static struct clk virt_16800000_ck
= {
105 .name
= "virt_16800000_ck",
110 static struct clk virt_19200000_ck
= {
111 .name
= "virt_19200000_ck",
116 static struct clk virt_26000000_ck
= {
117 .name
= "virt_26000000_ck",
122 static struct clk virt_27000000_ck
= {
123 .name
= "virt_27000000_ck",
128 static struct clk virt_38400000_ck
= {
129 .name
= "virt_38400000_ck",
134 static const struct clksel_rate div_1_0_rates
[] = {
135 { .div
= 1, .val
= 0, .flags
= RATE_IN_4430
},
139 static const struct clksel_rate div_1_1_rates
[] = {
140 { .div
= 1, .val
= 1, .flags
= RATE_IN_4430
},
144 static const struct clksel_rate div_1_2_rates
[] = {
145 { .div
= 1, .val
= 2, .flags
= RATE_IN_4430
},
149 static const struct clksel_rate div_1_3_rates
[] = {
150 { .div
= 1, .val
= 3, .flags
= RATE_IN_4430
},
154 static const struct clksel_rate div_1_4_rates
[] = {
155 { .div
= 1, .val
= 4, .flags
= RATE_IN_4430
},
159 static const struct clksel_rate div_1_5_rates
[] = {
160 { .div
= 1, .val
= 5, .flags
= RATE_IN_4430
},
164 static const struct clksel_rate div_1_6_rates
[] = {
165 { .div
= 1, .val
= 6, .flags
= RATE_IN_4430
},
169 static const struct clksel_rate div_1_7_rates
[] = {
170 { .div
= 1, .val
= 7, .flags
= RATE_IN_4430
},
174 static const struct clksel sys_clkin_sel
[] = {
175 { .parent
= &virt_12000000_ck
, .rates
= div_1_1_rates
},
176 { .parent
= &virt_13000000_ck
, .rates
= div_1_2_rates
},
177 { .parent
= &virt_16800000_ck
, .rates
= div_1_3_rates
},
178 { .parent
= &virt_19200000_ck
, .rates
= div_1_4_rates
},
179 { .parent
= &virt_26000000_ck
, .rates
= div_1_5_rates
},
180 { .parent
= &virt_27000000_ck
, .rates
= div_1_6_rates
},
181 { .parent
= &virt_38400000_ck
, .rates
= div_1_7_rates
},
185 static struct clk sys_clkin_ck
= {
186 .name
= "sys_clkin_ck",
188 .clksel
= sys_clkin_sel
,
189 .init
= &omap2_init_clksel_parent
,
190 .clksel_reg
= OMAP4430_CM_SYS_CLKSEL
,
191 .clksel_mask
= OMAP4430_SYS_CLKSEL_MASK
,
193 .recalc
= &omap2_clksel_recalc
,
196 static struct clk tie_low_clock_ck
= {
197 .name
= "tie_low_clock_ck",
202 static struct clk utmi_phy_clkout_ck
= {
203 .name
= "utmi_phy_clkout_ck",
208 static struct clk xclk60mhsp1_ck
= {
209 .name
= "xclk60mhsp1_ck",
214 static struct clk xclk60mhsp2_ck
= {
215 .name
= "xclk60mhsp2_ck",
220 static struct clk xclk60motg_ck
= {
221 .name
= "xclk60motg_ck",
226 /* Module clocks and DPLL outputs */
228 static const struct clksel abe_dpll_bypass_clk_mux_sel
[] = {
229 { .parent
= &sys_clkin_ck
, .rates
= div_1_0_rates
},
230 { .parent
= &sys_32k_ck
, .rates
= div_1_1_rates
},
234 static struct clk abe_dpll_bypass_clk_mux_ck
= {
235 .name
= "abe_dpll_bypass_clk_mux_ck",
236 .parent
= &sys_clkin_ck
,
238 .recalc
= &followparent_recalc
,
241 static struct clk abe_dpll_refclk_mux_ck
= {
242 .name
= "abe_dpll_refclk_mux_ck",
243 .parent
= &sys_clkin_ck
,
244 .clksel
= abe_dpll_bypass_clk_mux_sel
,
245 .init
= &omap2_init_clksel_parent
,
246 .clksel_reg
= OMAP4430_CM_ABE_PLL_REF_CLKSEL
,
247 .clksel_mask
= OMAP4430_CLKSEL_0_0_MASK
,
249 .recalc
= &omap2_clksel_recalc
,
253 static struct dpll_data dpll_abe_dd
= {
254 .mult_div1_reg
= OMAP4430_CM_CLKSEL_DPLL_ABE
,
255 .clk_bypass
= &abe_dpll_bypass_clk_mux_ck
,
256 .clk_ref
= &abe_dpll_refclk_mux_ck
,
257 .control_reg
= OMAP4430_CM_CLKMODE_DPLL_ABE
,
258 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
259 .autoidle_reg
= OMAP4430_CM_AUTOIDLE_DPLL_ABE
,
260 .idlest_reg
= OMAP4430_CM_IDLEST_DPLL_ABE
,
261 .mult_mask
= OMAP4430_DPLL_MULT_MASK
,
262 .div1_mask
= OMAP4430_DPLL_DIV_MASK
,
263 .enable_mask
= OMAP4430_DPLL_EN_MASK
,
264 .autoidle_mask
= OMAP4430_AUTO_DPLL_MODE_MASK
,
265 .idlest_mask
= OMAP4430_ST_DPLL_CLK_MASK
,
266 .max_multiplier
= 2047,
272 static struct clk dpll_abe_ck
= {
273 .name
= "dpll_abe_ck",
274 .parent
= &abe_dpll_refclk_mux_ck
,
275 .dpll_data
= &dpll_abe_dd
,
276 .init
= &omap2_init_dpll_parent
,
277 .ops
= &clkops_omap3_noncore_dpll_ops
,
278 .recalc
= &omap4_dpll_regm4xen_recalc
,
279 .round_rate
= &omap4_dpll_regm4xen_round_rate
,
280 .set_rate
= &omap3_noncore_dpll_set_rate
,
283 static struct clk dpll_abe_x2_ck
= {
284 .name
= "dpll_abe_x2_ck",
285 .parent
= &dpll_abe_ck
,
286 .clksel_reg
= OMAP4430_CM_DIV_M2_DPLL_ABE
,
287 .flags
= CLOCK_CLKOUTX2
,
288 .ops
= &clkops_omap4_dpllmx_ops
,
289 .recalc
= &omap3_clkoutx2_recalc
,
292 static const struct clksel_rate div31_1to31_rates
[] = {
293 { .div
= 1, .val
= 1, .flags
= RATE_IN_4430
},
294 { .div
= 2, .val
= 2, .flags
= RATE_IN_4430
},
295 { .div
= 3, .val
= 3, .flags
= RATE_IN_4430
},
296 { .div
= 4, .val
= 4, .flags
= RATE_IN_4430
},
297 { .div
= 5, .val
= 5, .flags
= RATE_IN_4430
},
298 { .div
= 6, .val
= 6, .flags
= RATE_IN_4430
},
299 { .div
= 7, .val
= 7, .flags
= RATE_IN_4430
},
300 { .div
= 8, .val
= 8, .flags
= RATE_IN_4430
},
301 { .div
= 9, .val
= 9, .flags
= RATE_IN_4430
},
302 { .div
= 10, .val
= 10, .flags
= RATE_IN_4430
},
303 { .div
= 11, .val
= 11, .flags
= RATE_IN_4430
},
304 { .div
= 12, .val
= 12, .flags
= RATE_IN_4430
},
305 { .div
= 13, .val
= 13, .flags
= RATE_IN_4430
},
306 { .div
= 14, .val
= 14, .flags
= RATE_IN_4430
},
307 { .div
= 15, .val
= 15, .flags
= RATE_IN_4430
},
308 { .div
= 16, .val
= 16, .flags
= RATE_IN_4430
},
309 { .div
= 17, .val
= 17, .flags
= RATE_IN_4430
},
310 { .div
= 18, .val
= 18, .flags
= RATE_IN_4430
},
311 { .div
= 19, .val
= 19, .flags
= RATE_IN_4430
},
312 { .div
= 20, .val
= 20, .flags
= RATE_IN_4430
},
313 { .div
= 21, .val
= 21, .flags
= RATE_IN_4430
},
314 { .div
= 22, .val
= 22, .flags
= RATE_IN_4430
},
315 { .div
= 23, .val
= 23, .flags
= RATE_IN_4430
},
316 { .div
= 24, .val
= 24, .flags
= RATE_IN_4430
},
317 { .div
= 25, .val
= 25, .flags
= RATE_IN_4430
},
318 { .div
= 26, .val
= 26, .flags
= RATE_IN_4430
},
319 { .div
= 27, .val
= 27, .flags
= RATE_IN_4430
},
320 { .div
= 28, .val
= 28, .flags
= RATE_IN_4430
},
321 { .div
= 29, .val
= 29, .flags
= RATE_IN_4430
},
322 { .div
= 30, .val
= 30, .flags
= RATE_IN_4430
},
323 { .div
= 31, .val
= 31, .flags
= RATE_IN_4430
},
327 static const struct clksel dpll_abe_m2x2_div
[] = {
328 { .parent
= &dpll_abe_x2_ck
, .rates
= div31_1to31_rates
},
332 static struct clk dpll_abe_m2x2_ck
= {
333 .name
= "dpll_abe_m2x2_ck",
334 .parent
= &dpll_abe_x2_ck
,
335 .clksel
= dpll_abe_m2x2_div
,
336 .clksel_reg
= OMAP4430_CM_DIV_M2_DPLL_ABE
,
337 .clksel_mask
= OMAP4430_DPLL_CLKOUT_DIV_MASK
,
338 .ops
= &clkops_omap4_dpllmx_ops
,
339 .recalc
= &omap2_clksel_recalc
,
340 .round_rate
= &omap2_clksel_round_rate
,
341 .set_rate
= &omap2_clksel_set_rate
,
344 static struct clk abe_24m_fclk
= {
345 .name
= "abe_24m_fclk",
346 .parent
= &dpll_abe_m2x2_ck
,
349 .recalc
= &omap_fixed_divisor_recalc
,
352 static const struct clksel_rate div3_1to4_rates
[] = {
353 { .div
= 1, .val
= 0, .flags
= RATE_IN_4430
},
354 { .div
= 2, .val
= 1, .flags
= RATE_IN_4430
},
355 { .div
= 4, .val
= 2, .flags
= RATE_IN_4430
},
359 static const struct clksel abe_clk_div
[] = {
360 { .parent
= &dpll_abe_m2x2_ck
, .rates
= div3_1to4_rates
},
364 static struct clk abe_clk
= {
366 .parent
= &dpll_abe_m2x2_ck
,
367 .clksel
= abe_clk_div
,
368 .clksel_reg
= OMAP4430_CM_CLKSEL_ABE
,
369 .clksel_mask
= OMAP4430_CLKSEL_OPP_MASK
,
371 .recalc
= &omap2_clksel_recalc
,
372 .round_rate
= &omap2_clksel_round_rate
,
373 .set_rate
= &omap2_clksel_set_rate
,
376 static const struct clksel_rate div2_1to2_rates
[] = {
377 { .div
= 1, .val
= 0, .flags
= RATE_IN_4430
},
378 { .div
= 2, .val
= 1, .flags
= RATE_IN_4430
},
382 static const struct clksel aess_fclk_div
[] = {
383 { .parent
= &abe_clk
, .rates
= div2_1to2_rates
},
387 static struct clk aess_fclk
= {
390 .clksel
= aess_fclk_div
,
391 .clksel_reg
= OMAP4430_CM1_ABE_AESS_CLKCTRL
,
392 .clksel_mask
= OMAP4430_CLKSEL_AESS_FCLK_MASK
,
394 .recalc
= &omap2_clksel_recalc
,
395 .round_rate
= &omap2_clksel_round_rate
,
396 .set_rate
= &omap2_clksel_set_rate
,
399 static struct clk dpll_abe_m3x2_ck
= {
400 .name
= "dpll_abe_m3x2_ck",
401 .parent
= &dpll_abe_x2_ck
,
402 .clksel
= dpll_abe_m2x2_div
,
403 .clksel_reg
= OMAP4430_CM_DIV_M3_DPLL_ABE
,
404 .clksel_mask
= OMAP4430_DPLL_CLKOUTHIF_DIV_MASK
,
405 .ops
= &clkops_omap4_dpllmx_ops
,
406 .recalc
= &omap2_clksel_recalc
,
407 .round_rate
= &omap2_clksel_round_rate
,
408 .set_rate
= &omap2_clksel_set_rate
,
411 static const struct clksel core_hsd_byp_clk_mux_sel
[] = {
412 { .parent
= &sys_clkin_ck
, .rates
= div_1_0_rates
},
413 { .parent
= &dpll_abe_m3x2_ck
, .rates
= div_1_1_rates
},
417 static struct clk core_hsd_byp_clk_mux_ck
= {
418 .name
= "core_hsd_byp_clk_mux_ck",
419 .parent
= &sys_clkin_ck
,
420 .clksel
= core_hsd_byp_clk_mux_sel
,
421 .init
= &omap2_init_clksel_parent
,
422 .clksel_reg
= OMAP4430_CM_CLKSEL_DPLL_CORE
,
423 .clksel_mask
= OMAP4430_DPLL_BYP_CLKSEL_MASK
,
425 .recalc
= &omap2_clksel_recalc
,
429 static struct dpll_data dpll_core_dd
= {
430 .mult_div1_reg
= OMAP4430_CM_CLKSEL_DPLL_CORE
,
431 .clk_bypass
= &core_hsd_byp_clk_mux_ck
,
432 .clk_ref
= &sys_clkin_ck
,
433 .control_reg
= OMAP4430_CM_CLKMODE_DPLL_CORE
,
434 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
435 .autoidle_reg
= OMAP4430_CM_AUTOIDLE_DPLL_CORE
,
436 .idlest_reg
= OMAP4430_CM_IDLEST_DPLL_CORE
,
437 .mult_mask
= OMAP4430_DPLL_MULT_MASK
,
438 .div1_mask
= OMAP4430_DPLL_DIV_MASK
,
439 .enable_mask
= OMAP4430_DPLL_EN_MASK
,
440 .autoidle_mask
= OMAP4430_AUTO_DPLL_MODE_MASK
,
441 .idlest_mask
= OMAP4430_ST_DPLL_CLK_MASK
,
442 .max_multiplier
= 2047,
448 static struct clk dpll_core_ck
= {
449 .name
= "dpll_core_ck",
450 .parent
= &sys_clkin_ck
,
451 .dpll_data
= &dpll_core_dd
,
452 .init
= &omap2_init_dpll_parent
,
453 .ops
= &clkops_omap3_core_dpll_ops
,
454 .recalc
= &omap3_dpll_recalc
,
457 static struct clk dpll_core_x2_ck
= {
458 .name
= "dpll_core_x2_ck",
459 .parent
= &dpll_core_ck
,
460 .flags
= CLOCK_CLKOUTX2
,
462 .recalc
= &omap3_clkoutx2_recalc
,
465 static const struct clksel dpll_core_m6x2_div
[] = {
466 { .parent
= &dpll_core_x2_ck
, .rates
= div31_1to31_rates
},
470 static struct clk dpll_core_m6x2_ck
= {
471 .name
= "dpll_core_m6x2_ck",
472 .parent
= &dpll_core_x2_ck
,
473 .clksel
= dpll_core_m6x2_div
,
474 .clksel_reg
= OMAP4430_CM_DIV_M6_DPLL_CORE
,
475 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK
,
476 .ops
= &clkops_omap4_dpllmx_ops
,
477 .recalc
= &omap2_clksel_recalc
,
478 .round_rate
= &omap2_clksel_round_rate
,
479 .set_rate
= &omap2_clksel_set_rate
,
482 static const struct clksel dbgclk_mux_sel
[] = {
483 { .parent
= &sys_clkin_ck
, .rates
= div_1_0_rates
},
484 { .parent
= &dpll_core_m6x2_ck
, .rates
= div_1_1_rates
},
488 static struct clk dbgclk_mux_ck
= {
489 .name
= "dbgclk_mux_ck",
490 .parent
= &sys_clkin_ck
,
492 .recalc
= &followparent_recalc
,
495 static const struct clksel dpll_core_m2_div
[] = {
496 { .parent
= &dpll_core_ck
, .rates
= div31_1to31_rates
},
500 static struct clk dpll_core_m2_ck
= {
501 .name
= "dpll_core_m2_ck",
502 .parent
= &dpll_core_ck
,
503 .clksel
= dpll_core_m2_div
,
504 .clksel_reg
= OMAP4430_CM_DIV_M2_DPLL_CORE
,
505 .clksel_mask
= OMAP4430_DPLL_CLKOUT_DIV_MASK
,
506 .ops
= &clkops_omap4_dpllmx_ops
,
507 .recalc
= &omap2_clksel_recalc
,
508 .round_rate
= &omap2_clksel_round_rate
,
509 .set_rate
= &omap2_clksel_set_rate
,
512 static struct clk ddrphy_ck
= {
514 .parent
= &dpll_core_m2_ck
,
516 .clkdm_name
= "l3_emif_clkdm",
518 .recalc
= &omap_fixed_divisor_recalc
,
521 static struct clk dpll_core_m5x2_ck
= {
522 .name
= "dpll_core_m5x2_ck",
523 .parent
= &dpll_core_x2_ck
,
524 .clksel
= dpll_core_m6x2_div
,
525 .clksel_reg
= OMAP4430_CM_DIV_M5_DPLL_CORE
,
526 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK
,
527 .ops
= &clkops_omap4_dpllmx_ops
,
528 .recalc
= &omap2_clksel_recalc
,
529 .round_rate
= &omap2_clksel_round_rate
,
530 .set_rate
= &omap2_clksel_set_rate
,
533 static const struct clksel div_core_div
[] = {
534 { .parent
= &dpll_core_m5x2_ck
, .rates
= div2_1to2_rates
},
538 static struct clk div_core_ck
= {
539 .name
= "div_core_ck",
540 .parent
= &dpll_core_m5x2_ck
,
541 .clksel
= div_core_div
,
542 .clksel_reg
= OMAP4430_CM_CLKSEL_CORE
,
543 .clksel_mask
= OMAP4430_CLKSEL_CORE_MASK
,
545 .recalc
= &omap2_clksel_recalc
,
546 .round_rate
= &omap2_clksel_round_rate
,
547 .set_rate
= &omap2_clksel_set_rate
,
550 static const struct clksel_rate div4_1to8_rates
[] = {
551 { .div
= 1, .val
= 0, .flags
= RATE_IN_4430
},
552 { .div
= 2, .val
= 1, .flags
= RATE_IN_4430
},
553 { .div
= 4, .val
= 2, .flags
= RATE_IN_4430
},
554 { .div
= 8, .val
= 3, .flags
= RATE_IN_4430
},
558 static const struct clksel div_iva_hs_clk_div
[] = {
559 { .parent
= &dpll_core_m5x2_ck
, .rates
= div4_1to8_rates
},
563 static struct clk div_iva_hs_clk
= {
564 .name
= "div_iva_hs_clk",
565 .parent
= &dpll_core_m5x2_ck
,
566 .clksel
= div_iva_hs_clk_div
,
567 .clksel_reg
= OMAP4430_CM_BYPCLK_DPLL_IVA
,
568 .clksel_mask
= OMAP4430_CLKSEL_0_1_MASK
,
570 .recalc
= &omap2_clksel_recalc
,
571 .round_rate
= &omap2_clksel_round_rate
,
572 .set_rate
= &omap2_clksel_set_rate
,
575 static struct clk div_mpu_hs_clk
= {
576 .name
= "div_mpu_hs_clk",
577 .parent
= &dpll_core_m5x2_ck
,
578 .clksel
= div_iva_hs_clk_div
,
579 .clksel_reg
= OMAP4430_CM_BYPCLK_DPLL_MPU
,
580 .clksel_mask
= OMAP4430_CLKSEL_0_1_MASK
,
582 .recalc
= &omap2_clksel_recalc
,
583 .round_rate
= &omap2_clksel_round_rate
,
584 .set_rate
= &omap2_clksel_set_rate
,
587 static struct clk dpll_core_m4x2_ck
= {
588 .name
= "dpll_core_m4x2_ck",
589 .parent
= &dpll_core_x2_ck
,
590 .clksel
= dpll_core_m6x2_div
,
591 .clksel_reg
= OMAP4430_CM_DIV_M4_DPLL_CORE
,
592 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK
,
593 .ops
= &clkops_omap4_dpllmx_ops
,
594 .recalc
= &omap2_clksel_recalc
,
595 .round_rate
= &omap2_clksel_round_rate
,
596 .set_rate
= &omap2_clksel_set_rate
,
599 static struct clk dll_clk_div_ck
= {
600 .name
= "dll_clk_div_ck",
601 .parent
= &dpll_core_m4x2_ck
,
604 .recalc
= &omap_fixed_divisor_recalc
,
607 static const struct clksel dpll_abe_m2_div
[] = {
608 { .parent
= &dpll_abe_ck
, .rates
= div31_1to31_rates
},
612 static struct clk dpll_abe_m2_ck
= {
613 .name
= "dpll_abe_m2_ck",
614 .parent
= &dpll_abe_ck
,
615 .clksel
= dpll_abe_m2_div
,
616 .clksel_reg
= OMAP4430_CM_DIV_M2_DPLL_ABE
,
617 .clksel_mask
= OMAP4430_DPLL_CLKOUT_DIV_MASK
,
618 .ops
= &clkops_omap4_dpllmx_ops
,
619 .recalc
= &omap2_clksel_recalc
,
620 .round_rate
= &omap2_clksel_round_rate
,
621 .set_rate
= &omap2_clksel_set_rate
,
624 static struct clk dpll_core_m3x2_ck
= {
625 .name
= "dpll_core_m3x2_ck",
626 .parent
= &dpll_core_x2_ck
,
627 .clksel
= dpll_core_m6x2_div
,
628 .clksel_reg
= OMAP4430_CM_DIV_M3_DPLL_CORE
,
629 .clksel_mask
= OMAP4430_DPLL_CLKOUTHIF_DIV_MASK
,
630 .ops
= &clkops_omap2_dflt
,
631 .recalc
= &omap2_clksel_recalc
,
632 .round_rate
= &omap2_clksel_round_rate
,
633 .set_rate
= &omap2_clksel_set_rate
,
634 .enable_reg
= OMAP4430_CM_DIV_M3_DPLL_CORE
,
635 .enable_bit
= OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT
,
638 static struct clk dpll_core_m7x2_ck
= {
639 .name
= "dpll_core_m7x2_ck",
640 .parent
= &dpll_core_x2_ck
,
641 .clksel
= dpll_core_m6x2_div
,
642 .clksel_reg
= OMAP4430_CM_DIV_M7_DPLL_CORE
,
643 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK
,
644 .ops
= &clkops_omap4_dpllmx_ops
,
645 .recalc
= &omap2_clksel_recalc
,
646 .round_rate
= &omap2_clksel_round_rate
,
647 .set_rate
= &omap2_clksel_set_rate
,
650 static const struct clksel iva_hsd_byp_clk_mux_sel
[] = {
651 { .parent
= &sys_clkin_ck
, .rates
= div_1_0_rates
},
652 { .parent
= &div_iva_hs_clk
, .rates
= div_1_1_rates
},
656 static struct clk iva_hsd_byp_clk_mux_ck
= {
657 .name
= "iva_hsd_byp_clk_mux_ck",
658 .parent
= &sys_clkin_ck
,
659 .clksel
= iva_hsd_byp_clk_mux_sel
,
660 .init
= &omap2_init_clksel_parent
,
661 .clksel_reg
= OMAP4430_CM_CLKSEL_DPLL_IVA
,
662 .clksel_mask
= OMAP4430_DPLL_BYP_CLKSEL_MASK
,
664 .recalc
= &omap2_clksel_recalc
,
668 static struct dpll_data dpll_iva_dd
= {
669 .mult_div1_reg
= OMAP4430_CM_CLKSEL_DPLL_IVA
,
670 .clk_bypass
= &iva_hsd_byp_clk_mux_ck
,
671 .clk_ref
= &sys_clkin_ck
,
672 .control_reg
= OMAP4430_CM_CLKMODE_DPLL_IVA
,
673 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
674 .autoidle_reg
= OMAP4430_CM_AUTOIDLE_DPLL_IVA
,
675 .idlest_reg
= OMAP4430_CM_IDLEST_DPLL_IVA
,
676 .mult_mask
= OMAP4430_DPLL_MULT_MASK
,
677 .div1_mask
= OMAP4430_DPLL_DIV_MASK
,
678 .enable_mask
= OMAP4430_DPLL_EN_MASK
,
679 .autoidle_mask
= OMAP4430_AUTO_DPLL_MODE_MASK
,
680 .idlest_mask
= OMAP4430_ST_DPLL_CLK_MASK
,
681 .max_multiplier
= 2047,
687 static struct clk dpll_iva_ck
= {
688 .name
= "dpll_iva_ck",
689 .parent
= &sys_clkin_ck
,
690 .dpll_data
= &dpll_iva_dd
,
691 .init
= &omap2_init_dpll_parent
,
692 .ops
= &clkops_omap3_noncore_dpll_ops
,
693 .recalc
= &omap3_dpll_recalc
,
694 .round_rate
= &omap2_dpll_round_rate
,
695 .set_rate
= &omap3_noncore_dpll_set_rate
,
698 static struct clk dpll_iva_x2_ck
= {
699 .name
= "dpll_iva_x2_ck",
700 .parent
= &dpll_iva_ck
,
701 .flags
= CLOCK_CLKOUTX2
,
703 .recalc
= &omap3_clkoutx2_recalc
,
706 static const struct clksel dpll_iva_m4x2_div
[] = {
707 { .parent
= &dpll_iva_x2_ck
, .rates
= div31_1to31_rates
},
711 static struct clk dpll_iva_m4x2_ck
= {
712 .name
= "dpll_iva_m4x2_ck",
713 .parent
= &dpll_iva_x2_ck
,
714 .clksel
= dpll_iva_m4x2_div
,
715 .clksel_reg
= OMAP4430_CM_DIV_M4_DPLL_IVA
,
716 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK
,
717 .ops
= &clkops_omap4_dpllmx_ops
,
718 .recalc
= &omap2_clksel_recalc
,
719 .round_rate
= &omap2_clksel_round_rate
,
720 .set_rate
= &omap2_clksel_set_rate
,
723 static struct clk dpll_iva_m5x2_ck
= {
724 .name
= "dpll_iva_m5x2_ck",
725 .parent
= &dpll_iva_x2_ck
,
726 .clksel
= dpll_iva_m4x2_div
,
727 .clksel_reg
= OMAP4430_CM_DIV_M5_DPLL_IVA
,
728 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK
,
729 .ops
= &clkops_omap4_dpllmx_ops
,
730 .recalc
= &omap2_clksel_recalc
,
731 .round_rate
= &omap2_clksel_round_rate
,
732 .set_rate
= &omap2_clksel_set_rate
,
736 static struct dpll_data dpll_mpu_dd
= {
737 .mult_div1_reg
= OMAP4430_CM_CLKSEL_DPLL_MPU
,
738 .clk_bypass
= &div_mpu_hs_clk
,
739 .clk_ref
= &sys_clkin_ck
,
740 .control_reg
= OMAP4430_CM_CLKMODE_DPLL_MPU
,
741 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
742 .autoidle_reg
= OMAP4430_CM_AUTOIDLE_DPLL_MPU
,
743 .idlest_reg
= OMAP4430_CM_IDLEST_DPLL_MPU
,
744 .mult_mask
= OMAP4430_DPLL_MULT_MASK
,
745 .div1_mask
= OMAP4430_DPLL_DIV_MASK
,
746 .enable_mask
= OMAP4430_DPLL_EN_MASK
,
747 .autoidle_mask
= OMAP4430_AUTO_DPLL_MODE_MASK
,
748 .idlest_mask
= OMAP4430_ST_DPLL_CLK_MASK
,
749 .max_multiplier
= 2047,
755 static struct clk dpll_mpu_ck
= {
756 .name
= "dpll_mpu_ck",
757 .parent
= &sys_clkin_ck
,
758 .dpll_data
= &dpll_mpu_dd
,
759 .init
= &omap2_init_dpll_parent
,
760 .ops
= &clkops_omap3_noncore_dpll_ops
,
761 .recalc
= &omap3_dpll_recalc
,
762 .round_rate
= &omap2_dpll_round_rate
,
763 .set_rate
= &omap3_noncore_dpll_set_rate
,
766 static const struct clksel dpll_mpu_m2_div
[] = {
767 { .parent
= &dpll_mpu_ck
, .rates
= div31_1to31_rates
},
771 static struct clk dpll_mpu_m2_ck
= {
772 .name
= "dpll_mpu_m2_ck",
773 .parent
= &dpll_mpu_ck
,
774 .clkdm_name
= "cm_clkdm",
775 .clksel
= dpll_mpu_m2_div
,
776 .clksel_reg
= OMAP4430_CM_DIV_M2_DPLL_MPU
,
777 .clksel_mask
= OMAP4430_DPLL_CLKOUT_DIV_MASK
,
778 .ops
= &clkops_omap4_dpllmx_ops
,
779 .recalc
= &omap2_clksel_recalc
,
780 .round_rate
= &omap2_clksel_round_rate
,
781 .set_rate
= &omap2_clksel_set_rate
,
784 static struct clk per_hs_clk_div_ck
= {
785 .name
= "per_hs_clk_div_ck",
786 .parent
= &dpll_abe_m3x2_ck
,
789 .recalc
= &omap_fixed_divisor_recalc
,
792 static const struct clksel per_hsd_byp_clk_mux_sel
[] = {
793 { .parent
= &sys_clkin_ck
, .rates
= div_1_0_rates
},
794 { .parent
= &per_hs_clk_div_ck
, .rates
= div_1_1_rates
},
798 static struct clk per_hsd_byp_clk_mux_ck
= {
799 .name
= "per_hsd_byp_clk_mux_ck",
800 .parent
= &sys_clkin_ck
,
801 .clksel
= per_hsd_byp_clk_mux_sel
,
802 .init
= &omap2_init_clksel_parent
,
803 .clksel_reg
= OMAP4430_CM_CLKSEL_DPLL_PER
,
804 .clksel_mask
= OMAP4430_DPLL_BYP_CLKSEL_MASK
,
806 .recalc
= &omap2_clksel_recalc
,
810 static struct dpll_data dpll_per_dd
= {
811 .mult_div1_reg
= OMAP4430_CM_CLKSEL_DPLL_PER
,
812 .clk_bypass
= &per_hsd_byp_clk_mux_ck
,
813 .clk_ref
= &sys_clkin_ck
,
814 .control_reg
= OMAP4430_CM_CLKMODE_DPLL_PER
,
815 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
816 .autoidle_reg
= OMAP4430_CM_AUTOIDLE_DPLL_PER
,
817 .idlest_reg
= OMAP4430_CM_IDLEST_DPLL_PER
,
818 .mult_mask
= OMAP4430_DPLL_MULT_MASK
,
819 .div1_mask
= OMAP4430_DPLL_DIV_MASK
,
820 .enable_mask
= OMAP4430_DPLL_EN_MASK
,
821 .autoidle_mask
= OMAP4430_AUTO_DPLL_MODE_MASK
,
822 .idlest_mask
= OMAP4430_ST_DPLL_CLK_MASK
,
823 .max_multiplier
= 2047,
829 static struct clk dpll_per_ck
= {
830 .name
= "dpll_per_ck",
831 .parent
= &sys_clkin_ck
,
832 .dpll_data
= &dpll_per_dd
,
833 .init
= &omap2_init_dpll_parent
,
834 .ops
= &clkops_omap3_noncore_dpll_ops
,
835 .recalc
= &omap3_dpll_recalc
,
836 .round_rate
= &omap2_dpll_round_rate
,
837 .set_rate
= &omap3_noncore_dpll_set_rate
,
840 static const struct clksel dpll_per_m2_div
[] = {
841 { .parent
= &dpll_per_ck
, .rates
= div31_1to31_rates
},
845 static struct clk dpll_per_m2_ck
= {
846 .name
= "dpll_per_m2_ck",
847 .parent
= &dpll_per_ck
,
848 .clksel
= dpll_per_m2_div
,
849 .clksel_reg
= OMAP4430_CM_DIV_M2_DPLL_PER
,
850 .clksel_mask
= OMAP4430_DPLL_CLKOUT_DIV_MASK
,
851 .ops
= &clkops_omap4_dpllmx_ops
,
852 .recalc
= &omap2_clksel_recalc
,
853 .round_rate
= &omap2_clksel_round_rate
,
854 .set_rate
= &omap2_clksel_set_rate
,
857 static struct clk dpll_per_x2_ck
= {
858 .name
= "dpll_per_x2_ck",
859 .parent
= &dpll_per_ck
,
860 .clksel_reg
= OMAP4430_CM_DIV_M2_DPLL_PER
,
861 .flags
= CLOCK_CLKOUTX2
,
862 .ops
= &clkops_omap4_dpllmx_ops
,
863 .recalc
= &omap3_clkoutx2_recalc
,
866 static const struct clksel dpll_per_m2x2_div
[] = {
867 { .parent
= &dpll_per_x2_ck
, .rates
= div31_1to31_rates
},
871 static struct clk dpll_per_m2x2_ck
= {
872 .name
= "dpll_per_m2x2_ck",
873 .parent
= &dpll_per_x2_ck
,
874 .clksel
= dpll_per_m2x2_div
,
875 .clksel_reg
= OMAP4430_CM_DIV_M2_DPLL_PER
,
876 .clksel_mask
= OMAP4430_DPLL_CLKOUT_DIV_MASK
,
877 .ops
= &clkops_omap4_dpllmx_ops
,
878 .recalc
= &omap2_clksel_recalc
,
879 .round_rate
= &omap2_clksel_round_rate
,
880 .set_rate
= &omap2_clksel_set_rate
,
883 static struct clk dpll_per_m3x2_ck
= {
884 .name
= "dpll_per_m3x2_ck",
885 .parent
= &dpll_per_x2_ck
,
886 .clksel
= dpll_per_m2x2_div
,
887 .clksel_reg
= OMAP4430_CM_DIV_M3_DPLL_PER
,
888 .clksel_mask
= OMAP4430_DPLL_CLKOUTHIF_DIV_MASK
,
889 .ops
= &clkops_omap2_dflt
,
890 .recalc
= &omap2_clksel_recalc
,
891 .round_rate
= &omap2_clksel_round_rate
,
892 .set_rate
= &omap2_clksel_set_rate
,
893 .enable_reg
= OMAP4430_CM_DIV_M3_DPLL_PER
,
894 .enable_bit
= OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT
,
897 static struct clk dpll_per_m4x2_ck
= {
898 .name
= "dpll_per_m4x2_ck",
899 .parent
= &dpll_per_x2_ck
,
900 .clksel
= dpll_per_m2x2_div
,
901 .clksel_reg
= OMAP4430_CM_DIV_M4_DPLL_PER
,
902 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK
,
903 .ops
= &clkops_omap4_dpllmx_ops
,
904 .recalc
= &omap2_clksel_recalc
,
905 .round_rate
= &omap2_clksel_round_rate
,
906 .set_rate
= &omap2_clksel_set_rate
,
909 static struct clk dpll_per_m5x2_ck
= {
910 .name
= "dpll_per_m5x2_ck",
911 .parent
= &dpll_per_x2_ck
,
912 .clksel
= dpll_per_m2x2_div
,
913 .clksel_reg
= OMAP4430_CM_DIV_M5_DPLL_PER
,
914 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK
,
915 .ops
= &clkops_omap4_dpllmx_ops
,
916 .recalc
= &omap2_clksel_recalc
,
917 .round_rate
= &omap2_clksel_round_rate
,
918 .set_rate
= &omap2_clksel_set_rate
,
921 static struct clk dpll_per_m6x2_ck
= {
922 .name
= "dpll_per_m6x2_ck",
923 .parent
= &dpll_per_x2_ck
,
924 .clksel
= dpll_per_m2x2_div
,
925 .clksel_reg
= OMAP4430_CM_DIV_M6_DPLL_PER
,
926 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK
,
927 .ops
= &clkops_omap4_dpllmx_ops
,
928 .recalc
= &omap2_clksel_recalc
,
929 .round_rate
= &omap2_clksel_round_rate
,
930 .set_rate
= &omap2_clksel_set_rate
,
933 static struct clk dpll_per_m7x2_ck
= {
934 .name
= "dpll_per_m7x2_ck",
935 .parent
= &dpll_per_x2_ck
,
936 .clksel
= dpll_per_m2x2_div
,
937 .clksel_reg
= OMAP4430_CM_DIV_M7_DPLL_PER
,
938 .clksel_mask
= OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK
,
939 .ops
= &clkops_omap4_dpllmx_ops
,
940 .recalc
= &omap2_clksel_recalc
,
941 .round_rate
= &omap2_clksel_round_rate
,
942 .set_rate
= &omap2_clksel_set_rate
,
945 static struct clk usb_hs_clk_div_ck
= {
946 .name
= "usb_hs_clk_div_ck",
947 .parent
= &dpll_abe_m3x2_ck
,
950 .recalc
= &omap_fixed_divisor_recalc
,
954 static struct dpll_data dpll_usb_dd
= {
955 .mult_div1_reg
= OMAP4430_CM_CLKSEL_DPLL_USB
,
956 .clk_bypass
= &usb_hs_clk_div_ck
,
957 .flags
= DPLL_J_TYPE
,
958 .clk_ref
= &sys_clkin_ck
,
959 .control_reg
= OMAP4430_CM_CLKMODE_DPLL_USB
,
960 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
961 .autoidle_reg
= OMAP4430_CM_AUTOIDLE_DPLL_USB
,
962 .idlest_reg
= OMAP4430_CM_IDLEST_DPLL_USB
,
963 .mult_mask
= OMAP4430_DPLL_MULT_USB_MASK
,
964 .div1_mask
= OMAP4430_DPLL_DIV_0_7_MASK
,
965 .enable_mask
= OMAP4430_DPLL_EN_MASK
,
966 .autoidle_mask
= OMAP4430_AUTO_DPLL_MODE_MASK
,
967 .idlest_mask
= OMAP4430_ST_DPLL_CLK_MASK
,
968 .sddiv_mask
= OMAP4430_DPLL_SD_DIV_MASK
,
969 .max_multiplier
= 4095,
975 static struct clk dpll_usb_ck
= {
976 .name
= "dpll_usb_ck",
977 .parent
= &sys_clkin_ck
,
978 .dpll_data
= &dpll_usb_dd
,
979 .init
= &omap2_init_dpll_parent
,
980 .ops
= &clkops_omap3_noncore_dpll_ops
,
981 .recalc
= &omap3_dpll_recalc
,
982 .round_rate
= &omap2_dpll_round_rate
,
983 .set_rate
= &omap3_noncore_dpll_set_rate
,
984 .clkdm_name
= "l3_init_clkdm",
987 static struct clk dpll_usb_clkdcoldo_ck
= {
988 .name
= "dpll_usb_clkdcoldo_ck",
989 .parent
= &dpll_usb_ck
,
990 .clksel_reg
= OMAP4430_CM_CLKDCOLDO_DPLL_USB
,
991 .ops
= &clkops_omap4_dpllmx_ops
,
992 .recalc
= &followparent_recalc
,
995 static const struct clksel dpll_usb_m2_div
[] = {
996 { .parent
= &dpll_usb_ck
, .rates
= div31_1to31_rates
},
1000 static struct clk dpll_usb_m2_ck
= {
1001 .name
= "dpll_usb_m2_ck",
1002 .parent
= &dpll_usb_ck
,
1003 .clksel
= dpll_usb_m2_div
,
1004 .clksel_reg
= OMAP4430_CM_DIV_M2_DPLL_USB
,
1005 .clksel_mask
= OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK
,
1006 .ops
= &clkops_omap4_dpllmx_ops
,
1007 .recalc
= &omap2_clksel_recalc
,
1008 .round_rate
= &omap2_clksel_round_rate
,
1009 .set_rate
= &omap2_clksel_set_rate
,
1012 static const struct clksel ducati_clk_mux_sel
[] = {
1013 { .parent
= &div_core_ck
, .rates
= div_1_0_rates
},
1014 { .parent
= &dpll_per_m6x2_ck
, .rates
= div_1_1_rates
},
1018 static struct clk ducati_clk_mux_ck
= {
1019 .name
= "ducati_clk_mux_ck",
1020 .parent
= &div_core_ck
,
1021 .clksel
= ducati_clk_mux_sel
,
1022 .init
= &omap2_init_clksel_parent
,
1023 .clksel_reg
= OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT
,
1024 .clksel_mask
= OMAP4430_CLKSEL_0_0_MASK
,
1025 .ops
= &clkops_null
,
1026 .recalc
= &omap2_clksel_recalc
,
1029 static struct clk func_12m_fclk
= {
1030 .name
= "func_12m_fclk",
1031 .parent
= &dpll_per_m2x2_ck
,
1032 .ops
= &clkops_null
,
1034 .recalc
= &omap_fixed_divisor_recalc
,
1037 static struct clk func_24m_clk
= {
1038 .name
= "func_24m_clk",
1039 .parent
= &dpll_per_m2_ck
,
1040 .ops
= &clkops_null
,
1042 .recalc
= &omap_fixed_divisor_recalc
,
1045 static struct clk func_24mc_fclk
= {
1046 .name
= "func_24mc_fclk",
1047 .parent
= &dpll_per_m2x2_ck
,
1048 .ops
= &clkops_null
,
1050 .recalc
= &omap_fixed_divisor_recalc
,
1053 static const struct clksel_rate div2_4to8_rates
[] = {
1054 { .div
= 4, .val
= 0, .flags
= RATE_IN_4430
},
1055 { .div
= 8, .val
= 1, .flags
= RATE_IN_4430
},
1059 static const struct clksel func_48m_fclk_div
[] = {
1060 { .parent
= &dpll_per_m2x2_ck
, .rates
= div2_4to8_rates
},
1064 static struct clk func_48m_fclk
= {
1065 .name
= "func_48m_fclk",
1066 .parent
= &dpll_per_m2x2_ck
,
1067 .clksel
= func_48m_fclk_div
,
1068 .clksel_reg
= OMAP4430_CM_SCALE_FCLK
,
1069 .clksel_mask
= OMAP4430_SCALE_FCLK_MASK
,
1070 .ops
= &clkops_null
,
1071 .recalc
= &omap2_clksel_recalc
,
1072 .round_rate
= &omap2_clksel_round_rate
,
1073 .set_rate
= &omap2_clksel_set_rate
,
1076 static struct clk func_48mc_fclk
= {
1077 .name
= "func_48mc_fclk",
1078 .parent
= &dpll_per_m2x2_ck
,
1079 .ops
= &clkops_null
,
1081 .recalc
= &omap_fixed_divisor_recalc
,
1084 static const struct clksel_rate div2_2to4_rates
[] = {
1085 { .div
= 2, .val
= 0, .flags
= RATE_IN_4430
},
1086 { .div
= 4, .val
= 1, .flags
= RATE_IN_4430
},
1090 static const struct clksel func_64m_fclk_div
[] = {
1091 { .parent
= &dpll_per_m4x2_ck
, .rates
= div2_2to4_rates
},
1095 static struct clk func_64m_fclk
= {
1096 .name
= "func_64m_fclk",
1097 .parent
= &dpll_per_m4x2_ck
,
1098 .clksel
= func_64m_fclk_div
,
1099 .clksel_reg
= OMAP4430_CM_SCALE_FCLK
,
1100 .clksel_mask
= OMAP4430_SCALE_FCLK_MASK
,
1101 .ops
= &clkops_null
,
1102 .recalc
= &omap2_clksel_recalc
,
1103 .round_rate
= &omap2_clksel_round_rate
,
1104 .set_rate
= &omap2_clksel_set_rate
,
1107 static const struct clksel func_96m_fclk_div
[] = {
1108 { .parent
= &dpll_per_m2x2_ck
, .rates
= div2_2to4_rates
},
1112 static struct clk func_96m_fclk
= {
1113 .name
= "func_96m_fclk",
1114 .parent
= &dpll_per_m2x2_ck
,
1115 .clksel
= func_96m_fclk_div
,
1116 .clksel_reg
= OMAP4430_CM_SCALE_FCLK
,
1117 .clksel_mask
= OMAP4430_SCALE_FCLK_MASK
,
1118 .ops
= &clkops_null
,
1119 .recalc
= &omap2_clksel_recalc
,
1120 .round_rate
= &omap2_clksel_round_rate
,
1121 .set_rate
= &omap2_clksel_set_rate
,
1124 static const struct clksel_rate div2_1to8_rates
[] = {
1125 { .div
= 1, .val
= 0, .flags
= RATE_IN_4430
},
1126 { .div
= 8, .val
= 1, .flags
= RATE_IN_4430
},
1130 static const struct clksel init_60m_fclk_div
[] = {
1131 { .parent
= &dpll_usb_m2_ck
, .rates
= div2_1to8_rates
},
1135 static struct clk init_60m_fclk
= {
1136 .name
= "init_60m_fclk",
1137 .parent
= &dpll_usb_m2_ck
,
1138 .clksel
= init_60m_fclk_div
,
1139 .clksel_reg
= OMAP4430_CM_CLKSEL_USB_60MHZ
,
1140 .clksel_mask
= OMAP4430_CLKSEL_0_0_MASK
,
1141 .ops
= &clkops_null
,
1142 .recalc
= &omap2_clksel_recalc
,
1143 .round_rate
= &omap2_clksel_round_rate
,
1144 .set_rate
= &omap2_clksel_set_rate
,
1147 static const struct clksel l3_div_div
[] = {
1148 { .parent
= &div_core_ck
, .rates
= div2_1to2_rates
},
1152 static struct clk l3_div_ck
= {
1153 .name
= "l3_div_ck",
1154 .parent
= &div_core_ck
,
1155 .clkdm_name
= "cm_clkdm",
1156 .clksel
= l3_div_div
,
1157 .clksel_reg
= OMAP4430_CM_CLKSEL_CORE
,
1158 .clksel_mask
= OMAP4430_CLKSEL_L3_MASK
,
1159 .ops
= &clkops_null
,
1160 .recalc
= &omap2_clksel_recalc
,
1161 .round_rate
= &omap2_clksel_round_rate
,
1162 .set_rate
= &omap2_clksel_set_rate
,
1165 static const struct clksel l4_div_div
[] = {
1166 { .parent
= &l3_div_ck
, .rates
= div2_1to2_rates
},
1170 static struct clk l4_div_ck
= {
1171 .name
= "l4_div_ck",
1172 .parent
= &l3_div_ck
,
1173 .clksel
= l4_div_div
,
1174 .clksel_reg
= OMAP4430_CM_CLKSEL_CORE
,
1175 .clksel_mask
= OMAP4430_CLKSEL_L4_MASK
,
1176 .ops
= &clkops_null
,
1177 .recalc
= &omap2_clksel_recalc
,
1178 .round_rate
= &omap2_clksel_round_rate
,
1179 .set_rate
= &omap2_clksel_set_rate
,
1182 static struct clk lp_clk_div_ck
= {
1183 .name
= "lp_clk_div_ck",
1184 .parent
= &dpll_abe_m2x2_ck
,
1185 .ops
= &clkops_null
,
1187 .recalc
= &omap_fixed_divisor_recalc
,
1190 static const struct clksel l4_wkup_clk_mux_sel
[] = {
1191 { .parent
= &sys_clkin_ck
, .rates
= div_1_0_rates
},
1192 { .parent
= &lp_clk_div_ck
, .rates
= div_1_1_rates
},
1196 static struct clk l4_wkup_clk_mux_ck
= {
1197 .name
= "l4_wkup_clk_mux_ck",
1198 .parent
= &sys_clkin_ck
,
1199 .clksel
= l4_wkup_clk_mux_sel
,
1200 .init
= &omap2_init_clksel_parent
,
1201 .clksel_reg
= OMAP4430_CM_L4_WKUP_CLKSEL
,
1202 .clksel_mask
= OMAP4430_CLKSEL_0_0_MASK
,
1203 .ops
= &clkops_null
,
1204 .recalc
= &omap2_clksel_recalc
,
1207 static const struct clksel_rate div2_2to1_rates
[] = {
1208 { .div
= 1, .val
= 1, .flags
= RATE_IN_4430
},
1209 { .div
= 2, .val
= 0, .flags
= RATE_IN_4430
},
1213 static const struct clksel ocp_abe_iclk_div
[] = {
1214 { .parent
= &aess_fclk
, .rates
= div2_2to1_rates
},
1218 static struct clk mpu_periphclk
= {
1219 .name
= "mpu_periphclk",
1220 .parent
= &dpll_mpu_ck
,
1221 .ops
= &clkops_null
,
1223 .recalc
= &omap_fixed_divisor_recalc
,
1226 static struct clk ocp_abe_iclk
= {
1227 .name
= "ocp_abe_iclk",
1228 .parent
= &aess_fclk
,
1229 .clksel
= ocp_abe_iclk_div
,
1230 .clksel_reg
= OMAP4430_CM1_ABE_AESS_CLKCTRL
,
1231 .clksel_mask
= OMAP4430_CLKSEL_AESS_FCLK_MASK
,
1232 .ops
= &clkops_null
,
1233 .recalc
= &omap2_clksel_recalc
,
1236 static struct clk per_abe_24m_fclk
= {
1237 .name
= "per_abe_24m_fclk",
1238 .parent
= &dpll_abe_m2_ck
,
1239 .ops
= &clkops_null
,
1241 .recalc
= &omap_fixed_divisor_recalc
,
1244 static const struct clksel per_abe_nc_fclk_div
[] = {
1245 { .parent
= &dpll_abe_m2_ck
, .rates
= div2_1to2_rates
},
1249 static struct clk per_abe_nc_fclk
= {
1250 .name
= "per_abe_nc_fclk",
1251 .parent
= &dpll_abe_m2_ck
,
1252 .clksel
= per_abe_nc_fclk_div
,
1253 .clksel_reg
= OMAP4430_CM_SCALE_FCLK
,
1254 .clksel_mask
= OMAP4430_SCALE_FCLK_MASK
,
1255 .ops
= &clkops_null
,
1256 .recalc
= &omap2_clksel_recalc
,
1257 .round_rate
= &omap2_clksel_round_rate
,
1258 .set_rate
= &omap2_clksel_set_rate
,
1261 static const struct clksel pmd_stm_clock_mux_sel
[] = {
1262 { .parent
= &sys_clkin_ck
, .rates
= div_1_0_rates
},
1263 { .parent
= &dpll_core_m6x2_ck
, .rates
= div_1_1_rates
},
1264 { .parent
= &tie_low_clock_ck
, .rates
= div_1_2_rates
},
1268 static struct clk pmd_stm_clock_mux_ck
= {
1269 .name
= "pmd_stm_clock_mux_ck",
1270 .parent
= &sys_clkin_ck
,
1271 .ops
= &clkops_null
,
1272 .recalc
= &followparent_recalc
,
1275 static struct clk pmd_trace_clk_mux_ck
= {
1276 .name
= "pmd_trace_clk_mux_ck",
1277 .parent
= &sys_clkin_ck
,
1278 .ops
= &clkops_null
,
1279 .recalc
= &followparent_recalc
,
1282 static const struct clksel syc_clk_div_div
[] = {
1283 { .parent
= &sys_clkin_ck
, .rates
= div2_1to2_rates
},
1287 static struct clk syc_clk_div_ck
= {
1288 .name
= "syc_clk_div_ck",
1289 .parent
= &sys_clkin_ck
,
1290 .clksel
= syc_clk_div_div
,
1291 .clksel_reg
= OMAP4430_CM_ABE_DSS_SYS_CLKSEL
,
1292 .clksel_mask
= OMAP4430_CLKSEL_0_0_MASK
,
1293 .ops
= &clkops_null
,
1294 .recalc
= &omap2_clksel_recalc
,
1295 .round_rate
= &omap2_clksel_round_rate
,
1296 .set_rate
= &omap2_clksel_set_rate
,
1299 /* Leaf clocks controlled by modules */
1301 static struct clk aes1_fck
= {
1303 .ops
= &clkops_omap2_dflt
,
1304 .enable_reg
= OMAP4430_CM_L4SEC_AES1_CLKCTRL
,
1305 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1306 .clkdm_name
= "l4_secure_clkdm",
1307 .parent
= &l3_div_ck
,
1308 .recalc
= &followparent_recalc
,
1311 static struct clk aes2_fck
= {
1313 .ops
= &clkops_omap2_dflt
,
1314 .enable_reg
= OMAP4430_CM_L4SEC_AES2_CLKCTRL
,
1315 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1316 .clkdm_name
= "l4_secure_clkdm",
1317 .parent
= &l3_div_ck
,
1318 .recalc
= &followparent_recalc
,
1321 static struct clk aess_fck
= {
1323 .ops
= &clkops_omap2_dflt
,
1324 .enable_reg
= OMAP4430_CM1_ABE_AESS_CLKCTRL
,
1325 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1326 .clkdm_name
= "abe_clkdm",
1327 .parent
= &aess_fclk
,
1328 .recalc
= &followparent_recalc
,
1331 static struct clk bandgap_fclk
= {
1332 .name
= "bandgap_fclk",
1333 .ops
= &clkops_omap2_dflt
,
1334 .enable_reg
= OMAP4430_CM_WKUP_BANDGAP_CLKCTRL
,
1335 .enable_bit
= OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT
,
1336 .clkdm_name
= "l4_wkup_clkdm",
1337 .parent
= &sys_32k_ck
,
1338 .recalc
= &followparent_recalc
,
1341 static struct clk des3des_fck
= {
1342 .name
= "des3des_fck",
1343 .ops
= &clkops_omap2_dflt
,
1344 .enable_reg
= OMAP4430_CM_L4SEC_DES3DES_CLKCTRL
,
1345 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1346 .clkdm_name
= "l4_secure_clkdm",
1347 .parent
= &l4_div_ck
,
1348 .recalc
= &followparent_recalc
,
1351 static const struct clksel dmic_sync_mux_sel
[] = {
1352 { .parent
= &abe_24m_fclk
, .rates
= div_1_0_rates
},
1353 { .parent
= &syc_clk_div_ck
, .rates
= div_1_1_rates
},
1354 { .parent
= &func_24m_clk
, .rates
= div_1_2_rates
},
1358 static struct clk dmic_sync_mux_ck
= {
1359 .name
= "dmic_sync_mux_ck",
1360 .parent
= &abe_24m_fclk
,
1361 .clksel
= dmic_sync_mux_sel
,
1362 .init
= &omap2_init_clksel_parent
,
1363 .clksel_reg
= OMAP4430_CM1_ABE_DMIC_CLKCTRL
,
1364 .clksel_mask
= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK
,
1365 .ops
= &clkops_null
,
1366 .recalc
= &omap2_clksel_recalc
,
1369 static const struct clksel func_dmic_abe_gfclk_sel
[] = {
1370 { .parent
= &dmic_sync_mux_ck
, .rates
= div_1_0_rates
},
1371 { .parent
= &pad_clks_ck
, .rates
= div_1_1_rates
},
1372 { .parent
= &slimbus_clk
, .rates
= div_1_2_rates
},
1376 /* Merged func_dmic_abe_gfclk into dmic */
1377 static struct clk dmic_fck
= {
1379 .parent
= &dmic_sync_mux_ck
,
1380 .clksel
= func_dmic_abe_gfclk_sel
,
1381 .init
= &omap2_init_clksel_parent
,
1382 .clksel_reg
= OMAP4430_CM1_ABE_DMIC_CLKCTRL
,
1383 .clksel_mask
= OMAP4430_CLKSEL_SOURCE_MASK
,
1384 .ops
= &clkops_omap2_dflt
,
1385 .recalc
= &omap2_clksel_recalc
,
1386 .enable_reg
= OMAP4430_CM1_ABE_DMIC_CLKCTRL
,
1387 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1388 .clkdm_name
= "abe_clkdm",
1391 static struct clk dsp_fck
= {
1393 .ops
= &clkops_omap2_dflt
,
1394 .enable_reg
= OMAP4430_CM_TESLA_TESLA_CLKCTRL
,
1395 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1396 .clkdm_name
= "tesla_clkdm",
1397 .parent
= &dpll_iva_m4x2_ck
,
1398 .recalc
= &followparent_recalc
,
1401 static struct clk dss_sys_clk
= {
1402 .name
= "dss_sys_clk",
1403 .ops
= &clkops_omap2_dflt
,
1404 .enable_reg
= OMAP4430_CM_DSS_DSS_CLKCTRL
,
1405 .enable_bit
= OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT
,
1406 .clkdm_name
= "l3_dss_clkdm",
1407 .parent
= &syc_clk_div_ck
,
1408 .recalc
= &followparent_recalc
,
1411 static struct clk dss_tv_clk
= {
1412 .name
= "dss_tv_clk",
1413 .ops
= &clkops_omap2_dflt
,
1414 .enable_reg
= OMAP4430_CM_DSS_DSS_CLKCTRL
,
1415 .enable_bit
= OMAP4430_OPTFCLKEN_TV_CLK_SHIFT
,
1416 .clkdm_name
= "l3_dss_clkdm",
1417 .parent
= &extalt_clkin_ck
,
1418 .recalc
= &followparent_recalc
,
1421 static struct clk dss_dss_clk
= {
1422 .name
= "dss_dss_clk",
1423 .ops
= &clkops_omap2_dflt
,
1424 .enable_reg
= OMAP4430_CM_DSS_DSS_CLKCTRL
,
1425 .enable_bit
= OMAP4430_OPTFCLKEN_DSSCLK_SHIFT
,
1426 .clkdm_name
= "l3_dss_clkdm",
1427 .parent
= &dpll_per_m5x2_ck
,
1428 .recalc
= &followparent_recalc
,
1431 static const struct clksel_rate div3_8to32_rates
[] = {
1432 { .div
= 8, .val
= 0, .flags
= RATE_IN_4460
},
1433 { .div
= 16, .val
= 1, .flags
= RATE_IN_4460
},
1434 { .div
= 32, .val
= 2, .flags
= RATE_IN_4460
},
1438 static const struct clksel div_ts_div
[] = {
1439 { .parent
= &l4_wkup_clk_mux_ck
, .rates
= div3_8to32_rates
},
1443 static struct clk div_ts_ck
= {
1444 .name
= "div_ts_ck",
1445 .parent
= &l4_wkup_clk_mux_ck
,
1446 .clksel
= div_ts_div
,
1447 .clksel_reg
= OMAP4430_CM_WKUP_BANDGAP_CLKCTRL
,
1448 .clksel_mask
= OMAP4430_CLKSEL_24_25_MASK
,
1449 .ops
= &clkops_null
,
1450 .recalc
= &omap2_clksel_recalc
,
1451 .round_rate
= &omap2_clksel_round_rate
,
1452 .set_rate
= &omap2_clksel_set_rate
,
1455 static struct clk bandgap_ts_fclk
= {
1456 .name
= "bandgap_ts_fclk",
1457 .ops
= &clkops_omap2_dflt
,
1458 .enable_reg
= OMAP4430_CM_WKUP_BANDGAP_CLKCTRL
,
1459 .enable_bit
= OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT
,
1460 .clkdm_name
= "l4_wkup_clkdm",
1461 .parent
= &div_ts_ck
,
1462 .recalc
= &followparent_recalc
,
1465 static struct clk dss_48mhz_clk
= {
1466 .name
= "dss_48mhz_clk",
1467 .ops
= &clkops_omap2_dflt
,
1468 .enable_reg
= OMAP4430_CM_DSS_DSS_CLKCTRL
,
1469 .enable_bit
= OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT
,
1470 .clkdm_name
= "l3_dss_clkdm",
1471 .parent
= &func_48mc_fclk
,
1472 .recalc
= &followparent_recalc
,
1475 static struct clk dss_fck
= {
1477 .ops
= &clkops_omap2_dflt
,
1478 .enable_reg
= OMAP4430_CM_DSS_DSS_CLKCTRL
,
1479 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1480 .clkdm_name
= "l3_dss_clkdm",
1481 .parent
= &l3_div_ck
,
1482 .recalc
= &followparent_recalc
,
1485 static struct clk efuse_ctrl_cust_fck
= {
1486 .name
= "efuse_ctrl_cust_fck",
1487 .ops
= &clkops_omap2_dflt
,
1488 .enable_reg
= OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL
,
1489 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1490 .clkdm_name
= "l4_cefuse_clkdm",
1491 .parent
= &sys_clkin_ck
,
1492 .recalc
= &followparent_recalc
,
1495 static struct clk emif1_fck
= {
1496 .name
= "emif1_fck",
1497 .ops
= &clkops_omap2_dflt
,
1498 .enable_reg
= OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL
,
1499 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1500 .flags
= ENABLE_ON_INIT
,
1501 .clkdm_name
= "l3_emif_clkdm",
1502 .parent
= &ddrphy_ck
,
1503 .recalc
= &followparent_recalc
,
1506 static struct clk emif2_fck
= {
1507 .name
= "emif2_fck",
1508 .ops
= &clkops_omap2_dflt
,
1509 .enable_reg
= OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL
,
1510 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1511 .flags
= ENABLE_ON_INIT
,
1512 .clkdm_name
= "l3_emif_clkdm",
1513 .parent
= &ddrphy_ck
,
1514 .recalc
= &followparent_recalc
,
1517 static const struct clksel fdif_fclk_div
[] = {
1518 { .parent
= &dpll_per_m4x2_ck
, .rates
= div3_1to4_rates
},
1522 /* Merged fdif_fclk into fdif */
1523 static struct clk fdif_fck
= {
1525 .parent
= &dpll_per_m4x2_ck
,
1526 .clksel
= fdif_fclk_div
,
1527 .clksel_reg
= OMAP4430_CM_CAM_FDIF_CLKCTRL
,
1528 .clksel_mask
= OMAP4430_CLKSEL_FCLK_MASK
,
1529 .ops
= &clkops_omap2_dflt
,
1530 .recalc
= &omap2_clksel_recalc
,
1531 .round_rate
= &omap2_clksel_round_rate
,
1532 .set_rate
= &omap2_clksel_set_rate
,
1533 .enable_reg
= OMAP4430_CM_CAM_FDIF_CLKCTRL
,
1534 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1535 .clkdm_name
= "iss_clkdm",
1538 static struct clk fpka_fck
= {
1540 .ops
= &clkops_omap2_dflt
,
1541 .enable_reg
= OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL
,
1542 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1543 .clkdm_name
= "l4_secure_clkdm",
1544 .parent
= &l4_div_ck
,
1545 .recalc
= &followparent_recalc
,
1548 static struct clk gpio1_dbclk
= {
1549 .name
= "gpio1_dbclk",
1550 .ops
= &clkops_omap2_dflt
,
1551 .enable_reg
= OMAP4430_CM_WKUP_GPIO1_CLKCTRL
,
1552 .enable_bit
= OMAP4430_OPTFCLKEN_DBCLK_SHIFT
,
1553 .clkdm_name
= "l4_wkup_clkdm",
1554 .parent
= &sys_32k_ck
,
1555 .recalc
= &followparent_recalc
,
1558 static struct clk gpio1_ick
= {
1559 .name
= "gpio1_ick",
1560 .ops
= &clkops_omap2_dflt
,
1561 .enable_reg
= OMAP4430_CM_WKUP_GPIO1_CLKCTRL
,
1562 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1563 .clkdm_name
= "l4_wkup_clkdm",
1564 .parent
= &l4_wkup_clk_mux_ck
,
1565 .recalc
= &followparent_recalc
,
1568 static struct clk gpio2_dbclk
= {
1569 .name
= "gpio2_dbclk",
1570 .ops
= &clkops_omap2_dflt
,
1571 .enable_reg
= OMAP4430_CM_L4PER_GPIO2_CLKCTRL
,
1572 .enable_bit
= OMAP4430_OPTFCLKEN_DBCLK_SHIFT
,
1573 .clkdm_name
= "l4_per_clkdm",
1574 .parent
= &sys_32k_ck
,
1575 .recalc
= &followparent_recalc
,
1578 static struct clk gpio2_ick
= {
1579 .name
= "gpio2_ick",
1580 .ops
= &clkops_omap2_dflt
,
1581 .enable_reg
= OMAP4430_CM_L4PER_GPIO2_CLKCTRL
,
1582 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1583 .clkdm_name
= "l4_per_clkdm",
1584 .parent
= &l4_div_ck
,
1585 .recalc
= &followparent_recalc
,
1588 static struct clk gpio3_dbclk
= {
1589 .name
= "gpio3_dbclk",
1590 .ops
= &clkops_omap2_dflt
,
1591 .enable_reg
= OMAP4430_CM_L4PER_GPIO3_CLKCTRL
,
1592 .enable_bit
= OMAP4430_OPTFCLKEN_DBCLK_SHIFT
,
1593 .clkdm_name
= "l4_per_clkdm",
1594 .parent
= &sys_32k_ck
,
1595 .recalc
= &followparent_recalc
,
1598 static struct clk gpio3_ick
= {
1599 .name
= "gpio3_ick",
1600 .ops
= &clkops_omap2_dflt
,
1601 .enable_reg
= OMAP4430_CM_L4PER_GPIO3_CLKCTRL
,
1602 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1603 .clkdm_name
= "l4_per_clkdm",
1604 .parent
= &l4_div_ck
,
1605 .recalc
= &followparent_recalc
,
1608 static struct clk gpio4_dbclk
= {
1609 .name
= "gpio4_dbclk",
1610 .ops
= &clkops_omap2_dflt
,
1611 .enable_reg
= OMAP4430_CM_L4PER_GPIO4_CLKCTRL
,
1612 .enable_bit
= OMAP4430_OPTFCLKEN_DBCLK_SHIFT
,
1613 .clkdm_name
= "l4_per_clkdm",
1614 .parent
= &sys_32k_ck
,
1615 .recalc
= &followparent_recalc
,
1618 static struct clk gpio4_ick
= {
1619 .name
= "gpio4_ick",
1620 .ops
= &clkops_omap2_dflt
,
1621 .enable_reg
= OMAP4430_CM_L4PER_GPIO4_CLKCTRL
,
1622 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1623 .clkdm_name
= "l4_per_clkdm",
1624 .parent
= &l4_div_ck
,
1625 .recalc
= &followparent_recalc
,
1628 static struct clk gpio5_dbclk
= {
1629 .name
= "gpio5_dbclk",
1630 .ops
= &clkops_omap2_dflt
,
1631 .enable_reg
= OMAP4430_CM_L4PER_GPIO5_CLKCTRL
,
1632 .enable_bit
= OMAP4430_OPTFCLKEN_DBCLK_SHIFT
,
1633 .clkdm_name
= "l4_per_clkdm",
1634 .parent
= &sys_32k_ck
,
1635 .recalc
= &followparent_recalc
,
1638 static struct clk gpio5_ick
= {
1639 .name
= "gpio5_ick",
1640 .ops
= &clkops_omap2_dflt
,
1641 .enable_reg
= OMAP4430_CM_L4PER_GPIO5_CLKCTRL
,
1642 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1643 .clkdm_name
= "l4_per_clkdm",
1644 .parent
= &l4_div_ck
,
1645 .recalc
= &followparent_recalc
,
1648 static struct clk gpio6_dbclk
= {
1649 .name
= "gpio6_dbclk",
1650 .ops
= &clkops_omap2_dflt
,
1651 .enable_reg
= OMAP4430_CM_L4PER_GPIO6_CLKCTRL
,
1652 .enable_bit
= OMAP4430_OPTFCLKEN_DBCLK_SHIFT
,
1653 .clkdm_name
= "l4_per_clkdm",
1654 .parent
= &sys_32k_ck
,
1655 .recalc
= &followparent_recalc
,
1658 static struct clk gpio6_ick
= {
1659 .name
= "gpio6_ick",
1660 .ops
= &clkops_omap2_dflt
,
1661 .enable_reg
= OMAP4430_CM_L4PER_GPIO6_CLKCTRL
,
1662 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1663 .clkdm_name
= "l4_per_clkdm",
1664 .parent
= &l4_div_ck
,
1665 .recalc
= &followparent_recalc
,
1668 static struct clk gpmc_ick
= {
1670 .ops
= &clkops_omap2_dflt
,
1671 .enable_reg
= OMAP4430_CM_L3_2_GPMC_CLKCTRL
,
1672 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1673 .flags
= ENABLE_ON_INIT
,
1674 .clkdm_name
= "l3_2_clkdm",
1675 .parent
= &l3_div_ck
,
1676 .recalc
= &followparent_recalc
,
1679 static const struct clksel sgx_clk_mux_sel
[] = {
1680 { .parent
= &dpll_core_m7x2_ck
, .rates
= div_1_0_rates
},
1681 { .parent
= &dpll_per_m7x2_ck
, .rates
= div_1_1_rates
},
1685 /* Merged sgx_clk_mux into gpu */
1686 static struct clk gpu_fck
= {
1688 .parent
= &dpll_core_m7x2_ck
,
1689 .clksel
= sgx_clk_mux_sel
,
1690 .init
= &omap2_init_clksel_parent
,
1691 .clksel_reg
= OMAP4430_CM_GFX_GFX_CLKCTRL
,
1692 .clksel_mask
= OMAP4430_CLKSEL_SGX_FCLK_MASK
,
1693 .ops
= &clkops_omap2_dflt
,
1694 .recalc
= &omap2_clksel_recalc
,
1695 .enable_reg
= OMAP4430_CM_GFX_GFX_CLKCTRL
,
1696 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1697 .clkdm_name
= "l3_gfx_clkdm",
1700 static struct clk hdq1w_fck
= {
1701 .name
= "hdq1w_fck",
1702 .ops
= &clkops_omap2_dflt
,
1703 .enable_reg
= OMAP4430_CM_L4PER_HDQ1W_CLKCTRL
,
1704 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1705 .clkdm_name
= "l4_per_clkdm",
1706 .parent
= &func_12m_fclk
,
1707 .recalc
= &followparent_recalc
,
1710 static const struct clksel hsi_fclk_div
[] = {
1711 { .parent
= &dpll_per_m2x2_ck
, .rates
= div3_1to4_rates
},
1715 /* Merged hsi_fclk into hsi */
1716 static struct clk hsi_fck
= {
1718 .parent
= &dpll_per_m2x2_ck
,
1719 .clksel
= hsi_fclk_div
,
1720 .clksel_reg
= OMAP4430_CM_L3INIT_HSI_CLKCTRL
,
1721 .clksel_mask
= OMAP4430_CLKSEL_24_25_MASK
,
1722 .ops
= &clkops_omap2_dflt
,
1723 .recalc
= &omap2_clksel_recalc
,
1724 .round_rate
= &omap2_clksel_round_rate
,
1725 .set_rate
= &omap2_clksel_set_rate
,
1726 .enable_reg
= OMAP4430_CM_L3INIT_HSI_CLKCTRL
,
1727 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1728 .clkdm_name
= "l3_init_clkdm",
1731 static struct clk i2c1_fck
= {
1733 .ops
= &clkops_omap2_dflt
,
1734 .enable_reg
= OMAP4430_CM_L4PER_I2C1_CLKCTRL
,
1735 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1736 .clkdm_name
= "l4_per_clkdm",
1737 .parent
= &func_96m_fclk
,
1738 .recalc
= &followparent_recalc
,
1741 static struct clk i2c2_fck
= {
1743 .ops
= &clkops_omap2_dflt
,
1744 .enable_reg
= OMAP4430_CM_L4PER_I2C2_CLKCTRL
,
1745 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1746 .clkdm_name
= "l4_per_clkdm",
1747 .parent
= &func_96m_fclk
,
1748 .recalc
= &followparent_recalc
,
1751 static struct clk i2c3_fck
= {
1753 .ops
= &clkops_omap2_dflt
,
1754 .enable_reg
= OMAP4430_CM_L4PER_I2C3_CLKCTRL
,
1755 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1756 .clkdm_name
= "l4_per_clkdm",
1757 .parent
= &func_96m_fclk
,
1758 .recalc
= &followparent_recalc
,
1761 static struct clk i2c4_fck
= {
1763 .ops
= &clkops_omap2_dflt
,
1764 .enable_reg
= OMAP4430_CM_L4PER_I2C4_CLKCTRL
,
1765 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1766 .clkdm_name
= "l4_per_clkdm",
1767 .parent
= &func_96m_fclk
,
1768 .recalc
= &followparent_recalc
,
1771 static struct clk ipu_fck
= {
1773 .ops
= &clkops_omap2_dflt
,
1774 .enable_reg
= OMAP4430_CM_DUCATI_DUCATI_CLKCTRL
,
1775 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1776 .clkdm_name
= "ducati_clkdm",
1777 .parent
= &ducati_clk_mux_ck
,
1778 .recalc
= &followparent_recalc
,
1781 static struct clk iss_ctrlclk
= {
1782 .name
= "iss_ctrlclk",
1783 .ops
= &clkops_omap2_dflt
,
1784 .enable_reg
= OMAP4430_CM_CAM_ISS_CLKCTRL
,
1785 .enable_bit
= OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT
,
1786 .clkdm_name
= "iss_clkdm",
1787 .parent
= &func_96m_fclk
,
1788 .recalc
= &followparent_recalc
,
1791 static struct clk iss_fck
= {
1793 .ops
= &clkops_omap2_dflt
,
1794 .enable_reg
= OMAP4430_CM_CAM_ISS_CLKCTRL
,
1795 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1796 .clkdm_name
= "iss_clkdm",
1797 .parent
= &ducati_clk_mux_ck
,
1798 .recalc
= &followparent_recalc
,
1801 static struct clk iva_fck
= {
1803 .ops
= &clkops_omap2_dflt
,
1804 .enable_reg
= OMAP4430_CM_IVAHD_IVAHD_CLKCTRL
,
1805 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1806 .clkdm_name
= "ivahd_clkdm",
1807 .parent
= &dpll_iva_m5x2_ck
,
1808 .recalc
= &followparent_recalc
,
1811 static struct clk kbd_fck
= {
1813 .ops
= &clkops_omap2_dflt
,
1814 .enable_reg
= OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL
,
1815 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1816 .clkdm_name
= "l4_wkup_clkdm",
1817 .parent
= &sys_32k_ck
,
1818 .recalc
= &followparent_recalc
,
1821 static struct clk l3_instr_ick
= {
1822 .name
= "l3_instr_ick",
1823 .ops
= &clkops_omap2_dflt
,
1824 .enable_reg
= OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL
,
1825 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1826 .flags
= ENABLE_ON_INIT
,
1827 .clkdm_name
= "l3_instr_clkdm",
1828 .parent
= &l3_div_ck
,
1829 .recalc
= &followparent_recalc
,
1832 static struct clk l3_main_3_ick
= {
1833 .name
= "l3_main_3_ick",
1834 .ops
= &clkops_omap2_dflt
,
1835 .enable_reg
= OMAP4430_CM_L3INSTR_L3_3_CLKCTRL
,
1836 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
1837 .flags
= ENABLE_ON_INIT
,
1838 .clkdm_name
= "l3_instr_clkdm",
1839 .parent
= &l3_div_ck
,
1840 .recalc
= &followparent_recalc
,
1843 static struct clk mcasp_sync_mux_ck
= {
1844 .name
= "mcasp_sync_mux_ck",
1845 .parent
= &abe_24m_fclk
,
1846 .clksel
= dmic_sync_mux_sel
,
1847 .init
= &omap2_init_clksel_parent
,
1848 .clksel_reg
= OMAP4430_CM1_ABE_MCASP_CLKCTRL
,
1849 .clksel_mask
= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK
,
1850 .ops
= &clkops_null
,
1851 .recalc
= &omap2_clksel_recalc
,
1854 static const struct clksel func_mcasp_abe_gfclk_sel
[] = {
1855 { .parent
= &mcasp_sync_mux_ck
, .rates
= div_1_0_rates
},
1856 { .parent
= &pad_clks_ck
, .rates
= div_1_1_rates
},
1857 { .parent
= &slimbus_clk
, .rates
= div_1_2_rates
},
1861 /* Merged func_mcasp_abe_gfclk into mcasp */
1862 static struct clk mcasp_fck
= {
1863 .name
= "mcasp_fck",
1864 .parent
= &mcasp_sync_mux_ck
,
1865 .clksel
= func_mcasp_abe_gfclk_sel
,
1866 .init
= &omap2_init_clksel_parent
,
1867 .clksel_reg
= OMAP4430_CM1_ABE_MCASP_CLKCTRL
,
1868 .clksel_mask
= OMAP4430_CLKSEL_SOURCE_MASK
,
1869 .ops
= &clkops_omap2_dflt
,
1870 .recalc
= &omap2_clksel_recalc
,
1871 .enable_reg
= OMAP4430_CM1_ABE_MCASP_CLKCTRL
,
1872 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1873 .clkdm_name
= "abe_clkdm",
1876 static struct clk mcbsp1_sync_mux_ck
= {
1877 .name
= "mcbsp1_sync_mux_ck",
1878 .parent
= &abe_24m_fclk
,
1879 .clksel
= dmic_sync_mux_sel
,
1880 .init
= &omap2_init_clksel_parent
,
1881 .clksel_reg
= OMAP4430_CM1_ABE_MCBSP1_CLKCTRL
,
1882 .clksel_mask
= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK
,
1883 .ops
= &clkops_null
,
1884 .recalc
= &omap2_clksel_recalc
,
1887 static const struct clksel func_mcbsp1_gfclk_sel
[] = {
1888 { .parent
= &mcbsp1_sync_mux_ck
, .rates
= div_1_0_rates
},
1889 { .parent
= &pad_clks_ck
, .rates
= div_1_1_rates
},
1890 { .parent
= &slimbus_clk
, .rates
= div_1_2_rates
},
1894 /* Merged func_mcbsp1_gfclk into mcbsp1 */
1895 static struct clk mcbsp1_fck
= {
1896 .name
= "mcbsp1_fck",
1897 .parent
= &mcbsp1_sync_mux_ck
,
1898 .clksel
= func_mcbsp1_gfclk_sel
,
1899 .init
= &omap2_init_clksel_parent
,
1900 .clksel_reg
= OMAP4430_CM1_ABE_MCBSP1_CLKCTRL
,
1901 .clksel_mask
= OMAP4430_CLKSEL_SOURCE_MASK
,
1902 .ops
= &clkops_omap2_dflt
,
1903 .recalc
= &omap2_clksel_recalc
,
1904 .enable_reg
= OMAP4430_CM1_ABE_MCBSP1_CLKCTRL
,
1905 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1906 .clkdm_name
= "abe_clkdm",
1909 static struct clk mcbsp2_sync_mux_ck
= {
1910 .name
= "mcbsp2_sync_mux_ck",
1911 .parent
= &abe_24m_fclk
,
1912 .clksel
= dmic_sync_mux_sel
,
1913 .init
= &omap2_init_clksel_parent
,
1914 .clksel_reg
= OMAP4430_CM1_ABE_MCBSP2_CLKCTRL
,
1915 .clksel_mask
= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK
,
1916 .ops
= &clkops_null
,
1917 .recalc
= &omap2_clksel_recalc
,
1920 static const struct clksel func_mcbsp2_gfclk_sel
[] = {
1921 { .parent
= &mcbsp2_sync_mux_ck
, .rates
= div_1_0_rates
},
1922 { .parent
= &pad_clks_ck
, .rates
= div_1_1_rates
},
1923 { .parent
= &slimbus_clk
, .rates
= div_1_2_rates
},
1927 /* Merged func_mcbsp2_gfclk into mcbsp2 */
1928 static struct clk mcbsp2_fck
= {
1929 .name
= "mcbsp2_fck",
1930 .parent
= &mcbsp2_sync_mux_ck
,
1931 .clksel
= func_mcbsp2_gfclk_sel
,
1932 .init
= &omap2_init_clksel_parent
,
1933 .clksel_reg
= OMAP4430_CM1_ABE_MCBSP2_CLKCTRL
,
1934 .clksel_mask
= OMAP4430_CLKSEL_SOURCE_MASK
,
1935 .ops
= &clkops_omap2_dflt
,
1936 .recalc
= &omap2_clksel_recalc
,
1937 .enable_reg
= OMAP4430_CM1_ABE_MCBSP2_CLKCTRL
,
1938 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1939 .clkdm_name
= "abe_clkdm",
1942 static struct clk mcbsp3_sync_mux_ck
= {
1943 .name
= "mcbsp3_sync_mux_ck",
1944 .parent
= &abe_24m_fclk
,
1945 .clksel
= dmic_sync_mux_sel
,
1946 .init
= &omap2_init_clksel_parent
,
1947 .clksel_reg
= OMAP4430_CM1_ABE_MCBSP3_CLKCTRL
,
1948 .clksel_mask
= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK
,
1949 .ops
= &clkops_null
,
1950 .recalc
= &omap2_clksel_recalc
,
1953 static const struct clksel func_mcbsp3_gfclk_sel
[] = {
1954 { .parent
= &mcbsp3_sync_mux_ck
, .rates
= div_1_0_rates
},
1955 { .parent
= &pad_clks_ck
, .rates
= div_1_1_rates
},
1956 { .parent
= &slimbus_clk
, .rates
= div_1_2_rates
},
1960 /* Merged func_mcbsp3_gfclk into mcbsp3 */
1961 static struct clk mcbsp3_fck
= {
1962 .name
= "mcbsp3_fck",
1963 .parent
= &mcbsp3_sync_mux_ck
,
1964 .clksel
= func_mcbsp3_gfclk_sel
,
1965 .init
= &omap2_init_clksel_parent
,
1966 .clksel_reg
= OMAP4430_CM1_ABE_MCBSP3_CLKCTRL
,
1967 .clksel_mask
= OMAP4430_CLKSEL_SOURCE_MASK
,
1968 .ops
= &clkops_omap2_dflt
,
1969 .recalc
= &omap2_clksel_recalc
,
1970 .enable_reg
= OMAP4430_CM1_ABE_MCBSP3_CLKCTRL
,
1971 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
1972 .clkdm_name
= "abe_clkdm",
1975 static const struct clksel mcbsp4_sync_mux_sel
[] = {
1976 { .parent
= &func_96m_fclk
, .rates
= div_1_0_rates
},
1977 { .parent
= &per_abe_nc_fclk
, .rates
= div_1_1_rates
},
1981 static struct clk mcbsp4_sync_mux_ck
= {
1982 .name
= "mcbsp4_sync_mux_ck",
1983 .parent
= &func_96m_fclk
,
1984 .clksel
= mcbsp4_sync_mux_sel
,
1985 .init
= &omap2_init_clksel_parent
,
1986 .clksel_reg
= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL
,
1987 .clksel_mask
= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK
,
1988 .ops
= &clkops_null
,
1989 .recalc
= &omap2_clksel_recalc
,
1992 static const struct clksel per_mcbsp4_gfclk_sel
[] = {
1993 { .parent
= &mcbsp4_sync_mux_ck
, .rates
= div_1_0_rates
},
1994 { .parent
= &pad_clks_ck
, .rates
= div_1_1_rates
},
1998 /* Merged per_mcbsp4_gfclk into mcbsp4 */
1999 static struct clk mcbsp4_fck
= {
2000 .name
= "mcbsp4_fck",
2001 .parent
= &mcbsp4_sync_mux_ck
,
2002 .clksel
= per_mcbsp4_gfclk_sel
,
2003 .init
= &omap2_init_clksel_parent
,
2004 .clksel_reg
= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL
,
2005 .clksel_mask
= OMAP4430_CLKSEL_SOURCE_24_24_MASK
,
2006 .ops
= &clkops_omap2_dflt
,
2007 .recalc
= &omap2_clksel_recalc
,
2008 .enable_reg
= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL
,
2009 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2010 .clkdm_name
= "l4_per_clkdm",
2013 static struct clk mcpdm_fck
= {
2014 .name
= "mcpdm_fck",
2015 .ops
= &clkops_omap2_dflt
,
2016 .enable_reg
= OMAP4430_CM1_ABE_PDM_CLKCTRL
,
2017 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2018 .clkdm_name
= "abe_clkdm",
2019 .parent
= &pad_clks_ck
,
2020 .recalc
= &followparent_recalc
,
2023 static struct clk mcspi1_fck
= {
2024 .name
= "mcspi1_fck",
2025 .ops
= &clkops_omap2_dflt
,
2026 .enable_reg
= OMAP4430_CM_L4PER_MCSPI1_CLKCTRL
,
2027 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2028 .clkdm_name
= "l4_per_clkdm",
2029 .parent
= &func_48m_fclk
,
2030 .recalc
= &followparent_recalc
,
2033 static struct clk mcspi2_fck
= {
2034 .name
= "mcspi2_fck",
2035 .ops
= &clkops_omap2_dflt
,
2036 .enable_reg
= OMAP4430_CM_L4PER_MCSPI2_CLKCTRL
,
2037 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2038 .clkdm_name
= "l4_per_clkdm",
2039 .parent
= &func_48m_fclk
,
2040 .recalc
= &followparent_recalc
,
2043 static struct clk mcspi3_fck
= {
2044 .name
= "mcspi3_fck",
2045 .ops
= &clkops_omap2_dflt
,
2046 .enable_reg
= OMAP4430_CM_L4PER_MCSPI3_CLKCTRL
,
2047 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2048 .clkdm_name
= "l4_per_clkdm",
2049 .parent
= &func_48m_fclk
,
2050 .recalc
= &followparent_recalc
,
2053 static struct clk mcspi4_fck
= {
2054 .name
= "mcspi4_fck",
2055 .ops
= &clkops_omap2_dflt
,
2056 .enable_reg
= OMAP4430_CM_L4PER_MCSPI4_CLKCTRL
,
2057 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2058 .clkdm_name
= "l4_per_clkdm",
2059 .parent
= &func_48m_fclk
,
2060 .recalc
= &followparent_recalc
,
2063 static const struct clksel hsmmc1_fclk_sel
[] = {
2064 { .parent
= &func_64m_fclk
, .rates
= div_1_0_rates
},
2065 { .parent
= &func_96m_fclk
, .rates
= div_1_1_rates
},
2069 /* Merged hsmmc1_fclk into mmc1 */
2070 static struct clk mmc1_fck
= {
2072 .parent
= &func_64m_fclk
,
2073 .clksel
= hsmmc1_fclk_sel
,
2074 .init
= &omap2_init_clksel_parent
,
2075 .clksel_reg
= OMAP4430_CM_L3INIT_MMC1_CLKCTRL
,
2076 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
2077 .ops
= &clkops_omap2_dflt
,
2078 .recalc
= &omap2_clksel_recalc
,
2079 .enable_reg
= OMAP4430_CM_L3INIT_MMC1_CLKCTRL
,
2080 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2081 .clkdm_name
= "l3_init_clkdm",
2084 /* Merged hsmmc2_fclk into mmc2 */
2085 static struct clk mmc2_fck
= {
2087 .parent
= &func_64m_fclk
,
2088 .clksel
= hsmmc1_fclk_sel
,
2089 .init
= &omap2_init_clksel_parent
,
2090 .clksel_reg
= OMAP4430_CM_L3INIT_MMC2_CLKCTRL
,
2091 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
2092 .ops
= &clkops_omap2_dflt
,
2093 .recalc
= &omap2_clksel_recalc
,
2094 .enable_reg
= OMAP4430_CM_L3INIT_MMC2_CLKCTRL
,
2095 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2096 .clkdm_name
= "l3_init_clkdm",
2099 static struct clk mmc3_fck
= {
2101 .ops
= &clkops_omap2_dflt
,
2102 .enable_reg
= OMAP4430_CM_L4PER_MMCSD3_CLKCTRL
,
2103 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2104 .clkdm_name
= "l4_per_clkdm",
2105 .parent
= &func_48m_fclk
,
2106 .recalc
= &followparent_recalc
,
2109 static struct clk mmc4_fck
= {
2111 .ops
= &clkops_omap2_dflt
,
2112 .enable_reg
= OMAP4430_CM_L4PER_MMCSD4_CLKCTRL
,
2113 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2114 .clkdm_name
= "l4_per_clkdm",
2115 .parent
= &func_48m_fclk
,
2116 .recalc
= &followparent_recalc
,
2119 static struct clk mmc5_fck
= {
2121 .ops
= &clkops_omap2_dflt
,
2122 .enable_reg
= OMAP4430_CM_L4PER_MMCSD5_CLKCTRL
,
2123 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2124 .clkdm_name
= "l4_per_clkdm",
2125 .parent
= &func_48m_fclk
,
2126 .recalc
= &followparent_recalc
,
2129 static struct clk ocp2scp_usb_phy_phy_48m
= {
2130 .name
= "ocp2scp_usb_phy_phy_48m",
2131 .ops
= &clkops_omap2_dflt
,
2132 .enable_reg
= OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL
,
2133 .enable_bit
= OMAP4430_OPTFCLKEN_PHY_48M_SHIFT
,
2134 .clkdm_name
= "l3_init_clkdm",
2135 .parent
= &func_48m_fclk
,
2136 .recalc
= &followparent_recalc
,
2139 static struct clk ocp2scp_usb_phy_ick
= {
2140 .name
= "ocp2scp_usb_phy_ick",
2141 .ops
= &clkops_omap2_dflt
,
2142 .enable_reg
= OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL
,
2143 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
2144 .clkdm_name
= "l3_init_clkdm",
2145 .parent
= &l4_div_ck
,
2146 .recalc
= &followparent_recalc
,
2149 static struct clk ocp_wp_noc_ick
= {
2150 .name
= "ocp_wp_noc_ick",
2151 .ops
= &clkops_omap2_dflt
,
2152 .enable_reg
= OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL
,
2153 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
2154 .flags
= ENABLE_ON_INIT
,
2155 .clkdm_name
= "l3_instr_clkdm",
2156 .parent
= &l3_div_ck
,
2157 .recalc
= &followparent_recalc
,
2160 static struct clk rng_ick
= {
2162 .ops
= &clkops_omap2_dflt
,
2163 .enable_reg
= OMAP4430_CM_L4SEC_RNG_CLKCTRL
,
2164 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
2165 .clkdm_name
= "l4_secure_clkdm",
2166 .parent
= &l4_div_ck
,
2167 .recalc
= &followparent_recalc
,
2170 static struct clk sha2md5_fck
= {
2171 .name
= "sha2md5_fck",
2172 .ops
= &clkops_omap2_dflt
,
2173 .enable_reg
= OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL
,
2174 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2175 .clkdm_name
= "l4_secure_clkdm",
2176 .parent
= &l3_div_ck
,
2177 .recalc
= &followparent_recalc
,
2180 static struct clk sl2if_ick
= {
2181 .name
= "sl2if_ick",
2182 .ops
= &clkops_omap2_dflt
,
2183 .enable_reg
= OMAP4430_CM_IVAHD_SL2_CLKCTRL
,
2184 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
2185 .clkdm_name
= "ivahd_clkdm",
2186 .parent
= &dpll_iva_m5x2_ck
,
2187 .recalc
= &followparent_recalc
,
2190 static struct clk slimbus1_fclk_1
= {
2191 .name
= "slimbus1_fclk_1",
2192 .ops
= &clkops_omap2_dflt
,
2193 .enable_reg
= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL
,
2194 .enable_bit
= OMAP4430_OPTFCLKEN_FCLK1_SHIFT
,
2195 .clkdm_name
= "abe_clkdm",
2196 .parent
= &func_24m_clk
,
2197 .recalc
= &followparent_recalc
,
2200 static struct clk slimbus1_fclk_0
= {
2201 .name
= "slimbus1_fclk_0",
2202 .ops
= &clkops_omap2_dflt
,
2203 .enable_reg
= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL
,
2204 .enable_bit
= OMAP4430_OPTFCLKEN_FCLK0_SHIFT
,
2205 .clkdm_name
= "abe_clkdm",
2206 .parent
= &abe_24m_fclk
,
2207 .recalc
= &followparent_recalc
,
2210 static struct clk slimbus1_fclk_2
= {
2211 .name
= "slimbus1_fclk_2",
2212 .ops
= &clkops_omap2_dflt
,
2213 .enable_reg
= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL
,
2214 .enable_bit
= OMAP4430_OPTFCLKEN_FCLK2_SHIFT
,
2215 .clkdm_name
= "abe_clkdm",
2216 .parent
= &pad_clks_ck
,
2217 .recalc
= &followparent_recalc
,
2220 static struct clk slimbus1_slimbus_clk
= {
2221 .name
= "slimbus1_slimbus_clk",
2222 .ops
= &clkops_omap2_dflt
,
2223 .enable_reg
= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL
,
2224 .enable_bit
= OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT
,
2225 .clkdm_name
= "abe_clkdm",
2226 .parent
= &slimbus_clk
,
2227 .recalc
= &followparent_recalc
,
2230 static struct clk slimbus1_fck
= {
2231 .name
= "slimbus1_fck",
2232 .ops
= &clkops_omap2_dflt
,
2233 .enable_reg
= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL
,
2234 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2235 .clkdm_name
= "abe_clkdm",
2236 .parent
= &ocp_abe_iclk
,
2237 .recalc
= &followparent_recalc
,
2240 static struct clk slimbus2_fclk_1
= {
2241 .name
= "slimbus2_fclk_1",
2242 .ops
= &clkops_omap2_dflt
,
2243 .enable_reg
= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL
,
2244 .enable_bit
= OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT
,
2245 .clkdm_name
= "l4_per_clkdm",
2246 .parent
= &per_abe_24m_fclk
,
2247 .recalc
= &followparent_recalc
,
2250 static struct clk slimbus2_fclk_0
= {
2251 .name
= "slimbus2_fclk_0",
2252 .ops
= &clkops_omap2_dflt
,
2253 .enable_reg
= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL
,
2254 .enable_bit
= OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT
,
2255 .clkdm_name
= "l4_per_clkdm",
2256 .parent
= &func_24mc_fclk
,
2257 .recalc
= &followparent_recalc
,
2260 static struct clk slimbus2_slimbus_clk
= {
2261 .name
= "slimbus2_slimbus_clk",
2262 .ops
= &clkops_omap2_dflt
,
2263 .enable_reg
= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL
,
2264 .enable_bit
= OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT
,
2265 .clkdm_name
= "l4_per_clkdm",
2266 .parent
= &pad_slimbus_core_clks_ck
,
2267 .recalc
= &followparent_recalc
,
2270 static struct clk slimbus2_fck
= {
2271 .name
= "slimbus2_fck",
2272 .ops
= &clkops_omap2_dflt
,
2273 .enable_reg
= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL
,
2274 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2275 .clkdm_name
= "l4_per_clkdm",
2276 .parent
= &l4_div_ck
,
2277 .recalc
= &followparent_recalc
,
2280 static struct clk smartreflex_core_fck
= {
2281 .name
= "smartreflex_core_fck",
2282 .ops
= &clkops_omap2_dflt
,
2283 .enable_reg
= OMAP4430_CM_ALWON_SR_CORE_CLKCTRL
,
2284 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2285 .clkdm_name
= "l4_ao_clkdm",
2286 .parent
= &l4_wkup_clk_mux_ck
,
2287 .recalc
= &followparent_recalc
,
2290 static struct clk smartreflex_iva_fck
= {
2291 .name
= "smartreflex_iva_fck",
2292 .ops
= &clkops_omap2_dflt
,
2293 .enable_reg
= OMAP4430_CM_ALWON_SR_IVA_CLKCTRL
,
2294 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2295 .clkdm_name
= "l4_ao_clkdm",
2296 .parent
= &l4_wkup_clk_mux_ck
,
2297 .recalc
= &followparent_recalc
,
2300 static struct clk smartreflex_mpu_fck
= {
2301 .name
= "smartreflex_mpu_fck",
2302 .ops
= &clkops_omap2_dflt
,
2303 .enable_reg
= OMAP4430_CM_ALWON_SR_MPU_CLKCTRL
,
2304 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2305 .clkdm_name
= "l4_ao_clkdm",
2306 .parent
= &l4_wkup_clk_mux_ck
,
2307 .recalc
= &followparent_recalc
,
2310 /* Merged dmt1_clk_mux into timer1 */
2311 static struct clk timer1_fck
= {
2312 .name
= "timer1_fck",
2313 .parent
= &sys_clkin_ck
,
2314 .clksel
= abe_dpll_bypass_clk_mux_sel
,
2315 .init
= &omap2_init_clksel_parent
,
2316 .clksel_reg
= OMAP4430_CM_WKUP_TIMER1_CLKCTRL
,
2317 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
2318 .ops
= &clkops_omap2_dflt
,
2319 .recalc
= &omap2_clksel_recalc
,
2320 .enable_reg
= OMAP4430_CM_WKUP_TIMER1_CLKCTRL
,
2321 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2322 .clkdm_name
= "l4_wkup_clkdm",
2325 /* Merged cm2_dm10_mux into timer10 */
2326 static struct clk timer10_fck
= {
2327 .name
= "timer10_fck",
2328 .parent
= &sys_clkin_ck
,
2329 .clksel
= abe_dpll_bypass_clk_mux_sel
,
2330 .init
= &omap2_init_clksel_parent
,
2331 .clksel_reg
= OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL
,
2332 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
2333 .ops
= &clkops_omap2_dflt
,
2334 .recalc
= &omap2_clksel_recalc
,
2335 .enable_reg
= OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL
,
2336 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2337 .clkdm_name
= "l4_per_clkdm",
2340 /* Merged cm2_dm11_mux into timer11 */
2341 static struct clk timer11_fck
= {
2342 .name
= "timer11_fck",
2343 .parent
= &sys_clkin_ck
,
2344 .clksel
= abe_dpll_bypass_clk_mux_sel
,
2345 .init
= &omap2_init_clksel_parent
,
2346 .clksel_reg
= OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL
,
2347 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
2348 .ops
= &clkops_omap2_dflt
,
2349 .recalc
= &omap2_clksel_recalc
,
2350 .enable_reg
= OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL
,
2351 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2352 .clkdm_name
= "l4_per_clkdm",
2355 /* Merged cm2_dm2_mux into timer2 */
2356 static struct clk timer2_fck
= {
2357 .name
= "timer2_fck",
2358 .parent
= &sys_clkin_ck
,
2359 .clksel
= abe_dpll_bypass_clk_mux_sel
,
2360 .init
= &omap2_init_clksel_parent
,
2361 .clksel_reg
= OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL
,
2362 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
2363 .ops
= &clkops_omap2_dflt
,
2364 .recalc
= &omap2_clksel_recalc
,
2365 .enable_reg
= OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL
,
2366 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2367 .clkdm_name
= "l4_per_clkdm",
2370 /* Merged cm2_dm3_mux into timer3 */
2371 static struct clk timer3_fck
= {
2372 .name
= "timer3_fck",
2373 .parent
= &sys_clkin_ck
,
2374 .clksel
= abe_dpll_bypass_clk_mux_sel
,
2375 .init
= &omap2_init_clksel_parent
,
2376 .clksel_reg
= OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL
,
2377 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
2378 .ops
= &clkops_omap2_dflt
,
2379 .recalc
= &omap2_clksel_recalc
,
2380 .enable_reg
= OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL
,
2381 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2382 .clkdm_name
= "l4_per_clkdm",
2385 /* Merged cm2_dm4_mux into timer4 */
2386 static struct clk timer4_fck
= {
2387 .name
= "timer4_fck",
2388 .parent
= &sys_clkin_ck
,
2389 .clksel
= abe_dpll_bypass_clk_mux_sel
,
2390 .init
= &omap2_init_clksel_parent
,
2391 .clksel_reg
= OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL
,
2392 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
2393 .ops
= &clkops_omap2_dflt
,
2394 .recalc
= &omap2_clksel_recalc
,
2395 .enable_reg
= OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL
,
2396 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2397 .clkdm_name
= "l4_per_clkdm",
2400 static const struct clksel timer5_sync_mux_sel
[] = {
2401 { .parent
= &syc_clk_div_ck
, .rates
= div_1_0_rates
},
2402 { .parent
= &sys_32k_ck
, .rates
= div_1_1_rates
},
2406 /* Merged timer5_sync_mux into timer5 */
2407 static struct clk timer5_fck
= {
2408 .name
= "timer5_fck",
2409 .parent
= &syc_clk_div_ck
,
2410 .clksel
= timer5_sync_mux_sel
,
2411 .init
= &omap2_init_clksel_parent
,
2412 .clksel_reg
= OMAP4430_CM1_ABE_TIMER5_CLKCTRL
,
2413 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
2414 .ops
= &clkops_omap2_dflt
,
2415 .recalc
= &omap2_clksel_recalc
,
2416 .enable_reg
= OMAP4430_CM1_ABE_TIMER5_CLKCTRL
,
2417 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2418 .clkdm_name
= "abe_clkdm",
2421 /* Merged timer6_sync_mux into timer6 */
2422 static struct clk timer6_fck
= {
2423 .name
= "timer6_fck",
2424 .parent
= &syc_clk_div_ck
,
2425 .clksel
= timer5_sync_mux_sel
,
2426 .init
= &omap2_init_clksel_parent
,
2427 .clksel_reg
= OMAP4430_CM1_ABE_TIMER6_CLKCTRL
,
2428 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
2429 .ops
= &clkops_omap2_dflt
,
2430 .recalc
= &omap2_clksel_recalc
,
2431 .enable_reg
= OMAP4430_CM1_ABE_TIMER6_CLKCTRL
,
2432 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2433 .clkdm_name
= "abe_clkdm",
2436 /* Merged timer7_sync_mux into timer7 */
2437 static struct clk timer7_fck
= {
2438 .name
= "timer7_fck",
2439 .parent
= &syc_clk_div_ck
,
2440 .clksel
= timer5_sync_mux_sel
,
2441 .init
= &omap2_init_clksel_parent
,
2442 .clksel_reg
= OMAP4430_CM1_ABE_TIMER7_CLKCTRL
,
2443 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
2444 .ops
= &clkops_omap2_dflt
,
2445 .recalc
= &omap2_clksel_recalc
,
2446 .enable_reg
= OMAP4430_CM1_ABE_TIMER7_CLKCTRL
,
2447 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2448 .clkdm_name
= "abe_clkdm",
2451 /* Merged timer8_sync_mux into timer8 */
2452 static struct clk timer8_fck
= {
2453 .name
= "timer8_fck",
2454 .parent
= &syc_clk_div_ck
,
2455 .clksel
= timer5_sync_mux_sel
,
2456 .init
= &omap2_init_clksel_parent
,
2457 .clksel_reg
= OMAP4430_CM1_ABE_TIMER8_CLKCTRL
,
2458 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
2459 .ops
= &clkops_omap2_dflt
,
2460 .recalc
= &omap2_clksel_recalc
,
2461 .enable_reg
= OMAP4430_CM1_ABE_TIMER8_CLKCTRL
,
2462 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2463 .clkdm_name
= "abe_clkdm",
2466 /* Merged cm2_dm9_mux into timer9 */
2467 static struct clk timer9_fck
= {
2468 .name
= "timer9_fck",
2469 .parent
= &sys_clkin_ck
,
2470 .clksel
= abe_dpll_bypass_clk_mux_sel
,
2471 .init
= &omap2_init_clksel_parent
,
2472 .clksel_reg
= OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL
,
2473 .clksel_mask
= OMAP4430_CLKSEL_MASK
,
2474 .ops
= &clkops_omap2_dflt
,
2475 .recalc
= &omap2_clksel_recalc
,
2476 .enable_reg
= OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL
,
2477 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2478 .clkdm_name
= "l4_per_clkdm",
2481 static struct clk uart1_fck
= {
2482 .name
= "uart1_fck",
2483 .ops
= &clkops_omap2_dflt
,
2484 .enable_reg
= OMAP4430_CM_L4PER_UART1_CLKCTRL
,
2485 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2486 .clkdm_name
= "l4_per_clkdm",
2487 .parent
= &func_48m_fclk
,
2488 .recalc
= &followparent_recalc
,
2491 static struct clk uart2_fck
= {
2492 .name
= "uart2_fck",
2493 .ops
= &clkops_omap2_dflt
,
2494 .enable_reg
= OMAP4430_CM_L4PER_UART2_CLKCTRL
,
2495 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2496 .clkdm_name
= "l4_per_clkdm",
2497 .parent
= &func_48m_fclk
,
2498 .recalc
= &followparent_recalc
,
2501 static struct clk uart3_fck
= {
2502 .name
= "uart3_fck",
2503 .ops
= &clkops_omap2_dflt
,
2504 .enable_reg
= OMAP4430_CM_L4PER_UART3_CLKCTRL
,
2505 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2506 .clkdm_name
= "l4_per_clkdm",
2507 .parent
= &func_48m_fclk
,
2508 .recalc
= &followparent_recalc
,
2511 static struct clk uart4_fck
= {
2512 .name
= "uart4_fck",
2513 .ops
= &clkops_omap2_dflt
,
2514 .enable_reg
= OMAP4430_CM_L4PER_UART4_CLKCTRL
,
2515 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2516 .clkdm_name
= "l4_per_clkdm",
2517 .parent
= &func_48m_fclk
,
2518 .recalc
= &followparent_recalc
,
2521 static struct clk usb_host_fs_fck
= {
2522 .name
= "usb_host_fs_fck",
2523 .ops
= &clkops_omap2_dflt
,
2524 .enable_reg
= OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL
,
2525 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2526 .clkdm_name
= "l3_init_clkdm",
2527 .parent
= &func_48mc_fclk
,
2528 .recalc
= &followparent_recalc
,
2531 static const struct clksel utmi_p1_gfclk_sel
[] = {
2532 { .parent
= &init_60m_fclk
, .rates
= div_1_0_rates
},
2533 { .parent
= &xclk60mhsp1_ck
, .rates
= div_1_1_rates
},
2537 static struct clk utmi_p1_gfclk
= {
2538 .name
= "utmi_p1_gfclk",
2539 .parent
= &init_60m_fclk
,
2540 .clksel
= utmi_p1_gfclk_sel
,
2541 .init
= &omap2_init_clksel_parent
,
2542 .clksel_reg
= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL
,
2543 .clksel_mask
= OMAP4430_CLKSEL_UTMI_P1_MASK
,
2544 .ops
= &clkops_null
,
2545 .recalc
= &omap2_clksel_recalc
,
2548 static struct clk usb_host_hs_utmi_p1_clk
= {
2549 .name
= "usb_host_hs_utmi_p1_clk",
2550 .ops
= &clkops_omap2_dflt
,
2551 .enable_reg
= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL
,
2552 .enable_bit
= OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT
,
2553 .clkdm_name
= "l3_init_clkdm",
2554 .parent
= &utmi_p1_gfclk
,
2555 .recalc
= &followparent_recalc
,
2558 static const struct clksel utmi_p2_gfclk_sel
[] = {
2559 { .parent
= &init_60m_fclk
, .rates
= div_1_0_rates
},
2560 { .parent
= &xclk60mhsp2_ck
, .rates
= div_1_1_rates
},
2564 static struct clk utmi_p2_gfclk
= {
2565 .name
= "utmi_p2_gfclk",
2566 .parent
= &init_60m_fclk
,
2567 .clksel
= utmi_p2_gfclk_sel
,
2568 .init
= &omap2_init_clksel_parent
,
2569 .clksel_reg
= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL
,
2570 .clksel_mask
= OMAP4430_CLKSEL_UTMI_P2_MASK
,
2571 .ops
= &clkops_null
,
2572 .recalc
= &omap2_clksel_recalc
,
2575 static struct clk usb_host_hs_utmi_p2_clk
= {
2576 .name
= "usb_host_hs_utmi_p2_clk",
2577 .ops
= &clkops_omap2_dflt
,
2578 .enable_reg
= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL
,
2579 .enable_bit
= OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT
,
2580 .clkdm_name
= "l3_init_clkdm",
2581 .parent
= &utmi_p2_gfclk
,
2582 .recalc
= &followparent_recalc
,
2585 static struct clk usb_host_hs_utmi_p3_clk
= {
2586 .name
= "usb_host_hs_utmi_p3_clk",
2587 .ops
= &clkops_omap2_dflt
,
2588 .enable_reg
= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL
,
2589 .enable_bit
= OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT
,
2590 .clkdm_name
= "l3_init_clkdm",
2591 .parent
= &init_60m_fclk
,
2592 .recalc
= &followparent_recalc
,
2595 static struct clk usb_host_hs_hsic480m_p1_clk
= {
2596 .name
= "usb_host_hs_hsic480m_p1_clk",
2597 .ops
= &clkops_omap2_dflt
,
2598 .enable_reg
= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL
,
2599 .enable_bit
= OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT
,
2600 .clkdm_name
= "l3_init_clkdm",
2601 .parent
= &dpll_usb_m2_ck
,
2602 .recalc
= &followparent_recalc
,
2605 static struct clk usb_host_hs_hsic60m_p1_clk
= {
2606 .name
= "usb_host_hs_hsic60m_p1_clk",
2607 .ops
= &clkops_omap2_dflt
,
2608 .enable_reg
= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL
,
2609 .enable_bit
= OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT
,
2610 .clkdm_name
= "l3_init_clkdm",
2611 .parent
= &init_60m_fclk
,
2612 .recalc
= &followparent_recalc
,
2615 static struct clk usb_host_hs_hsic60m_p2_clk
= {
2616 .name
= "usb_host_hs_hsic60m_p2_clk",
2617 .ops
= &clkops_omap2_dflt
,
2618 .enable_reg
= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL
,
2619 .enable_bit
= OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT
,
2620 .clkdm_name
= "l3_init_clkdm",
2621 .parent
= &init_60m_fclk
,
2622 .recalc
= &followparent_recalc
,
2625 static struct clk usb_host_hs_hsic480m_p2_clk
= {
2626 .name
= "usb_host_hs_hsic480m_p2_clk",
2627 .ops
= &clkops_omap2_dflt
,
2628 .enable_reg
= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL
,
2629 .enable_bit
= OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT
,
2630 .clkdm_name
= "l3_init_clkdm",
2631 .parent
= &dpll_usb_m2_ck
,
2632 .recalc
= &followparent_recalc
,
2635 static struct clk usb_host_hs_func48mclk
= {
2636 .name
= "usb_host_hs_func48mclk",
2637 .ops
= &clkops_omap2_dflt
,
2638 .enable_reg
= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL
,
2639 .enable_bit
= OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT
,
2640 .clkdm_name
= "l3_init_clkdm",
2641 .parent
= &func_48mc_fclk
,
2642 .recalc
= &followparent_recalc
,
2645 static struct clk usb_host_hs_fck
= {
2646 .name
= "usb_host_hs_fck",
2647 .ops
= &clkops_omap2_dflt
,
2648 .enable_reg
= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL
,
2649 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2650 .clkdm_name
= "l3_init_clkdm",
2651 .parent
= &init_60m_fclk
,
2652 .recalc
= &followparent_recalc
,
2655 static const struct clksel otg_60m_gfclk_sel
[] = {
2656 { .parent
= &utmi_phy_clkout_ck
, .rates
= div_1_0_rates
},
2657 { .parent
= &xclk60motg_ck
, .rates
= div_1_1_rates
},
2661 static struct clk otg_60m_gfclk
= {
2662 .name
= "otg_60m_gfclk",
2663 .parent
= &utmi_phy_clkout_ck
,
2664 .clksel
= otg_60m_gfclk_sel
,
2665 .init
= &omap2_init_clksel_parent
,
2666 .clksel_reg
= OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL
,
2667 .clksel_mask
= OMAP4430_CLKSEL_60M_MASK
,
2668 .ops
= &clkops_null
,
2669 .recalc
= &omap2_clksel_recalc
,
2672 static struct clk usb_otg_hs_xclk
= {
2673 .name
= "usb_otg_hs_xclk",
2674 .ops
= &clkops_omap2_dflt
,
2675 .enable_reg
= OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL
,
2676 .enable_bit
= OMAP4430_OPTFCLKEN_XCLK_SHIFT
,
2677 .clkdm_name
= "l3_init_clkdm",
2678 .parent
= &otg_60m_gfclk
,
2679 .recalc
= &followparent_recalc
,
2682 static struct clk usb_otg_hs_ick
= {
2683 .name
= "usb_otg_hs_ick",
2684 .ops
= &clkops_omap2_dflt
,
2685 .enable_reg
= OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL
,
2686 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
2687 .clkdm_name
= "l3_init_clkdm",
2688 .parent
= &l3_div_ck
,
2689 .recalc
= &followparent_recalc
,
2692 static struct clk usb_phy_cm_clk32k
= {
2693 .name
= "usb_phy_cm_clk32k",
2694 .ops
= &clkops_omap2_dflt
,
2695 .enable_reg
= OMAP4430_CM_ALWON_USBPHY_CLKCTRL
,
2696 .enable_bit
= OMAP4430_OPTFCLKEN_CLK32K_SHIFT
,
2697 .clkdm_name
= "l4_ao_clkdm",
2698 .parent
= &sys_32k_ck
,
2699 .recalc
= &followparent_recalc
,
2702 static struct clk usb_tll_hs_usb_ch2_clk
= {
2703 .name
= "usb_tll_hs_usb_ch2_clk",
2704 .ops
= &clkops_omap2_dflt
,
2705 .enable_reg
= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL
,
2706 .enable_bit
= OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT
,
2707 .clkdm_name
= "l3_init_clkdm",
2708 .parent
= &init_60m_fclk
,
2709 .recalc
= &followparent_recalc
,
2712 static struct clk usb_tll_hs_usb_ch0_clk
= {
2713 .name
= "usb_tll_hs_usb_ch0_clk",
2714 .ops
= &clkops_omap2_dflt
,
2715 .enable_reg
= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL
,
2716 .enable_bit
= OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT
,
2717 .clkdm_name
= "l3_init_clkdm",
2718 .parent
= &init_60m_fclk
,
2719 .recalc
= &followparent_recalc
,
2722 static struct clk usb_tll_hs_usb_ch1_clk
= {
2723 .name
= "usb_tll_hs_usb_ch1_clk",
2724 .ops
= &clkops_omap2_dflt
,
2725 .enable_reg
= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL
,
2726 .enable_bit
= OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT
,
2727 .clkdm_name
= "l3_init_clkdm",
2728 .parent
= &init_60m_fclk
,
2729 .recalc
= &followparent_recalc
,
2732 static struct clk usb_tll_hs_ick
= {
2733 .name
= "usb_tll_hs_ick",
2734 .ops
= &clkops_omap2_dflt
,
2735 .enable_reg
= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL
,
2736 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
2737 .clkdm_name
= "l3_init_clkdm",
2738 .parent
= &l4_div_ck
,
2739 .recalc
= &followparent_recalc
,
2742 static const struct clksel_rate div2_14to18_rates
[] = {
2743 { .div
= 14, .val
= 0, .flags
= RATE_IN_4430
},
2744 { .div
= 18, .val
= 1, .flags
= RATE_IN_4430
},
2748 static const struct clksel usim_fclk_div
[] = {
2749 { .parent
= &dpll_per_m4x2_ck
, .rates
= div2_14to18_rates
},
2753 static struct clk usim_ck
= {
2755 .parent
= &dpll_per_m4x2_ck
,
2756 .clksel
= usim_fclk_div
,
2757 .clksel_reg
= OMAP4430_CM_WKUP_USIM_CLKCTRL
,
2758 .clksel_mask
= OMAP4430_CLKSEL_DIV_MASK
,
2759 .ops
= &clkops_null
,
2760 .recalc
= &omap2_clksel_recalc
,
2761 .round_rate
= &omap2_clksel_round_rate
,
2762 .set_rate
= &omap2_clksel_set_rate
,
2765 static struct clk usim_fclk
= {
2766 .name
= "usim_fclk",
2767 .ops
= &clkops_omap2_dflt
,
2768 .enable_reg
= OMAP4430_CM_WKUP_USIM_CLKCTRL
,
2769 .enable_bit
= OMAP4430_OPTFCLKEN_FCLK_SHIFT
,
2770 .clkdm_name
= "l4_wkup_clkdm",
2772 .recalc
= &followparent_recalc
,
2775 static struct clk usim_fck
= {
2777 .ops
= &clkops_omap2_dflt
,
2778 .enable_reg
= OMAP4430_CM_WKUP_USIM_CLKCTRL
,
2779 .enable_bit
= OMAP4430_MODULEMODE_HWCTRL
,
2780 .clkdm_name
= "l4_wkup_clkdm",
2781 .parent
= &sys_32k_ck
,
2782 .recalc
= &followparent_recalc
,
2785 static struct clk wd_timer2_fck
= {
2786 .name
= "wd_timer2_fck",
2787 .ops
= &clkops_omap2_dflt
,
2788 .enable_reg
= OMAP4430_CM_WKUP_WDT2_CLKCTRL
,
2789 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2790 .clkdm_name
= "l4_wkup_clkdm",
2791 .parent
= &sys_32k_ck
,
2792 .recalc
= &followparent_recalc
,
2795 static struct clk wd_timer3_fck
= {
2796 .name
= "wd_timer3_fck",
2797 .ops
= &clkops_omap2_dflt
,
2798 .enable_reg
= OMAP4430_CM1_ABE_WDT3_CLKCTRL
,
2799 .enable_bit
= OMAP4430_MODULEMODE_SWCTRL
,
2800 .clkdm_name
= "abe_clkdm",
2801 .parent
= &sys_32k_ck
,
2802 .recalc
= &followparent_recalc
,
2805 /* Remaining optional clocks */
2806 static const struct clksel stm_clk_div_div
[] = {
2807 { .parent
= &pmd_stm_clock_mux_ck
, .rates
= div3_1to4_rates
},
2811 static struct clk stm_clk_div_ck
= {
2812 .name
= "stm_clk_div_ck",
2813 .parent
= &pmd_stm_clock_mux_ck
,
2814 .clksel
= stm_clk_div_div
,
2815 .clksel_reg
= OMAP4430_CM_EMU_DEBUGSS_CLKCTRL
,
2816 .clksel_mask
= OMAP4430_CLKSEL_PMD_STM_CLK_MASK
,
2817 .ops
= &clkops_null
,
2818 .recalc
= &omap2_clksel_recalc
,
2819 .round_rate
= &omap2_clksel_round_rate
,
2820 .set_rate
= &omap2_clksel_set_rate
,
2823 static const struct clksel trace_clk_div_div
[] = {
2824 { .parent
= &pmd_trace_clk_mux_ck
, .rates
= div3_1to4_rates
},
2828 static struct clk trace_clk_div_ck
= {
2829 .name
= "trace_clk_div_ck",
2830 .parent
= &pmd_trace_clk_mux_ck
,
2831 .clkdm_name
= "emu_sys_clkdm",
2832 .clksel
= trace_clk_div_div
,
2833 .clksel_reg
= OMAP4430_CM_EMU_DEBUGSS_CLKCTRL
,
2834 .clksel_mask
= OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK
,
2835 .ops
= &clkops_null
,
2836 .recalc
= &omap2_clksel_recalc
,
2837 .round_rate
= &omap2_clksel_round_rate
,
2838 .set_rate
= &omap2_clksel_set_rate
,
2841 /* SCRM aux clk nodes */
2843 static const struct clksel auxclk_src_sel
[] = {
2844 { .parent
= &sys_clkin_ck
, .rates
= div_1_0_rates
},
2845 { .parent
= &dpll_core_m3x2_ck
, .rates
= div_1_1_rates
},
2846 { .parent
= &dpll_per_m3x2_ck
, .rates
= div_1_2_rates
},
2850 static const struct clksel_rate div16_1to16_rates
[] = {
2851 { .div
= 1, .val
= 0, .flags
= RATE_IN_4430
},
2852 { .div
= 2, .val
= 1, .flags
= RATE_IN_4430
},
2853 { .div
= 3, .val
= 2, .flags
= RATE_IN_4430
},
2854 { .div
= 4, .val
= 3, .flags
= RATE_IN_4430
},
2855 { .div
= 5, .val
= 4, .flags
= RATE_IN_4430
},
2856 { .div
= 6, .val
= 5, .flags
= RATE_IN_4430
},
2857 { .div
= 7, .val
= 6, .flags
= RATE_IN_4430
},
2858 { .div
= 8, .val
= 7, .flags
= RATE_IN_4430
},
2859 { .div
= 9, .val
= 8, .flags
= RATE_IN_4430
},
2860 { .div
= 10, .val
= 9, .flags
= RATE_IN_4430
},
2861 { .div
= 11, .val
= 10, .flags
= RATE_IN_4430
},
2862 { .div
= 12, .val
= 11, .flags
= RATE_IN_4430
},
2863 { .div
= 13, .val
= 12, .flags
= RATE_IN_4430
},
2864 { .div
= 14, .val
= 13, .flags
= RATE_IN_4430
},
2865 { .div
= 15, .val
= 14, .flags
= RATE_IN_4430
},
2866 { .div
= 16, .val
= 15, .flags
= RATE_IN_4430
},
2870 static struct clk auxclk0_src_ck
= {
2871 .name
= "auxclk0_src_ck",
2872 .parent
= &sys_clkin_ck
,
2873 .init
= &omap2_init_clksel_parent
,
2874 .ops
= &clkops_omap2_dflt
,
2875 .clksel
= auxclk_src_sel
,
2876 .clksel_reg
= OMAP4_SCRM_AUXCLK0
,
2877 .clksel_mask
= OMAP4_SRCSELECT_MASK
,
2878 .recalc
= &omap2_clksel_recalc
,
2879 .enable_reg
= OMAP4_SCRM_AUXCLK0
,
2880 .enable_bit
= OMAP4_ENABLE_SHIFT
,
2883 static const struct clksel auxclk0_sel
[] = {
2884 { .parent
= &auxclk0_src_ck
, .rates
= div16_1to16_rates
},
2888 static struct clk auxclk0_ck
= {
2889 .name
= "auxclk0_ck",
2890 .parent
= &auxclk0_src_ck
,
2891 .clksel
= auxclk0_sel
,
2892 .clksel_reg
= OMAP4_SCRM_AUXCLK0
,
2893 .clksel_mask
= OMAP4_CLKDIV_MASK
,
2894 .ops
= &clkops_null
,
2895 .recalc
= &omap2_clksel_recalc
,
2896 .round_rate
= &omap2_clksel_round_rate
,
2897 .set_rate
= &omap2_clksel_set_rate
,
2900 static struct clk auxclk1_src_ck
= {
2901 .name
= "auxclk1_src_ck",
2902 .parent
= &sys_clkin_ck
,
2903 .init
= &omap2_init_clksel_parent
,
2904 .ops
= &clkops_omap2_dflt
,
2905 .clksel
= auxclk_src_sel
,
2906 .clksel_reg
= OMAP4_SCRM_AUXCLK1
,
2907 .clksel_mask
= OMAP4_SRCSELECT_MASK
,
2908 .recalc
= &omap2_clksel_recalc
,
2909 .enable_reg
= OMAP4_SCRM_AUXCLK1
,
2910 .enable_bit
= OMAP4_ENABLE_SHIFT
,
2913 static const struct clksel auxclk1_sel
[] = {
2914 { .parent
= &auxclk1_src_ck
, .rates
= div16_1to16_rates
},
2918 static struct clk auxclk1_ck
= {
2919 .name
= "auxclk1_ck",
2920 .parent
= &auxclk1_src_ck
,
2921 .clksel
= auxclk1_sel
,
2922 .clksel_reg
= OMAP4_SCRM_AUXCLK1
,
2923 .clksel_mask
= OMAP4_CLKDIV_MASK
,
2924 .ops
= &clkops_null
,
2925 .recalc
= &omap2_clksel_recalc
,
2926 .round_rate
= &omap2_clksel_round_rate
,
2927 .set_rate
= &omap2_clksel_set_rate
,
2930 static struct clk auxclk2_src_ck
= {
2931 .name
= "auxclk2_src_ck",
2932 .parent
= &sys_clkin_ck
,
2933 .init
= &omap2_init_clksel_parent
,
2934 .ops
= &clkops_omap2_dflt
,
2935 .clksel
= auxclk_src_sel
,
2936 .clksel_reg
= OMAP4_SCRM_AUXCLK2
,
2937 .clksel_mask
= OMAP4_SRCSELECT_MASK
,
2938 .recalc
= &omap2_clksel_recalc
,
2939 .enable_reg
= OMAP4_SCRM_AUXCLK2
,
2940 .enable_bit
= OMAP4_ENABLE_SHIFT
,
2943 static const struct clksel auxclk2_sel
[] = {
2944 { .parent
= &auxclk2_src_ck
, .rates
= div16_1to16_rates
},
2948 static struct clk auxclk2_ck
= {
2949 .name
= "auxclk2_ck",
2950 .parent
= &auxclk2_src_ck
,
2951 .clksel
= auxclk2_sel
,
2952 .clksel_reg
= OMAP4_SCRM_AUXCLK2
,
2953 .clksel_mask
= OMAP4_CLKDIV_MASK
,
2954 .ops
= &clkops_null
,
2955 .recalc
= &omap2_clksel_recalc
,
2956 .round_rate
= &omap2_clksel_round_rate
,
2957 .set_rate
= &omap2_clksel_set_rate
,
2960 static struct clk auxclk3_src_ck
= {
2961 .name
= "auxclk3_src_ck",
2962 .parent
= &sys_clkin_ck
,
2963 .init
= &omap2_init_clksel_parent
,
2964 .ops
= &clkops_omap2_dflt
,
2965 .clksel
= auxclk_src_sel
,
2966 .clksel_reg
= OMAP4_SCRM_AUXCLK3
,
2967 .clksel_mask
= OMAP4_SRCSELECT_MASK
,
2968 .recalc
= &omap2_clksel_recalc
,
2969 .enable_reg
= OMAP4_SCRM_AUXCLK3
,
2970 .enable_bit
= OMAP4_ENABLE_SHIFT
,
2973 static const struct clksel auxclk3_sel
[] = {
2974 { .parent
= &auxclk3_src_ck
, .rates
= div16_1to16_rates
},
2978 static struct clk auxclk3_ck
= {
2979 .name
= "auxclk3_ck",
2980 .parent
= &auxclk3_src_ck
,
2981 .clksel
= auxclk3_sel
,
2982 .clksel_reg
= OMAP4_SCRM_AUXCLK3
,
2983 .clksel_mask
= OMAP4_CLKDIV_MASK
,
2984 .ops
= &clkops_null
,
2985 .recalc
= &omap2_clksel_recalc
,
2986 .round_rate
= &omap2_clksel_round_rate
,
2987 .set_rate
= &omap2_clksel_set_rate
,
2990 static struct clk auxclk4_src_ck
= {
2991 .name
= "auxclk4_src_ck",
2992 .parent
= &sys_clkin_ck
,
2993 .init
= &omap2_init_clksel_parent
,
2994 .ops
= &clkops_omap2_dflt
,
2995 .clksel
= auxclk_src_sel
,
2996 .clksel_reg
= OMAP4_SCRM_AUXCLK4
,
2997 .clksel_mask
= OMAP4_SRCSELECT_MASK
,
2998 .recalc
= &omap2_clksel_recalc
,
2999 .enable_reg
= OMAP4_SCRM_AUXCLK4
,
3000 .enable_bit
= OMAP4_ENABLE_SHIFT
,
3003 static const struct clksel auxclk4_sel
[] = {
3004 { .parent
= &auxclk4_src_ck
, .rates
= div16_1to16_rates
},
3008 static struct clk auxclk4_ck
= {
3009 .name
= "auxclk4_ck",
3010 .parent
= &auxclk4_src_ck
,
3011 .clksel
= auxclk4_sel
,
3012 .clksel_reg
= OMAP4_SCRM_AUXCLK4
,
3013 .clksel_mask
= OMAP4_CLKDIV_MASK
,
3014 .ops
= &clkops_null
,
3015 .recalc
= &omap2_clksel_recalc
,
3016 .round_rate
= &omap2_clksel_round_rate
,
3017 .set_rate
= &omap2_clksel_set_rate
,
3020 static struct clk auxclk5_src_ck
= {
3021 .name
= "auxclk5_src_ck",
3022 .parent
= &sys_clkin_ck
,
3023 .init
= &omap2_init_clksel_parent
,
3024 .ops
= &clkops_omap2_dflt
,
3025 .clksel
= auxclk_src_sel
,
3026 .clksel_reg
= OMAP4_SCRM_AUXCLK5
,
3027 .clksel_mask
= OMAP4_SRCSELECT_MASK
,
3028 .recalc
= &omap2_clksel_recalc
,
3029 .enable_reg
= OMAP4_SCRM_AUXCLK5
,
3030 .enable_bit
= OMAP4_ENABLE_SHIFT
,
3033 static const struct clksel auxclk5_sel
[] = {
3034 { .parent
= &auxclk5_src_ck
, .rates
= div16_1to16_rates
},
3038 static struct clk auxclk5_ck
= {
3039 .name
= "auxclk5_ck",
3040 .parent
= &auxclk5_src_ck
,
3041 .clksel
= auxclk5_sel
,
3042 .clksel_reg
= OMAP4_SCRM_AUXCLK5
,
3043 .clksel_mask
= OMAP4_CLKDIV_MASK
,
3044 .ops
= &clkops_null
,
3045 .recalc
= &omap2_clksel_recalc
,
3046 .round_rate
= &omap2_clksel_round_rate
,
3047 .set_rate
= &omap2_clksel_set_rate
,
3050 static const struct clksel auxclkreq_sel
[] = {
3051 { .parent
= &auxclk0_ck
, .rates
= div_1_0_rates
},
3052 { .parent
= &auxclk1_ck
, .rates
= div_1_1_rates
},
3053 { .parent
= &auxclk2_ck
, .rates
= div_1_2_rates
},
3054 { .parent
= &auxclk3_ck
, .rates
= div_1_3_rates
},
3055 { .parent
= &auxclk4_ck
, .rates
= div_1_4_rates
},
3056 { .parent
= &auxclk5_ck
, .rates
= div_1_5_rates
},
3060 static struct clk auxclkreq0_ck
= {
3061 .name
= "auxclkreq0_ck",
3062 .parent
= &auxclk0_ck
,
3063 .init
= &omap2_init_clksel_parent
,
3064 .ops
= &clkops_null
,
3065 .clksel
= auxclkreq_sel
,
3066 .clksel_reg
= OMAP4_SCRM_AUXCLKREQ0
,
3067 .clksel_mask
= OMAP4_MAPPING_MASK
,
3068 .recalc
= &omap2_clksel_recalc
,
3071 static struct clk auxclkreq1_ck
= {
3072 .name
= "auxclkreq1_ck",
3073 .parent
= &auxclk1_ck
,
3074 .init
= &omap2_init_clksel_parent
,
3075 .ops
= &clkops_null
,
3076 .clksel
= auxclkreq_sel
,
3077 .clksel_reg
= OMAP4_SCRM_AUXCLKREQ1
,
3078 .clksel_mask
= OMAP4_MAPPING_MASK
,
3079 .recalc
= &omap2_clksel_recalc
,
3082 static struct clk auxclkreq2_ck
= {
3083 .name
= "auxclkreq2_ck",
3084 .parent
= &auxclk2_ck
,
3085 .init
= &omap2_init_clksel_parent
,
3086 .ops
= &clkops_null
,
3087 .clksel
= auxclkreq_sel
,
3088 .clksel_reg
= OMAP4_SCRM_AUXCLKREQ2
,
3089 .clksel_mask
= OMAP4_MAPPING_MASK
,
3090 .recalc
= &omap2_clksel_recalc
,
3093 static struct clk auxclkreq3_ck
= {
3094 .name
= "auxclkreq3_ck",
3095 .parent
= &auxclk3_ck
,
3096 .init
= &omap2_init_clksel_parent
,
3097 .ops
= &clkops_null
,
3098 .clksel
= auxclkreq_sel
,
3099 .clksel_reg
= OMAP4_SCRM_AUXCLKREQ3
,
3100 .clksel_mask
= OMAP4_MAPPING_MASK
,
3101 .recalc
= &omap2_clksel_recalc
,
3104 static struct clk auxclkreq4_ck
= {
3105 .name
= "auxclkreq4_ck",
3106 .parent
= &auxclk4_ck
,
3107 .init
= &omap2_init_clksel_parent
,
3108 .ops
= &clkops_null
,
3109 .clksel
= auxclkreq_sel
,
3110 .clksel_reg
= OMAP4_SCRM_AUXCLKREQ4
,
3111 .clksel_mask
= OMAP4_MAPPING_MASK
,
3112 .recalc
= &omap2_clksel_recalc
,
3115 static struct clk auxclkreq5_ck
= {
3116 .name
= "auxclkreq5_ck",
3117 .parent
= &auxclk5_ck
,
3118 .init
= &omap2_init_clksel_parent
,
3119 .ops
= &clkops_null
,
3120 .clksel
= auxclkreq_sel
,
3121 .clksel_reg
= OMAP4_SCRM_AUXCLKREQ5
,
3122 .clksel_mask
= OMAP4_MAPPING_MASK
,
3123 .recalc
= &omap2_clksel_recalc
,
3130 static struct omap_clk omap44xx_clks
[] = {
3131 CLK(NULL
, "extalt_clkin_ck", &extalt_clkin_ck
, CK_443X
),
3132 CLK(NULL
, "pad_clks_ck", &pad_clks_ck
, CK_443X
),
3133 CLK(NULL
, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck
, CK_443X
),
3134 CLK(NULL
, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck
, CK_443X
),
3135 CLK(NULL
, "slimbus_clk", &slimbus_clk
, CK_443X
),
3136 CLK(NULL
, "sys_32k_ck", &sys_32k_ck
, CK_443X
),
3137 CLK(NULL
, "virt_12000000_ck", &virt_12000000_ck
, CK_443X
),
3138 CLK(NULL
, "virt_13000000_ck", &virt_13000000_ck
, CK_443X
),
3139 CLK(NULL
, "virt_16800000_ck", &virt_16800000_ck
, CK_443X
),
3140 CLK(NULL
, "virt_19200000_ck", &virt_19200000_ck
, CK_443X
),
3141 CLK(NULL
, "virt_26000000_ck", &virt_26000000_ck
, CK_443X
),
3142 CLK(NULL
, "virt_27000000_ck", &virt_27000000_ck
, CK_443X
),
3143 CLK(NULL
, "virt_38400000_ck", &virt_38400000_ck
, CK_443X
),
3144 CLK(NULL
, "sys_clkin_ck", &sys_clkin_ck
, CK_443X
),
3145 CLK(NULL
, "tie_low_clock_ck", &tie_low_clock_ck
, CK_443X
),
3146 CLK(NULL
, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck
, CK_443X
),
3147 CLK(NULL
, "xclk60mhsp1_ck", &xclk60mhsp1_ck
, CK_443X
),
3148 CLK(NULL
, "xclk60mhsp2_ck", &xclk60mhsp2_ck
, CK_443X
),
3149 CLK(NULL
, "xclk60motg_ck", &xclk60motg_ck
, CK_443X
),
3150 CLK(NULL
, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck
, CK_443X
),
3151 CLK(NULL
, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck
, CK_443X
),
3152 CLK(NULL
, "dpll_abe_ck", &dpll_abe_ck
, CK_443X
),
3153 CLK(NULL
, "dpll_abe_x2_ck", &dpll_abe_x2_ck
, CK_443X
),
3154 CLK(NULL
, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck
, CK_443X
),
3155 CLK(NULL
, "abe_24m_fclk", &abe_24m_fclk
, CK_443X
),
3156 CLK(NULL
, "abe_clk", &abe_clk
, CK_443X
),
3157 CLK(NULL
, "aess_fclk", &aess_fclk
, CK_443X
),
3158 CLK(NULL
, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck
, CK_443X
),
3159 CLK(NULL
, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck
, CK_443X
),
3160 CLK(NULL
, "dpll_core_ck", &dpll_core_ck
, CK_443X
),
3161 CLK(NULL
, "dpll_core_x2_ck", &dpll_core_x2_ck
, CK_443X
),
3162 CLK(NULL
, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck
, CK_443X
),
3163 CLK(NULL
, "dbgclk_mux_ck", &dbgclk_mux_ck
, CK_443X
),
3164 CLK(NULL
, "dpll_core_m2_ck", &dpll_core_m2_ck
, CK_443X
),
3165 CLK(NULL
, "ddrphy_ck", &ddrphy_ck
, CK_443X
),
3166 CLK(NULL
, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck
, CK_443X
),
3167 CLK(NULL
, "div_core_ck", &div_core_ck
, CK_443X
),
3168 CLK(NULL
, "div_iva_hs_clk", &div_iva_hs_clk
, CK_443X
),
3169 CLK(NULL
, "div_mpu_hs_clk", &div_mpu_hs_clk
, CK_443X
),
3170 CLK(NULL
, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck
, CK_443X
),
3171 CLK(NULL
, "dll_clk_div_ck", &dll_clk_div_ck
, CK_443X
),
3172 CLK(NULL
, "dpll_abe_m2_ck", &dpll_abe_m2_ck
, CK_443X
),
3173 CLK(NULL
, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck
, CK_443X
),
3174 CLK(NULL
, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck
, CK_443X
),
3175 CLK(NULL
, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck
, CK_443X
),
3176 CLK(NULL
, "dpll_iva_ck", &dpll_iva_ck
, CK_443X
),
3177 CLK(NULL
, "dpll_iva_x2_ck", &dpll_iva_x2_ck
, CK_443X
),
3178 CLK(NULL
, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck
, CK_443X
),
3179 CLK(NULL
, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck
, CK_443X
),
3180 CLK(NULL
, "dpll_mpu_ck", &dpll_mpu_ck
, CK_443X
),
3181 CLK(NULL
, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck
, CK_443X
),
3182 CLK(NULL
, "per_hs_clk_div_ck", &per_hs_clk_div_ck
, CK_443X
),
3183 CLK(NULL
, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck
, CK_443X
),
3184 CLK(NULL
, "dpll_per_ck", &dpll_per_ck
, CK_443X
),
3185 CLK(NULL
, "dpll_per_m2_ck", &dpll_per_m2_ck
, CK_443X
),
3186 CLK(NULL
, "dpll_per_x2_ck", &dpll_per_x2_ck
, CK_443X
),
3187 CLK(NULL
, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck
, CK_443X
),
3188 CLK(NULL
, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck
, CK_443X
),
3189 CLK(NULL
, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck
, CK_443X
),
3190 CLK(NULL
, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck
, CK_443X
),
3191 CLK(NULL
, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck
, CK_443X
),
3192 CLK(NULL
, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck
, CK_443X
),
3193 CLK(NULL
, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck
, CK_443X
),
3194 CLK(NULL
, "dpll_usb_ck", &dpll_usb_ck
, CK_443X
),
3195 CLK(NULL
, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck
, CK_443X
),
3196 CLK(NULL
, "dpll_usb_m2_ck", &dpll_usb_m2_ck
, CK_443X
),
3197 CLK(NULL
, "ducati_clk_mux_ck", &ducati_clk_mux_ck
, CK_443X
),
3198 CLK(NULL
, "func_12m_fclk", &func_12m_fclk
, CK_443X
),
3199 CLK(NULL
, "func_24m_clk", &func_24m_clk
, CK_443X
),
3200 CLK(NULL
, "func_24mc_fclk", &func_24mc_fclk
, CK_443X
),
3201 CLK(NULL
, "func_48m_fclk", &func_48m_fclk
, CK_443X
),
3202 CLK(NULL
, "func_48mc_fclk", &func_48mc_fclk
, CK_443X
),
3203 CLK(NULL
, "func_64m_fclk", &func_64m_fclk
, CK_443X
),
3204 CLK(NULL
, "func_96m_fclk", &func_96m_fclk
, CK_443X
),
3205 CLK(NULL
, "init_60m_fclk", &init_60m_fclk
, CK_443X
),
3206 CLK(NULL
, "l3_div_ck", &l3_div_ck
, CK_443X
),
3207 CLK(NULL
, "l4_div_ck", &l4_div_ck
, CK_443X
),
3208 CLK(NULL
, "lp_clk_div_ck", &lp_clk_div_ck
, CK_443X
),
3209 CLK(NULL
, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck
, CK_443X
),
3210 CLK("smp_twd", NULL
, &mpu_periphclk
, CK_443X
),
3211 CLK(NULL
, "ocp_abe_iclk", &ocp_abe_iclk
, CK_443X
),
3212 CLK(NULL
, "per_abe_24m_fclk", &per_abe_24m_fclk
, CK_443X
),
3213 CLK(NULL
, "per_abe_nc_fclk", &per_abe_nc_fclk
, CK_443X
),
3214 CLK(NULL
, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck
, CK_443X
),
3215 CLK(NULL
, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck
, CK_443X
),
3216 CLK(NULL
, "syc_clk_div_ck", &syc_clk_div_ck
, CK_443X
),
3217 CLK(NULL
, "aes1_fck", &aes1_fck
, CK_443X
),
3218 CLK(NULL
, "aes2_fck", &aes2_fck
, CK_443X
),
3219 CLK(NULL
, "aess_fck", &aess_fck
, CK_443X
),
3220 CLK(NULL
, "bandgap_fclk", &bandgap_fclk
, CK_443X
),
3221 CLK(NULL
, "bandgap_ts_fclk", &bandgap_ts_fclk
, CK_446X
),
3222 CLK(NULL
, "des3des_fck", &des3des_fck
, CK_443X
),
3223 CLK(NULL
, "div_ts_ck", &div_ts_ck
, CK_446X
),
3224 CLK(NULL
, "dmic_sync_mux_ck", &dmic_sync_mux_ck
, CK_443X
),
3225 CLK(NULL
, "dmic_fck", &dmic_fck
, CK_443X
),
3226 CLK(NULL
, "dsp_fck", &dsp_fck
, CK_443X
),
3227 CLK(NULL
, "dss_sys_clk", &dss_sys_clk
, CK_443X
),
3228 CLK(NULL
, "dss_tv_clk", &dss_tv_clk
, CK_443X
),
3229 CLK(NULL
, "dss_48mhz_clk", &dss_48mhz_clk
, CK_443X
),
3230 CLK(NULL
, "dss_dss_clk", &dss_dss_clk
, CK_443X
),
3231 CLK("omapdss_dss", "ick", &dss_fck
, CK_443X
),
3232 CLK(NULL
, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck
, CK_443X
),
3233 CLK(NULL
, "emif1_fck", &emif1_fck
, CK_443X
),
3234 CLK(NULL
, "emif2_fck", &emif2_fck
, CK_443X
),
3235 CLK(NULL
, "fdif_fck", &fdif_fck
, CK_443X
),
3236 CLK(NULL
, "fpka_fck", &fpka_fck
, CK_443X
),
3237 CLK(NULL
, "gpio1_dbclk", &gpio1_dbclk
, CK_443X
),
3238 CLK(NULL
, "gpio1_ick", &gpio1_ick
, CK_443X
),
3239 CLK(NULL
, "gpio2_dbclk", &gpio2_dbclk
, CK_443X
),
3240 CLK(NULL
, "gpio2_ick", &gpio2_ick
, CK_443X
),
3241 CLK(NULL
, "gpio3_dbclk", &gpio3_dbclk
, CK_443X
),
3242 CLK(NULL
, "gpio3_ick", &gpio3_ick
, CK_443X
),
3243 CLK(NULL
, "gpio4_dbclk", &gpio4_dbclk
, CK_443X
),
3244 CLK(NULL
, "gpio4_ick", &gpio4_ick
, CK_443X
),
3245 CLK(NULL
, "gpio5_dbclk", &gpio5_dbclk
, CK_443X
),
3246 CLK(NULL
, "gpio5_ick", &gpio5_ick
, CK_443X
),
3247 CLK(NULL
, "gpio6_dbclk", &gpio6_dbclk
, CK_443X
),
3248 CLK(NULL
, "gpio6_ick", &gpio6_ick
, CK_443X
),
3249 CLK(NULL
, "gpmc_ick", &gpmc_ick
, CK_443X
),
3250 CLK(NULL
, "gpu_fck", &gpu_fck
, CK_443X
),
3251 CLK(NULL
, "hdq1w_fck", &hdq1w_fck
, CK_443X
),
3252 CLK(NULL
, "hsi_fck", &hsi_fck
, CK_443X
),
3253 CLK(NULL
, "i2c1_fck", &i2c1_fck
, CK_443X
),
3254 CLK(NULL
, "i2c2_fck", &i2c2_fck
, CK_443X
),
3255 CLK(NULL
, "i2c3_fck", &i2c3_fck
, CK_443X
),
3256 CLK(NULL
, "i2c4_fck", &i2c4_fck
, CK_443X
),
3257 CLK(NULL
, "ipu_fck", &ipu_fck
, CK_443X
),
3258 CLK(NULL
, "iss_ctrlclk", &iss_ctrlclk
, CK_443X
),
3259 CLK(NULL
, "iss_fck", &iss_fck
, CK_443X
),
3260 CLK(NULL
, "iva_fck", &iva_fck
, CK_443X
),
3261 CLK(NULL
, "kbd_fck", &kbd_fck
, CK_443X
),
3262 CLK(NULL
, "l3_instr_ick", &l3_instr_ick
, CK_443X
),
3263 CLK(NULL
, "l3_main_3_ick", &l3_main_3_ick
, CK_443X
),
3264 CLK(NULL
, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck
, CK_443X
),
3265 CLK(NULL
, "mcasp_fck", &mcasp_fck
, CK_443X
),
3266 CLK(NULL
, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck
, CK_443X
),
3267 CLK(NULL
, "mcbsp1_fck", &mcbsp1_fck
, CK_443X
),
3268 CLK(NULL
, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck
, CK_443X
),
3269 CLK(NULL
, "mcbsp2_fck", &mcbsp2_fck
, CK_443X
),
3270 CLK(NULL
, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck
, CK_443X
),
3271 CLK(NULL
, "mcbsp3_fck", &mcbsp3_fck
, CK_443X
),
3272 CLK(NULL
, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck
, CK_443X
),
3273 CLK(NULL
, "mcbsp4_fck", &mcbsp4_fck
, CK_443X
),
3274 CLK(NULL
, "mcpdm_fck", &mcpdm_fck
, CK_443X
),
3275 CLK(NULL
, "mcspi1_fck", &mcspi1_fck
, CK_443X
),
3276 CLK(NULL
, "mcspi2_fck", &mcspi2_fck
, CK_443X
),
3277 CLK(NULL
, "mcspi3_fck", &mcspi3_fck
, CK_443X
),
3278 CLK(NULL
, "mcspi4_fck", &mcspi4_fck
, CK_443X
),
3279 CLK(NULL
, "mmc1_fck", &mmc1_fck
, CK_443X
),
3280 CLK(NULL
, "mmc2_fck", &mmc2_fck
, CK_443X
),
3281 CLK(NULL
, "mmc3_fck", &mmc3_fck
, CK_443X
),
3282 CLK(NULL
, "mmc4_fck", &mmc4_fck
, CK_443X
),
3283 CLK(NULL
, "mmc5_fck", &mmc5_fck
, CK_443X
),
3284 CLK(NULL
, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m
, CK_443X
),
3285 CLK(NULL
, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick
, CK_443X
),
3286 CLK(NULL
, "ocp_wp_noc_ick", &ocp_wp_noc_ick
, CK_443X
),
3287 CLK("omap_rng", "ick", &rng_ick
, CK_443X
),
3288 CLK(NULL
, "sha2md5_fck", &sha2md5_fck
, CK_443X
),
3289 CLK(NULL
, "sl2if_ick", &sl2if_ick
, CK_443X
),
3290 CLK(NULL
, "slimbus1_fclk_1", &slimbus1_fclk_1
, CK_443X
),
3291 CLK(NULL
, "slimbus1_fclk_0", &slimbus1_fclk_0
, CK_443X
),
3292 CLK(NULL
, "slimbus1_fclk_2", &slimbus1_fclk_2
, CK_443X
),
3293 CLK(NULL
, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk
, CK_443X
),
3294 CLK(NULL
, "slimbus1_fck", &slimbus1_fck
, CK_443X
),
3295 CLK(NULL
, "slimbus2_fclk_1", &slimbus2_fclk_1
, CK_443X
),
3296 CLK(NULL
, "slimbus2_fclk_0", &slimbus2_fclk_0
, CK_443X
),
3297 CLK(NULL
, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk
, CK_443X
),
3298 CLK(NULL
, "slimbus2_fck", &slimbus2_fck
, CK_443X
),
3299 CLK(NULL
, "smartreflex_core_fck", &smartreflex_core_fck
, CK_443X
),
3300 CLK(NULL
, "smartreflex_iva_fck", &smartreflex_iva_fck
, CK_443X
),
3301 CLK(NULL
, "smartreflex_mpu_fck", &smartreflex_mpu_fck
, CK_443X
),
3302 CLK(NULL
, "gpt1_fck", &timer1_fck
, CK_443X
),
3303 CLK(NULL
, "gpt10_fck", &timer10_fck
, CK_443X
),
3304 CLK(NULL
, "gpt11_fck", &timer11_fck
, CK_443X
),
3305 CLK(NULL
, "gpt2_fck", &timer2_fck
, CK_443X
),
3306 CLK(NULL
, "gpt3_fck", &timer3_fck
, CK_443X
),
3307 CLK(NULL
, "gpt4_fck", &timer4_fck
, CK_443X
),
3308 CLK(NULL
, "gpt5_fck", &timer5_fck
, CK_443X
),
3309 CLK(NULL
, "gpt6_fck", &timer6_fck
, CK_443X
),
3310 CLK(NULL
, "gpt7_fck", &timer7_fck
, CK_443X
),
3311 CLK(NULL
, "gpt8_fck", &timer8_fck
, CK_443X
),
3312 CLK(NULL
, "gpt9_fck", &timer9_fck
, CK_443X
),
3313 CLK(NULL
, "uart1_fck", &uart1_fck
, CK_443X
),
3314 CLK(NULL
, "uart2_fck", &uart2_fck
, CK_443X
),
3315 CLK(NULL
, "uart3_fck", &uart3_fck
, CK_443X
),
3316 CLK(NULL
, "uart4_fck", &uart4_fck
, CK_443X
),
3317 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck
, CK_443X
),
3318 CLK(NULL
, "utmi_p1_gfclk", &utmi_p1_gfclk
, CK_443X
),
3319 CLK(NULL
, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk
, CK_443X
),
3320 CLK(NULL
, "utmi_p2_gfclk", &utmi_p2_gfclk
, CK_443X
),
3321 CLK(NULL
, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk
, CK_443X
),
3322 CLK(NULL
, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk
, CK_443X
),
3323 CLK(NULL
, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk
, CK_443X
),
3324 CLK(NULL
, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk
, CK_443X
),
3325 CLK(NULL
, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk
, CK_443X
),
3326 CLK(NULL
, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk
, CK_443X
),
3327 CLK(NULL
, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk
, CK_443X
),
3328 CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck
, CK_443X
),
3329 CLK(NULL
, "otg_60m_gfclk", &otg_60m_gfclk
, CK_443X
),
3330 CLK(NULL
, "usb_otg_hs_xclk", &usb_otg_hs_xclk
, CK_443X
),
3331 CLK("musb-omap2430", "ick", &usb_otg_hs_ick
, CK_443X
),
3332 CLK(NULL
, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k
, CK_443X
),
3333 CLK(NULL
, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk
, CK_443X
),
3334 CLK(NULL
, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk
, CK_443X
),
3335 CLK(NULL
, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk
, CK_443X
),
3336 CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick
, CK_443X
),
3337 CLK(NULL
, "usim_ck", &usim_ck
, CK_443X
),
3338 CLK(NULL
, "usim_fclk", &usim_fclk
, CK_443X
),
3339 CLK(NULL
, "usim_fck", &usim_fck
, CK_443X
),
3340 CLK(NULL
, "wd_timer2_fck", &wd_timer2_fck
, CK_443X
),
3341 CLK(NULL
, "wd_timer3_fck", &wd_timer3_fck
, CK_443X
),
3342 CLK(NULL
, "stm_clk_div_ck", &stm_clk_div_ck
, CK_443X
),
3343 CLK(NULL
, "trace_clk_div_ck", &trace_clk_div_ck
, CK_443X
),
3344 CLK(NULL
, "auxclk0_src_ck", &auxclk0_src_ck
, CK_443X
),
3345 CLK(NULL
, "auxclk0_ck", &auxclk0_ck
, CK_443X
),
3346 CLK(NULL
, "auxclkreq0_ck", &auxclkreq0_ck
, CK_443X
),
3347 CLK(NULL
, "auxclk1_src_ck", &auxclk1_src_ck
, CK_443X
),
3348 CLK(NULL
, "auxclk1_ck", &auxclk1_ck
, CK_443X
),
3349 CLK(NULL
, "auxclkreq1_ck", &auxclkreq1_ck
, CK_443X
),
3350 CLK(NULL
, "auxclk2_src_ck", &auxclk2_src_ck
, CK_443X
),
3351 CLK(NULL
, "auxclk2_ck", &auxclk2_ck
, CK_443X
),
3352 CLK(NULL
, "auxclkreq2_ck", &auxclkreq2_ck
, CK_443X
),
3353 CLK(NULL
, "auxclk3_src_ck", &auxclk3_src_ck
, CK_443X
),
3354 CLK(NULL
, "auxclk3_ck", &auxclk3_ck
, CK_443X
),
3355 CLK(NULL
, "auxclkreq3_ck", &auxclkreq3_ck
, CK_443X
),
3356 CLK(NULL
, "auxclk4_src_ck", &auxclk4_src_ck
, CK_443X
),
3357 CLK(NULL
, "auxclk4_ck", &auxclk4_ck
, CK_443X
),
3358 CLK(NULL
, "auxclkreq4_ck", &auxclkreq4_ck
, CK_443X
),
3359 CLK(NULL
, "auxclk5_src_ck", &auxclk5_src_ck
, CK_443X
),
3360 CLK(NULL
, "auxclk5_ck", &auxclk5_ck
, CK_443X
),
3361 CLK(NULL
, "auxclkreq5_ck", &auxclkreq5_ck
, CK_443X
),
3362 CLK(NULL
, "gpmc_ck", &dummy_ck
, CK_443X
),
3363 CLK("omap_i2c.1", "ick", &dummy_ck
, CK_443X
),
3364 CLK("omap_i2c.2", "ick", &dummy_ck
, CK_443X
),
3365 CLK("omap_i2c.3", "ick", &dummy_ck
, CK_443X
),
3366 CLK("omap_i2c.4", "ick", &dummy_ck
, CK_443X
),
3367 CLK(NULL
, "mailboxes_ick", &dummy_ck
, CK_443X
),
3368 CLK("omap_hsmmc.0", "ick", &dummy_ck
, CK_443X
),
3369 CLK("omap_hsmmc.1", "ick", &dummy_ck
, CK_443X
),
3370 CLK("omap_hsmmc.2", "ick", &dummy_ck
, CK_443X
),
3371 CLK("omap_hsmmc.3", "ick", &dummy_ck
, CK_443X
),
3372 CLK("omap_hsmmc.4", "ick", &dummy_ck
, CK_443X
),
3373 CLK("omap-mcbsp.1", "ick", &dummy_ck
, CK_443X
),
3374 CLK("omap-mcbsp.2", "ick", &dummy_ck
, CK_443X
),
3375 CLK("omap-mcbsp.3", "ick", &dummy_ck
, CK_443X
),
3376 CLK("omap-mcbsp.4", "ick", &dummy_ck
, CK_443X
),
3377 CLK("omap2_mcspi.1", "ick", &dummy_ck
, CK_443X
),
3378 CLK("omap2_mcspi.2", "ick", &dummy_ck
, CK_443X
),
3379 CLK("omap2_mcspi.3", "ick", &dummy_ck
, CK_443X
),
3380 CLK("omap2_mcspi.4", "ick", &dummy_ck
, CK_443X
),
3381 CLK(NULL
, "uart1_ick", &dummy_ck
, CK_443X
),
3382 CLK(NULL
, "uart2_ick", &dummy_ck
, CK_443X
),
3383 CLK(NULL
, "uart3_ick", &dummy_ck
, CK_443X
),
3384 CLK(NULL
, "uart4_ick", &dummy_ck
, CK_443X
),
3385 CLK("usbhs_omap", "usbhost_ick", &dummy_ck
, CK_443X
),
3386 CLK("usbhs_omap", "usbtll_fck", &dummy_ck
, CK_443X
),
3387 CLK("omap_wdt", "ick", &dummy_ck
, CK_443X
),
3388 CLK("omap_timer.1", "32k_ck", &sys_32k_ck
, CK_443X
),
3389 CLK("omap_timer.2", "32k_ck", &sys_32k_ck
, CK_443X
),
3390 CLK("omap_timer.3", "32k_ck", &sys_32k_ck
, CK_443X
),
3391 CLK("omap_timer.4", "32k_ck", &sys_32k_ck
, CK_443X
),
3392 CLK("omap_timer.5", "32k_ck", &sys_32k_ck
, CK_443X
),
3393 CLK("omap_timer.6", "32k_ck", &sys_32k_ck
, CK_443X
),
3394 CLK("omap_timer.7", "32k_ck", &sys_32k_ck
, CK_443X
),
3395 CLK("omap_timer.8", "32k_ck", &sys_32k_ck
, CK_443X
),
3396 CLK("omap_timer.9", "32k_ck", &sys_32k_ck
, CK_443X
),
3397 CLK("omap_timer.10", "32k_ck", &sys_32k_ck
, CK_443X
),
3398 CLK("omap_timer.11", "32k_ck", &sys_32k_ck
, CK_443X
),
3399 CLK("omap_timer.1", "sys_ck", &sys_clkin_ck
, CK_443X
),
3400 CLK("omap_timer.2", "sys_ck", &sys_clkin_ck
, CK_443X
),
3401 CLK("omap_timer.3", "sys_ck", &sys_clkin_ck
, CK_443X
),
3402 CLK("omap_timer.4", "sys_ck", &sys_clkin_ck
, CK_443X
),
3403 CLK("omap_timer.9", "sys_ck", &sys_clkin_ck
, CK_443X
),
3404 CLK("omap_timer.10", "sys_ck", &sys_clkin_ck
, CK_443X
),
3405 CLK("omap_timer.11", "sys_ck", &sys_clkin_ck
, CK_443X
),
3406 CLK("omap_timer.5", "sys_ck", &syc_clk_div_ck
, CK_443X
),
3407 CLK("omap_timer.6", "sys_ck", &syc_clk_div_ck
, CK_443X
),
3408 CLK("omap_timer.7", "sys_ck", &syc_clk_div_ck
, CK_443X
),
3409 CLK("omap_timer.8", "sys_ck", &syc_clk_div_ck
, CK_443X
),
3412 int __init
omap4xxx_clk_init(void)
3417 if (cpu_is_omap443x()) {
3418 cpu_mask
= RATE_IN_4430
;
3419 cpu_clkflg
= CK_443X
;
3420 } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
3421 cpu_mask
= RATE_IN_4460
| RATE_IN_4430
;
3422 cpu_clkflg
= CK_446X
| CK_443X
;
3424 if (cpu_is_omap447x())
3425 pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
3430 clk_init(&omap2_clk_functions
);
3433 * Must stay commented until all OMAP SoC drivers are
3434 * converted to runtime PM, or drivers may start crashing
3436 * omap2_clk_disable_clkdm_control();
3439 for (c
= omap44xx_clks
; c
< omap44xx_clks
+ ARRAY_SIZE(omap44xx_clks
);
3441 clk_preinit(c
->lk
.clk
);
3443 for (c
= omap44xx_clks
; c
< omap44xx_clks
+ ARRAY_SIZE(omap44xx_clks
);
3445 if (c
->cpu
& cpu_clkflg
) {
3447 clk_register(c
->lk
.clk
);
3448 omap2_init_clk_clkdm(c
->lk
.clk
);
3451 /* Disable autoidle on all clocks; let the PM code enable it later */
3452 omap_clk_disable_autoidle_all();
3454 recalculate_root_clocks();
3457 * Only enable those clocks we will need, let the drivers
3458 * enable other clocks as necessary
3460 clk_enable_init_clocks();