arch/arm/mach-omap2/clockdomains44xx_data.c

   1 /*
   2  * OMAP4 Clock domains framework
   3  *
   4  * Copyright (C) 2009 Texas Instruments, Inc.
   5  * Copyright (C) 2009 Nokia Corporation
   6  *
   7  * Abhijit Pagare (abhijitpagare@ti.com)
   8  * Benoit Cousson (b-cousson@ti.com)
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 /*
  22  * To-Do List
  23  * -> Populate the Sleep/Wakeup dependencies for the domains
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/io.h>
  28
  29 #include "clockdomain.h"
  30 #include "cm1_44xx.h"
  31 #include "cm2_44xx.h"
  32
  33 #include "cm1_44xx.h"
  34 #include "cm2_44xx.h"
  35 #include "cm-regbits-44xx.h"
  36 #include "prm44xx.h"
  37 #include "prcm44xx.h"
  38 #include "prcm_mpu44xx.h"
  39
  40
  41 static struct clockdomain l4_cefuse_44xx_clkdm = {
  42         .name             = "l4_cefuse_clkdm",
  43         .pwrdm            = { .name = "cefuse_pwrdm" },
  44         .prcm_partition   = OMAP4430_CM2_PARTITION,
  45         .cm_inst          = OMAP4430_CM2_CEFUSE_INST,
  46         .clkdm_offs       = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
  47         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
  48         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  49 };
  50
  51 static struct clockdomain l4_cfg_44xx_clkdm = {
  52         .name             = "l4_cfg_clkdm",
  53         .pwrdm            = { .name = "core_pwrdm" },
  54         .prcm_partition   = OMAP4430_CM2_PARTITION,
  55         .cm_inst          = OMAP4430_CM2_CORE_INST,
  56         .clkdm_offs       = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
  57         .flags            = CLKDM_CAN_HWSUP,
  58         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  59 };
  60
  61 static struct clockdomain tesla_44xx_clkdm = {
  62         .name             = "tesla_clkdm",
  63         .pwrdm            = { .name = "tesla_pwrdm" },
  64         .prcm_partition   = OMAP4430_CM1_PARTITION,
  65         .cm_inst          = OMAP4430_CM1_TESLA_INST,
  66         .clkdm_offs       = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
  67         .flags            = CLKDM_CAN_HWSUP_SWSUP,
  68         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  69 };
  70
  71 static struct clockdomain l3_gfx_44xx_clkdm = {
  72         .name             = "l3_gfx_clkdm",
  73         .pwrdm            = { .name = "gfx_pwrdm" },
  74         .prcm_partition   = OMAP4430_CM2_PARTITION,
  75         .cm_inst          = OMAP4430_CM2_GFX_INST,
  76         .clkdm_offs       = OMAP4430_CM2_GFX_GFX_CDOFFS,
  77         .flags            = CLKDM_CAN_HWSUP_SWSUP,
  78         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  79 };
  80
  81 static struct clockdomain ivahd_44xx_clkdm = {
  82         .name             = "ivahd_clkdm",
  83         .pwrdm            = { .name = "ivahd_pwrdm" },
  84         .prcm_partition   = OMAP4430_CM2_PARTITION,
  85         .cm_inst          = OMAP4430_CM2_IVAHD_INST,
  86         .clkdm_offs       = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS,
  87         .flags            = CLKDM_CAN_HWSUP_SWSUP,
  88         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  89 };
  90
  91 static struct clockdomain l4_secure_44xx_clkdm = {
  92         .name             = "l4_secure_clkdm",
  93         .pwrdm            = { .name = "l4per_pwrdm" },
  94         .prcm_partition   = OMAP4430_CM2_PARTITION,
  95         .cm_inst          = OMAP4430_CM2_L4PER_INST,
  96         .clkdm_offs       = OMAP4430_CM2_L4PER_L4SEC_CDOFFS,
  97         .flags            = CLKDM_CAN_HWSUP_SWSUP,
  98         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  99 };
 100
 101 static struct clockdomain l4_per_44xx_clkdm = {
 102         .name             = "l4_per_clkdm",
 103         .pwrdm            = { .name = "l4per_pwrdm" },
 104         .prcm_partition   = OMAP4430_CM2_PARTITION,
 105         .cm_inst          = OMAP4430_CM2_L4PER_INST,
 106         .clkdm_offs       = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
 107         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 108         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 109 };
 110
 111 static struct clockdomain abe_44xx_clkdm = {
 112         .name             = "abe_clkdm",
 113         .pwrdm            = { .name = "abe_pwrdm" },
 114         .prcm_partition   = OMAP4430_CM1_PARTITION,
 115         .cm_inst          = OMAP4430_CM1_ABE_INST,
 116         .clkdm_offs       = OMAP4430_CM1_ABE_ABE_CDOFFS,
 117         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 118         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 119 };
 120
 121 static struct clockdomain l3_instr_44xx_clkdm = {
 122         .name             = "l3_instr_clkdm",
 123         .pwrdm            = { .name = "core_pwrdm" },
 124         .prcm_partition   = OMAP4430_CM2_PARTITION,
 125         .cm_inst          = OMAP4430_CM2_CORE_INST,
 126         .clkdm_offs       = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
 127         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 128 };
 129
 130 static struct clockdomain l3_init_44xx_clkdm = {
 131         .name             = "l3_init_clkdm",
 132         .pwrdm            = { .name = "l3init_pwrdm" },
 133         .prcm_partition   = OMAP4430_CM2_PARTITION,
 134         .cm_inst          = OMAP4430_CM2_L3INIT_INST,
 135         .clkdm_offs       = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS,
 136         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 137         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 138 };
 139
 140 static struct clockdomain mpuss_44xx_clkdm = {
 141         .name             = "mpuss_clkdm",
 142         .pwrdm            = { .name = "mpu_pwrdm" },
 143         .prcm_partition   = OMAP4430_CM1_PARTITION,
 144         .cm_inst          = OMAP4430_CM1_MPU_INST,
 145         .clkdm_offs       = OMAP4430_CM1_MPU_MPU_CDOFFS,
 146         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 147         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 148 };
 149
 150 static struct clockdomain mpu0_44xx_clkdm = {
 151         .name             = "mpu0_clkdm",
 152         .pwrdm            = { .name = "cpu0_pwrdm" },
 153         .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
 154         .cm_inst          = OMAP4430_PRCM_MPU_CPU0_INST,
 155         .clkdm_offs       = OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS,
 156         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 157         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 158 };
 159
 160 static struct clockdomain mpu1_44xx_clkdm = {
 161         .name             = "mpu1_clkdm",
 162         .pwrdm            = { .name = "cpu1_pwrdm" },
 163         .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
 164         .cm_inst          = OMAP4430_PRCM_MPU_CPU1_INST,
 165         .clkdm_offs       = OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS,
 166         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 167         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 168 };
 169
 170 static struct clockdomain l3_emif_44xx_clkdm = {
 171         .name             = "l3_emif_clkdm",
 172         .pwrdm            = { .name = "core_pwrdm" },
 173         .prcm_partition   = OMAP4430_CM2_PARTITION,
 174         .cm_inst          = OMAP4430_CM2_CORE_INST,
 175         .clkdm_offs       = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
 176         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 177         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 178 };
 179
 180 static struct clockdomain l4_ao_44xx_clkdm = {
 181         .name             = "l4_ao_clkdm",
 182         .pwrdm            = { .name = "always_on_core_pwrdm" },
 183         .prcm_partition   = OMAP4430_CM2_PARTITION,
 184         .cm_inst          = OMAP4430_CM2_ALWAYS_ON_INST,
 185         .clkdm_offs       = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
 186         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 187         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 188 };
 189
 190 static struct clockdomain ducati_44xx_clkdm = {
 191         .name             = "ducati_clkdm",
 192         .pwrdm            = { .name = "core_pwrdm" },
 193         .prcm_partition   = OMAP4430_CM2_PARTITION,
 194         .cm_inst          = OMAP4430_CM2_CORE_INST,
 195         .clkdm_offs       = OMAP4430_CM2_CORE_DUCATI_CDOFFS,
 196         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 197         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 198 };
 199
 200 static struct clockdomain l3_2_44xx_clkdm = {
 201         .name             = "l3_2_clkdm",
 202         .pwrdm            = { .name = "core_pwrdm" },
 203         .prcm_partition   = OMAP4430_CM2_PARTITION,
 204         .cm_inst          = OMAP4430_CM2_CORE_INST,
 205         .clkdm_offs       = OMAP4430_CM2_CORE_L3_2_CDOFFS,
 206         .flags            = CLKDM_CAN_HWSUP,
 207         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 208 };
 209
 210 static struct clockdomain l3_1_44xx_clkdm = {
 211         .name             = "l3_1_clkdm",
 212         .pwrdm            = { .name = "core_pwrdm" },
 213         .prcm_partition   = OMAP4430_CM2_PARTITION,
 214         .cm_inst          = OMAP4430_CM2_CORE_INST,
 215         .clkdm_offs       = OMAP4430_CM2_CORE_L3_1_CDOFFS,
 216         .flags            = CLKDM_CAN_HWSUP,
 217         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 218 };
 219
 220 static struct clockdomain l3_d2d_44xx_clkdm = {
 221         .name             = "l3_d2d_clkdm",
 222         .pwrdm            = { .name = "core_pwrdm" },
 223         .prcm_partition   = OMAP4430_CM2_PARTITION,
 224         .cm_inst          = OMAP4430_CM2_CORE_INST,
 225         .clkdm_offs       = OMAP4430_CM2_CORE_D2D_CDOFFS,
 226         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 227         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 228 };
 229
 230 static struct clockdomain iss_44xx_clkdm = {
 231         .name             = "iss_clkdm",
 232         .pwrdm            = { .name = "cam_pwrdm" },
 233         .prcm_partition   = OMAP4430_CM2_PARTITION,
 234         .cm_inst          = OMAP4430_CM2_CAM_INST,
 235         .clkdm_offs       = OMAP4430_CM2_CAM_CAM_CDOFFS,
 236         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 237         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 238 };
 239
 240 static struct clockdomain l3_dss_44xx_clkdm = {
 241         .name             = "l3_dss_clkdm",
 242         .pwrdm            = { .name = "dss_pwrdm" },
 243         .prcm_partition   = OMAP4430_CM2_PARTITION,
 244         .cm_inst          = OMAP4430_CM2_DSS_INST,
 245         .clkdm_offs       = OMAP4430_CM2_DSS_DSS_CDOFFS,
 246         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 247         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 248 };
 249
 250 static struct clockdomain l4_wkup_44xx_clkdm = {
 251         .name             = "l4_wkup_clkdm",
 252         .pwrdm            = { .name = "wkup_pwrdm" },
 253         .prcm_partition   = OMAP4430_PRM_PARTITION,
 254         .cm_inst          = OMAP4430_PRM_WKUP_CM_INST,
 255         .clkdm_offs       = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
 256         .flags            = CLKDM_CAN_HWSUP,
 257         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 258 };
 259
 260 static struct clockdomain emu_sys_44xx_clkdm = {
 261         .name             = "emu_sys_clkdm",
 262         .pwrdm            = { .name = "emu_pwrdm" },
 263         .prcm_partition   = OMAP4430_PRM_PARTITION,
 264         .cm_inst          = OMAP4430_PRM_EMU_CM_INST,
 265         .clkdm_offs       = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
 266         .flags            = CLKDM_CAN_HWSUP,
 267         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 268 };
 269
 270 static struct clockdomain l3_dma_44xx_clkdm = {
 271         .name             = "l3_dma_clkdm",
 272         .pwrdm            = { .name = "core_pwrdm" },
 273         .prcm_partition   = OMAP4430_CM2_PARTITION,
 274         .cm_inst          = OMAP4430_CM2_CORE_INST,
 275         .clkdm_offs       = OMAP4430_CM2_CORE_SDMA_CDOFFS,
 276         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 277         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 278 };
 279
 280 static struct clockdomain *clockdomains_omap44xx[] __initdata = {
 281         &l4_cefuse_44xx_clkdm,
 282         &l4_cfg_44xx_clkdm,
 283         &tesla_44xx_clkdm,
 284         &l3_gfx_44xx_clkdm,
 285         &ivahd_44xx_clkdm,
 286         &l4_secure_44xx_clkdm,
 287         &l4_per_44xx_clkdm,
 288         &abe_44xx_clkdm,
 289         &l3_instr_44xx_clkdm,
 290         &l3_init_44xx_clkdm,
 291         &mpuss_44xx_clkdm,
 292         &mpu0_44xx_clkdm,
 293         &mpu1_44xx_clkdm,
 294         &l3_emif_44xx_clkdm,
 295         &l4_ao_44xx_clkdm,
 296         &ducati_44xx_clkdm,
 297         &l3_2_44xx_clkdm,
 298         &l3_1_44xx_clkdm,
 299         &l3_d2d_44xx_clkdm,
 300         &iss_44xx_clkdm,
 301         &l3_dss_44xx_clkdm,
 302         &l4_wkup_44xx_clkdm,
 303         &emu_sys_44xx_clkdm,
 304         &l3_dma_44xx_clkdm,
 305         NULL,
 306 };
 307
 308 void __init omap44xx_clockdomains_init(void)
 309 {
 310         clkdm_init(clockdomains_omap44xx, NULL);
 311 }