arch/arm/mach-omap2/cm2xxx.c

   1 /*
   2  * OMAP2xxx CM module functions
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  * Rajendra Nayak <rnayak@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/types.h>
  16 #include <linux/delay.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/io.h>
  20
  21 #include "soc.h"
  22 #include "iomap.h"
  23 #include "common.h"
  24 #include "prm2xxx.h"
  25 #include "cm.h"
  26 #include "cm2xxx.h"
  27 #include "cm-regbits-24xx.h"
  28 #include "clockdomain.h"
  29
  30 /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
  31 #define DPLL_AUTOIDLE_DISABLE                           0x0
  32 #define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP           0x3
  33
  34 /* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
  35 #define OMAP2XXX_APLL_AUTOIDLE_DISABLE                  0x0
  36 #define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP           0x3
  37
  38 static const u8 omap2xxx_cm_idlest_offs[] = {
  39         CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
  40 };
  41
  42 /*
  43  *
  44  */
  45
  46 static void _write_clktrctrl(u8 c, s16 module, u32 mask)
  47 {
  48         u32 v;
  49
  50         v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
  51         v &= ~mask;
  52         v |= c << __ffs(mask);
  53         omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
  54 }
  55
  56 bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
  57 {
  58         u32 v;
  59
  60         v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
  61         v &= mask;
  62         v >>= __ffs(mask);
  63
  64         return (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
  65 }
  66
  67 void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
  68 {
  69         _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
  70 }
  71
  72 void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
  73 {
  74         _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
  75 }
  76
  77 /*
  78  * DPLL autoidle control
  79  */
  80
  81 static void _omap2xxx_set_dpll_autoidle(u8 m)
  82 {
  83         u32 v;
  84
  85         v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
  86         v &= ~OMAP24XX_AUTO_DPLL_MASK;
  87         v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
  88         omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
  89 }
  90
  91 void omap2xxx_cm_set_dpll_disable_autoidle(void)
  92 {
  93         _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
  94 }
  95
  96 void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
  97 {
  98         _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
  99 }
 100
 101 /*
 102  * APLL autoidle control
 103  */
 104
 105 static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
 106 {
 107         u32 v;
 108
 109         v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
 110         v &= ~mask;
 111         v |= m << __ffs(mask);
 112         omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
 113 }
 114
 115 void omap2xxx_cm_set_apll54_disable_autoidle(void)
 116 {
 117         _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
 118                                     OMAP24XX_AUTO_54M_MASK);
 119 }
 120
 121 void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
 122 {
 123         _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
 124                                     OMAP24XX_AUTO_54M_MASK);
 125 }
 126
 127 void omap2xxx_cm_set_apll96_disable_autoidle(void)
 128 {
 129         _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
 130                                     OMAP24XX_AUTO_96M_MASK);
 131 }
 132
 133 void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
 134 {
 135         _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
 136                                     OMAP24XX_AUTO_96M_MASK);
 137 }
 138
 139 /*
 140  *
 141  */
 142
 143 /**
 144  * omap2xxx_cm_wait_module_ready - wait for a module to leave idle or standby
 145  * @prcm_mod: PRCM module offset
 146  * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
 147  * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
 148  *
 149  * Wait for the PRCM to indicate that the module identified by
 150  * (@prcm_mod, @idlest_id, @idlest_shift) is clocked.  Return 0 upon
 151  * success or -EBUSY if the module doesn't enable in time.
 152  */
 153 int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
 154 {
 155         int ena = 0, i = 0;
 156         u8 cm_idlest_reg;
 157         u32 mask;
 158
 159         if (!idlest_id || (idlest_id > ARRAY_SIZE(omap2xxx_cm_idlest_offs)))
 160                 return -EINVAL;
 161
 162         cm_idlest_reg = omap2xxx_cm_idlest_offs[idlest_id - 1];
 163
 164         mask = 1 << idlest_shift;
 165         ena = mask;
 166
 167         omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
 168                             mask) == ena), MAX_MODULE_READY_TIME, i);
 169
 170         return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
 171 }
 172
 173 /* Clockdomain low-level functions */
 174
 175 static void omap2xxx_clkdm_allow_idle(struct clockdomain *clkdm)
 176 {
 177         if (atomic_read(&clkdm->usecount) > 0)
 178                 _clkdm_add_autodeps(clkdm);
 179
 180         omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 181                                        clkdm->clktrctrl_mask);
 182 }
 183
 184 static void omap2xxx_clkdm_deny_idle(struct clockdomain *clkdm)
 185 {
 186         omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 187                                         clkdm->clktrctrl_mask);
 188
 189         if (atomic_read(&clkdm->usecount) > 0)
 190                 _clkdm_del_autodeps(clkdm);
 191 }
 192
 193 static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
 194 {
 195         bool hwsup = false;
 196
 197         if (!clkdm->clktrctrl_mask)
 198                 return 0;
 199
 200         hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 201                                               clkdm->clktrctrl_mask);
 202
 203         if (hwsup) {
 204                 /* Disable HW transitions when we are changing deps */
 205                 omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 206                                                 clkdm->clktrctrl_mask);
 207                 _clkdm_add_autodeps(clkdm);
 208                 omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 209                                                clkdm->clktrctrl_mask);
 210         } else {
 211                 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
 212                         omap2xxx_clkdm_wakeup(clkdm);
 213         }
 214
 215         return 0;
 216 }
 217
 218 static int omap2xxx_clkdm_clk_disable(struct clockdomain *clkdm)
 219 {
 220         bool hwsup = false;
 221
 222         if (!clkdm->clktrctrl_mask)
 223                 return 0;
 224
 225         hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 226                                               clkdm->clktrctrl_mask);
 227
 228         if (hwsup) {
 229                 /* Disable HW transitions when we are changing deps */
 230                 omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 231                                                 clkdm->clktrctrl_mask);
 232                 _clkdm_del_autodeps(clkdm);
 233                 omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 234                                                clkdm->clktrctrl_mask);
 235         } else {
 236                 if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
 237                         omap2xxx_clkdm_sleep(clkdm);
 238         }
 239
 240         return 0;
 241 }
 242
 243 struct clkdm_ops omap2_clkdm_operations = {
 244         .clkdm_add_wkdep        = omap2_clkdm_add_wkdep,
 245         .clkdm_del_wkdep        = omap2_clkdm_del_wkdep,
 246         .clkdm_read_wkdep       = omap2_clkdm_read_wkdep,
 247         .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
 248         .clkdm_sleep            = omap2xxx_clkdm_sleep,
 249         .clkdm_wakeup           = omap2xxx_clkdm_wakeup,
 250         .clkdm_allow_idle       = omap2xxx_clkdm_allow_idle,
 251         .clkdm_deny_idle        = omap2xxx_clkdm_deny_idle,
 252         .clkdm_clk_enable       = omap2xxx_clkdm_clk_enable,
 253         .clkdm_clk_disable      = omap2xxx_clkdm_clk_disable,
 254 };
 255