arch/arm/mach-omap2/control.c

   1 /*
   2  * OMAP2/3 System Control Module register access
   3  *
   4  * Copyright (C) 2007, 2012 Texas Instruments, Inc.
   5  * Copyright (C) 2007 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #undef DEBUG
  14
  15 #include <linux/kernel.h>
  16 #include <linux/io.h>
  17
  18 #include "soc.h"
  19 #include "iomap.h"
  20 #include "common.h"
  21 #include "cm-regbits-34xx.h"
  22 #include "prm-regbits-34xx.h"
  23 #include "prm3xxx.h"
  24 #include "cm3xxx.h"
  25 #include "sdrc.h"
  26 #include "pm.h"
  27 #include "control.h"
  28
  29 /* Used by omap3_ctrl_save_padconf() */
  30 #define START_PADCONF_SAVE              0x2
  31 #define PADCONF_SAVE_DONE               0x1
  32
  33 static void __iomem *omap2_ctrl_base;
  34 static void __iomem *omap4_ctrl_pad_base;
  35
  36 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  37 struct omap3_scratchpad {
  38         u32 boot_config_ptr;
  39         u32 public_restore_ptr;
  40         u32 secure_ram_restore_ptr;
  41         u32 sdrc_module_semaphore;
  42         u32 prcm_block_offset;
  43         u32 sdrc_block_offset;
  44 };
  45
  46 struct omap3_scratchpad_prcm_block {
  47         u32 prm_clksrc_ctrl;
  48         u32 prm_clksel;
  49         u32 cm_contents[11];
  50         u32 prcm_block_size;
  51 };
  52
  53 struct omap3_scratchpad_sdrc_block {
  54         u16 sysconfig;
  55         u16 cs_cfg;
  56         u16 sharing;
  57         u16 err_type;
  58         u32 dll_a_ctrl;
  59         u32 dll_b_ctrl;
  60         u32 power;
  61         u32 cs_0;
  62         u32 mcfg_0;
  63         u16 mr_0;
  64         u16 emr_1_0;
  65         u16 emr_2_0;
  66         u16 emr_3_0;
  67         u32 actim_ctrla_0;
  68         u32 actim_ctrlb_0;
  69         u32 rfr_ctrl_0;
  70         u32 cs_1;
  71         u32 mcfg_1;
  72         u16 mr_1;
  73         u16 emr_1_1;
  74         u16 emr_2_1;
  75         u16 emr_3_1;
  76         u32 actim_ctrla_1;
  77         u32 actim_ctrlb_1;
  78         u32 rfr_ctrl_1;
  79         u16 dcdl_1_ctrl;
  80         u16 dcdl_2_ctrl;
  81         u32 flags;
  82         u32 block_size;
  83 };
  84
  85 void *omap3_secure_ram_storage;
  86
  87 /*
  88  * This is used to store ARM registers in SDRAM before attempting
  89  * an MPU OFF. The save and restore happens from the SRAM sleep code.
  90  * The address is stored in scratchpad, so that it can be used
  91  * during the restore path.
  92  */
  93 u32 omap3_arm_context[128];
  94
  95 struct omap3_control_regs {
  96         u32 sysconfig;
  97         u32 devconf0;
  98         u32 mem_dftrw0;
  99         u32 mem_dftrw1;
 100         u32 msuspendmux_0;
 101         u32 msuspendmux_1;
 102         u32 msuspendmux_2;
 103         u32 msuspendmux_3;
 104         u32 msuspendmux_4;
 105         u32 msuspendmux_5;
 106         u32 sec_ctrl;
 107         u32 devconf1;
 108         u32 csirxfe;
 109         u32 iva2_bootaddr;
 110         u32 iva2_bootmod;
 111         u32 debobs_0;
 112         u32 debobs_1;
 113         u32 debobs_2;
 114         u32 debobs_3;
 115         u32 debobs_4;
 116         u32 debobs_5;
 117         u32 debobs_6;
 118         u32 debobs_7;
 119         u32 debobs_8;
 120         u32 prog_io0;
 121         u32 prog_io1;
 122         u32 dss_dpll_spreading;
 123         u32 core_dpll_spreading;
 124         u32 per_dpll_spreading;
 125         u32 usbhost_dpll_spreading;
 126         u32 pbias_lite;
 127         u32 temp_sensor;
 128         u32 sramldo4;
 129         u32 sramldo5;
 130         u32 csi;
 131         u32 padconf_sys_nirq;
 132 };
 133
 134 static struct omap3_control_regs control_context;
 135 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
 136
 137 #define OMAP_CTRL_REGADDR(reg)          (omap2_ctrl_base + (reg))
 138 #define OMAP4_CTRL_PAD_REGADDR(reg)     (omap4_ctrl_pad_base + (reg))
 139
 140 void __init omap2_set_globals_control(void __iomem *ctrl,
 141                                       void __iomem *ctrl_pad)
 142 {
 143         omap2_ctrl_base = ctrl;
 144         omap4_ctrl_pad_base = ctrl_pad;
 145 }
 146
 147 void __iomem *omap_ctrl_base_get(void)
 148 {
 149         return omap2_ctrl_base;
 150 }
 151
 152 u8 omap_ctrl_readb(u16 offset)
 153 {
 154         return readb_relaxed(OMAP_CTRL_REGADDR(offset));
 155 }
 156
 157 u16 omap_ctrl_readw(u16 offset)
 158 {
 159         return readw_relaxed(OMAP_CTRL_REGADDR(offset));
 160 }
 161
 162 u32 omap_ctrl_readl(u16 offset)
 163 {
 164         return readl_relaxed(OMAP_CTRL_REGADDR(offset));
 165 }
 166
 167 void omap_ctrl_writeb(u8 val, u16 offset)
 168 {
 169         writeb_relaxed(val, OMAP_CTRL_REGADDR(offset));
 170 }
 171
 172 void omap_ctrl_writew(u16 val, u16 offset)
 173 {
 174         writew_relaxed(val, OMAP_CTRL_REGADDR(offset));
 175 }
 176
 177 void omap_ctrl_writel(u32 val, u16 offset)
 178 {
 179         writel_relaxed(val, OMAP_CTRL_REGADDR(offset));
 180 }
 181
 182 /*
 183  * On OMAP4 control pad are not addressable from control
 184  * core base. So the common omap_ctrl_read/write APIs breaks
 185  * Hence export separate APIs to manage the omap4 pad control
 186  * registers. This APIs will work only for OMAP4
 187  */
 188
 189 u32 omap4_ctrl_pad_readl(u16 offset)
 190 {
 191         return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset));
 192 }
 193
 194 void omap4_ctrl_pad_writel(u32 val, u16 offset)
 195 {
 196         writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset));
 197 }
 198
 199 #ifdef CONFIG_ARCH_OMAP3
 200
 201 /**
 202  * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
 203  * @bootmode: 8-bit value to pass to some boot code
 204  *
 205  * Set the bootmode in the scratchpad RAM.  This is used after the
 206  * system restarts.  Not sure what actually uses this - it may be the
 207  * bootloader, rather than the boot ROM - contrary to the preserved
 208  * comment below.  No return value.
 209  */
 210 void omap3_ctrl_write_boot_mode(u8 bootmode)
 211 {
 212         u32 l;
 213
 214         l = ('B' << 24) | ('M' << 16) | bootmode;
 215
 216         /*
 217          * Reserve the first word in scratchpad for communicating
 218          * with the boot ROM. A pointer to a data structure
 219          * describing the boot process can be stored there,
 220          * cf. OMAP34xx TRM, Initialization / Software Booting
 221          * Configuration.
 222          *
 223          * XXX This should use some omap_ctrl_writel()-type function
 224          */
 225         writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
 226 }
 227
 228 #endif
 229
 230 /**
 231  * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
 232  * @bootaddr: physical address of the boot loader
 233  *
 234  * Set boot address for the boot loader of a supported processor
 235  * when a power ON sequence occurs.
 236  */
 237 void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
 238 {
 239         u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
 240                      cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
 241                      cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
 242                      soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
 243                      0;
 244
 245         if (!offset) {
 246                 pr_err("%s: unsupported omap type\n", __func__);
 247                 return;
 248         }
 249
 250         omap_ctrl_writel(bootaddr, offset);
 251 }
 252
 253 /**
 254  * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
 255  * @bootmode: 8-bit value to pass to some boot code
 256  *
 257  * Sets boot mode for the boot loader of a supported processor
 258  * when a power ON sequence occurs.
 259  */
 260 void omap_ctrl_write_dsp_boot_mode(u8 bootmode)
 261 {
 262         u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD :
 263                      cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD :
 264                      0;
 265
 266         if (!offset) {
 267                 pr_err("%s: unsupported omap type\n", __func__);
 268                 return;
 269         }
 270
 271         omap_ctrl_writel(bootmode, offset);
 272 }
 273
 274 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 275 /*
 276  * Clears the scratchpad contents in case of cold boot-
 277  * called during bootup
 278  */
 279 void omap3_clear_scratchpad_contents(void)
 280 {
 281         u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
 282         void __iomem *v_addr;
 283         u32 offset = 0;
 284         v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
 285         if (omap3xxx_prm_clear_global_cold_reset()) {
 286                 for ( ; offset <= max_offset; offset += 0x4)
 287                         writel_relaxed(0x0, (v_addr + offset));
 288         }
 289 }
 290
 291 /* Populate the scratchpad structure with restore structure */
 292 void omap3_save_scratchpad_contents(void)
 293 {
 294         void  __iomem *scratchpad_address;
 295         u32 arm_context_addr;
 296         struct omap3_scratchpad scratchpad_contents;
 297         struct omap3_scratchpad_prcm_block prcm_block_contents;
 298         struct omap3_scratchpad_sdrc_block sdrc_block_contents;
 299
 300         /*
 301          * Populate the Scratchpad contents
 302          *
 303          * The "get_*restore_pointer" functions are used to provide a
 304          * physical restore address where the ROM code jumps while waking
 305          * up from MPU OFF/OSWR state.
 306          * The restore pointer is stored into the scratchpad.
 307          */
 308         scratchpad_contents.boot_config_ptr = 0x0;
 309         if (cpu_is_omap3630())
 310                 scratchpad_contents.public_restore_ptr =
 311                         virt_to_phys(omap3_restore_3630);
 312         else if (omap_rev() != OMAP3430_REV_ES3_0 &&
 313                                         omap_rev() != OMAP3430_REV_ES3_1)
 314                 scratchpad_contents.public_restore_ptr =
 315                         virt_to_phys(omap3_restore);
 316         else
 317                 scratchpad_contents.public_restore_ptr =
 318                         virt_to_phys(omap3_restore_es3);
 319
 320         if (omap_type() == OMAP2_DEVICE_TYPE_GP)
 321                 scratchpad_contents.secure_ram_restore_ptr = 0x0;
 322         else
 323                 scratchpad_contents.secure_ram_restore_ptr =
 324                         (u32) __pa(omap3_secure_ram_storage);
 325         scratchpad_contents.sdrc_module_semaphore = 0x0;
 326         scratchpad_contents.prcm_block_offset = 0x2C;
 327         scratchpad_contents.sdrc_block_offset = 0x64;
 328
 329         /* Populate the PRCM block contents */
 330         prcm_block_contents.prm_clksrc_ctrl =
 331                 omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
 332                                        OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 333         prcm_block_contents.prm_clksel =
 334                 omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
 335                                        OMAP3_PRM_CLKSEL_OFFSET);
 336
 337         omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
 338
 339         prcm_block_contents.prcm_block_size = 0x0;
 340
 341         /* Populate the SDRC block contents */
 342         sdrc_block_contents.sysconfig =
 343                         (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
 344         sdrc_block_contents.cs_cfg =
 345                         (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
 346         sdrc_block_contents.sharing =
 347                         (sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
 348         sdrc_block_contents.err_type =
 349                         (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
 350         sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
 351         sdrc_block_contents.dll_b_ctrl = 0x0;
 352         /*
 353          * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
 354          * be programed to issue automatic self refresh on timeout
 355          * of AUTO_CNT = 1 prior to any transition to OFF mode.
 356          */
 357         if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
 358                         && (omap_rev() >= OMAP3430_REV_ES3_0))
 359                 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
 360                                 ~(SDRC_POWER_AUTOCOUNT_MASK|
 361                                 SDRC_POWER_CLKCTRL_MASK)) |
 362                                 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
 363                                 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
 364         else
 365                 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
 366
 367         sdrc_block_contents.cs_0 = 0x0;
 368         sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
 369         sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
 370         sdrc_block_contents.emr_1_0 = 0x0;
 371         sdrc_block_contents.emr_2_0 = 0x0;
 372         sdrc_block_contents.emr_3_0 = 0x0;
 373         sdrc_block_contents.actim_ctrla_0 =
 374                         sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
 375         sdrc_block_contents.actim_ctrlb_0 =
 376                         sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
 377         sdrc_block_contents.rfr_ctrl_0 =
 378                         sdrc_read_reg(SDRC_RFR_CTRL_0);
 379         sdrc_block_contents.cs_1 = 0x0;
 380         sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
 381         sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
 382         sdrc_block_contents.emr_1_1 = 0x0;
 383         sdrc_block_contents.emr_2_1 = 0x0;
 384         sdrc_block_contents.emr_3_1 = 0x0;
 385         sdrc_block_contents.actim_ctrla_1 =
 386                         sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
 387         sdrc_block_contents.actim_ctrlb_1 =
 388                         sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
 389         sdrc_block_contents.rfr_ctrl_1 =
 390                         sdrc_read_reg(SDRC_RFR_CTRL_1);
 391         sdrc_block_contents.dcdl_1_ctrl = 0x0;
 392         sdrc_block_contents.dcdl_2_ctrl = 0x0;
 393         sdrc_block_contents.flags = 0x0;
 394         sdrc_block_contents.block_size = 0x0;
 395
 396         arm_context_addr = virt_to_phys(omap3_arm_context);
 397
 398         /* Copy all the contents to the scratchpad location */
 399         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 400         memcpy_toio(scratchpad_address, &scratchpad_contents,
 401                  sizeof(scratchpad_contents));
 402         /* Scratchpad contents being 32 bits, a divide by 4 done here */
 403         memcpy_toio(scratchpad_address +
 404                 scratchpad_contents.prcm_block_offset,
 405                 &prcm_block_contents, sizeof(prcm_block_contents));
 406         memcpy_toio(scratchpad_address +
 407                 scratchpad_contents.sdrc_block_offset,
 408                 &sdrc_block_contents, sizeof(sdrc_block_contents));
 409         /*
 410          * Copies the address of the location in SDRAM where ARM
 411          * registers get saved during a MPU OFF transition.
 412          */
 413         memcpy_toio(scratchpad_address +
 414                 scratchpad_contents.sdrc_block_offset +
 415                 sizeof(sdrc_block_contents), &arm_context_addr, 4);
 416 }
 417
 418 void omap3_control_save_context(void)
 419 {
 420         control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
 421         control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
 422         control_context.mem_dftrw0 =
 423                         omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
 424         control_context.mem_dftrw1 =
 425                         omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
 426         control_context.msuspendmux_0 =
 427                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
 428         control_context.msuspendmux_1 =
 429                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
 430         control_context.msuspendmux_2 =
 431                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
 432         control_context.msuspendmux_3 =
 433                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
 434         control_context.msuspendmux_4 =
 435                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
 436         control_context.msuspendmux_5 =
 437                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
 438         control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
 439         control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
 440         control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
 441         control_context.iva2_bootaddr =
 442                         omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
 443         control_context.iva2_bootmod =
 444                         omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
 445         control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
 446         control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
 447         control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
 448         control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
 449         control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
 450         control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
 451         control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
 452         control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
 453         control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
 454         control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
 455         control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
 456         control_context.dss_dpll_spreading =
 457                         omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
 458         control_context.core_dpll_spreading =
 459                         omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
 460         control_context.per_dpll_spreading =
 461                         omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
 462         control_context.usbhost_dpll_spreading =
 463                 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
 464         control_context.pbias_lite =
 465                         omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
 466         control_context.temp_sensor =
 467                         omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
 468         control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
 469         control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
 470         control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
 471         control_context.padconf_sys_nirq =
 472                 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
 473         return;
 474 }
 475
 476 void omap3_control_restore_context(void)
 477 {
 478         omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
 479         omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
 480         omap_ctrl_writel(control_context.mem_dftrw0,
 481                                         OMAP343X_CONTROL_MEM_DFTRW0);
 482         omap_ctrl_writel(control_context.mem_dftrw1,
 483                                         OMAP343X_CONTROL_MEM_DFTRW1);
 484         omap_ctrl_writel(control_context.msuspendmux_0,
 485                                         OMAP2_CONTROL_MSUSPENDMUX_0);
 486         omap_ctrl_writel(control_context.msuspendmux_1,
 487                                         OMAP2_CONTROL_MSUSPENDMUX_1);
 488         omap_ctrl_writel(control_context.msuspendmux_2,
 489                                         OMAP2_CONTROL_MSUSPENDMUX_2);
 490         omap_ctrl_writel(control_context.msuspendmux_3,
 491                                         OMAP2_CONTROL_MSUSPENDMUX_3);
 492         omap_ctrl_writel(control_context.msuspendmux_4,
 493                                         OMAP2_CONTROL_MSUSPENDMUX_4);
 494         omap_ctrl_writel(control_context.msuspendmux_5,
 495                                         OMAP2_CONTROL_MSUSPENDMUX_5);
 496         omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
 497         omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
 498         omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
 499         omap_ctrl_writel(control_context.iva2_bootaddr,
 500                                         OMAP343X_CONTROL_IVA2_BOOTADDR);
 501         omap_ctrl_writel(control_context.iva2_bootmod,
 502                                         OMAP343X_CONTROL_IVA2_BOOTMOD);
 503         omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
 504         omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
 505         omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
 506         omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
 507         omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
 508         omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
 509         omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
 510         omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
 511         omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
 512         omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
 513         omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
 514         omap_ctrl_writel(control_context.dss_dpll_spreading,
 515                                         OMAP343X_CONTROL_DSS_DPLL_SPREADING);
 516         omap_ctrl_writel(control_context.core_dpll_spreading,
 517                                         OMAP343X_CONTROL_CORE_DPLL_SPREADING);
 518         omap_ctrl_writel(control_context.per_dpll_spreading,
 519                                         OMAP343X_CONTROL_PER_DPLL_SPREADING);
 520         omap_ctrl_writel(control_context.usbhost_dpll_spreading,
 521                                 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
 522         omap_ctrl_writel(control_context.pbias_lite,
 523                                         OMAP343X_CONTROL_PBIAS_LITE);
 524         omap_ctrl_writel(control_context.temp_sensor,
 525                                         OMAP343X_CONTROL_TEMP_SENSOR);
 526         omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
 527         omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
 528         omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
 529         omap_ctrl_writel(control_context.padconf_sys_nirq,
 530                          OMAP343X_CONTROL_PADCONF_SYSNIRQ);
 531         return;
 532 }
 533
 534 void omap3630_ctrl_disable_rta(void)
 535 {
 536         if (!cpu_is_omap3630())
 537                 return;
 538         omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
 539 }
 540
 541 /**
 542  * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM
 543  *
 544  * Tell the SCM to start saving the padconf registers, then wait for
 545  * the process to complete.  Returns 0 unconditionally, although it
 546  * should also eventually be able to return -ETIMEDOUT, if the save
 547  * does not complete.
 548  *
 549  * XXX This function is missing a timeout.  What should it be?
 550  */
 551 int omap3_ctrl_save_padconf(void)
 552 {
 553         u32 cpo;
 554
 555         /* Save the padconf registers */
 556         cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
 557         cpo |= START_PADCONF_SAVE;
 558         omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF);
 559
 560         /* wait for the save to complete */
 561         while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
 562                  & PADCONF_SAVE_DONE))
 563                 udelay(1);
 564
 565         return 0;
 566 }
 567
 568 /**
 569  * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle
 570  *
 571  * Sets the bootmode for IVA2 to idle. This is needed by the PM code to
 572  * force disable IVA2 so that it does not prevent any low-power states.
 573  */
 574 void omap3_ctrl_set_iva_bootmode_idle(void)
 575 {
 576         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 577                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 578 }
 579 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */