arch/arm/mach-omap2/cpuidle34xx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/cpuidle34xx.c
   3  *
   4  * OMAP3 CPU IDLE Routines
   5  *
   6  * Copyright (C) 2008 Texas Instruments, Inc.
   7  * Rajendra Nayak <rnayak@ti.com>
   8  *
   9  * Copyright (C) 2007 Texas Instruments, Inc.
  10  * Karthik Dasu <karthik-dp@ti.com>
  11  *
  12  * Copyright (C) 2006 Nokia Corporation
  13  * Tony Lindgren <tony@atomide.com>
  14  *
  15  * Copyright (C) 2005 Texas Instruments, Inc.
  16  * Richard Woodruff <r-woodruff2@ti.com>
  17  *
  18  * Based on pm.c for omap2
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License version 2 as
  22  * published by the Free Software Foundation.
  23  */
  24
  25 #include <linux/sched.h>
  26 #include <linux/cpuidle.h>
  27
  28 #include <plat/prcm.h>
  29 #include <plat/irqs.h>
  30 #include "powerdomain.h"
  31 #include "clockdomain.h"
  32 #include <plat/serial.h>
  33
  34 #include "pm.h"
  35 #include "control.h"
  36
  37 #ifdef CONFIG_CPU_IDLE
  38
  39 /*
  40  * The latencies/thresholds for various C states have
  41  * to be configured from the respective board files.
  42  * These are some default values (which might not provide
  43  * the best power savings) used on boards which do not
  44  * pass these details from the board file.
  45  */
  46 static struct cpuidle_params cpuidle_params_table[] = {
  47         /* C1 */
  48         {2 + 2, 5, 1},
  49         /* C2 */
  50         {10 + 10, 30, 1},
  51         /* C3 */
  52         {50 + 50, 300, 1},
  53         /* C4 */
  54         {1500 + 1800, 4000, 1},
  55         /* C5 */
  56         {2500 + 7500, 12000, 1},
  57         /* C6 */
  58         {3000 + 8500, 15000, 1},
  59         /* C7 */
  60         {10000 + 30000, 300000, 1},
  61 };
  62 #define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
  63
  64 /* Mach specific information to be recorded in the C-state driver_data */
  65 struct omap3_idle_statedata {
  66         u32 mpu_state;
  67         u32 core_state;
  68         u8 valid;
  69 };
  70 struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
  71
  72 struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
  73
  74 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
  75                                 struct clockdomain *clkdm)
  76 {
  77         clkdm_allow_idle(clkdm);
  78         return 0;
  79 }
  80
  81 static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
  82                                 struct clockdomain *clkdm)
  83 {
  84         clkdm_deny_idle(clkdm);
  85         return 0;
  86 }
  87
  88 /**
  89  * omap3_enter_idle - Programs OMAP3 to enter the specified state
  90  * @dev: cpuidle device
  91  * @drv: cpuidle driver
  92  * @index: the index of state to be entered
  93  *
  94  * Called from the CPUidle framework to program the device to the
  95  * specified target state selected by the governor.
  96  */
  97 static int omap3_enter_idle(struct cpuidle_device *dev,
  98                                 struct cpuidle_driver *drv,
  99                                 int index)
 100 {
 101         struct omap3_idle_statedata *cx =
 102                         cpuidle_get_statedata(&dev->states_usage[index]);
 103         struct timespec ts_preidle, ts_postidle, ts_idle;
 104         u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
 105         int idle_time;
 106
 107         /* Used to keep track of the total time in idle */
 108         getnstimeofday(&ts_preidle);
 109
 110         local_irq_disable();
 111         local_fiq_disable();
 112
 113         pwrdm_set_next_pwrst(mpu_pd, mpu_state);
 114         pwrdm_set_next_pwrst(core_pd, core_state);
 115
 116         if (omap_irq_pending() || need_resched())
 117                 goto return_sleep_time;
 118
 119         /* Deny idle for C1 */
 120         if (index == 0) {
 121                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
 122                 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
 123         }
 124
 125         /* Execute ARM wfi */
 126         omap_sram_idle();
 127
 128         /* Re-allow idle for C1 */
 129         if (index == 0) {
 130                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
 131                 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
 132         }
 133
 134 return_sleep_time:
 135         getnstimeofday(&ts_postidle);
 136         ts_idle = timespec_sub(ts_postidle, ts_preidle);
 137
 138         local_irq_enable();
 139         local_fiq_enable();
 140
 141         idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
 142                                                                 USEC_PER_SEC;
 143
 144         /* Update cpuidle counters */
 145         dev->last_residency = idle_time;
 146
 147         return index;
 148 }
 149
 150 /**
 151  * next_valid_state - Find next valid C-state
 152  * @dev: cpuidle device
 153  * @drv: cpuidle driver
 154  * @index: Index of currently selected c-state
 155  *
 156  * If the state corresponding to index is valid, index is returned back
 157  * to the caller. Else, this function searches for a lower c-state which is
 158  * still valid (as defined in omap3_power_states[]) and returns its index.
 159  *
 160  * A state is valid if the 'valid' field is enabled and
 161  * if it satisfies the enable_off_mode condition.
 162  */
 163 static int next_valid_state(struct cpuidle_device *dev,
 164                         struct cpuidle_driver *drv,
 165                                 int index)
 166 {
 167         struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
 168         struct cpuidle_state *curr = &drv->states[index];
 169         struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
 170         u32 mpu_deepest_state = PWRDM_POWER_RET;
 171         u32 core_deepest_state = PWRDM_POWER_RET;
 172         int next_index = -1;
 173
 174         if (enable_off_mode) {
 175                 mpu_deepest_state = PWRDM_POWER_OFF;
 176                 /*
 177                  * Erratum i583: valable for ES rev < Es1.2 on 3630.
 178                  * CORE OFF mode is not supported in a stable form, restrict
 179                  * instead the CORE state to RET.
 180                  */
 181                 if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
 182                         core_deepest_state = PWRDM_POWER_OFF;
 183         }
 184
 185         /* Check if current state is valid */
 186         if ((cx->valid) &&
 187             (cx->mpu_state >= mpu_deepest_state) &&
 188             (cx->core_state >= core_deepest_state)) {
 189                 return index;
 190         } else {
 191                 int idx = OMAP3_NUM_STATES - 1;
 192
 193                 /* Reach the current state starting at highest C-state */
 194                 for (; idx >= 0; idx--) {
 195                         if (&drv->states[idx] == curr) {
 196                                 next_index = idx;
 197                                 break;
 198                         }
 199                 }
 200
 201                 /* Should never hit this condition */
 202                 WARN_ON(next_index == -1);
 203
 204                 /*
 205                  * Drop to next valid state.
 206                  * Start search from the next (lower) state.
 207                  */
 208                 idx--;
 209                 for (; idx >= 0; idx--) {
 210                         cx = cpuidle_get_statedata(&dev->states_usage[idx]);
 211                         if ((cx->valid) &&
 212                             (cx->mpu_state >= mpu_deepest_state) &&
 213                             (cx->core_state >= core_deepest_state)) {
 214                                 next_index = idx;
 215                                 break;
 216                         }
 217                 }
 218                 /*
 219                  * C1 is always valid.
 220                  * So, no need to check for 'next_index == -1' outside
 221                  * this loop.
 222                  */
 223         }
 224
 225         return next_index;
 226 }
 227
 228 /**
 229  * omap3_enter_idle_bm - Checks for any bus activity
 230  * @dev: cpuidle device
 231  * @drv: cpuidle driver
 232  * @index: array index of target state to be programmed
 233  *
 234  * This function checks for any pending activity and then programs
 235  * the device to the specified or a safer state.
 236  */
 237 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 238                                 struct cpuidle_driver *drv,
 239                                int index)
 240 {
 241         int new_state_idx;
 242         u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
 243         struct omap3_idle_statedata *cx;
 244         int ret;
 245
 246         if (!omap3_can_sleep()) {
 247                 new_state_idx = drv->safe_state_index;
 248                 goto select_state;
 249         }
 250
 251         /*
 252          * Prevent idle completely if CAM is active.
 253          * CAM does not have wakeup capability in OMAP3.
 254          */
 255         cam_state = pwrdm_read_pwrst(cam_pd);
 256         if (cam_state == PWRDM_POWER_ON) {
 257                 new_state_idx = drv->safe_state_index;
 258                 goto select_state;
 259         }
 260
 261         /*
 262          * FIXME: we currently manage device-specific idle states
 263          *        for PER and CORE in combination with CPU-specific
 264          *        idle states.  This is wrong, and device-specific
 265          *        idle management needs to be separated out into
 266          *        its own code.
 267          */
 268
 269         /*
 270          * Prevent PER off if CORE is not in retention or off as this
 271          * would disable PER wakeups completely.
 272          */
 273         cx = cpuidle_get_statedata(&dev->states_usage[index]);
 274         core_next_state = cx->core_state;
 275         per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
 276         if ((per_next_state == PWRDM_POWER_OFF) &&
 277             (core_next_state > PWRDM_POWER_RET))
 278                 per_next_state = PWRDM_POWER_RET;
 279
 280         /* Are we changing PER target state? */
 281         if (per_next_state != per_saved_state)
 282                 pwrdm_set_next_pwrst(per_pd, per_next_state);
 283
 284         new_state_idx = next_valid_state(dev, drv, index);
 285
 286 select_state:
 287         ret = omap3_enter_idle(dev, drv, new_state_idx);
 288
 289         /* Restore original PER state if it was modified */
 290         if (per_next_state != per_saved_state)
 291                 pwrdm_set_next_pwrst(per_pd, per_saved_state);
 292
 293         return ret;
 294 }
 295
 296 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 297
 298 void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
 299 {
 300         int i;
 301
 302         if (!cpuidle_board_params)
 303                 return;
 304
 305         for (i = 0; i < OMAP3_NUM_STATES; i++) {
 306                 cpuidle_params_table[i].valid = cpuidle_board_params[i].valid;
 307                 cpuidle_params_table[i].exit_latency =
 308                         cpuidle_board_params[i].exit_latency;
 309                 cpuidle_params_table[i].target_residency =
 310                         cpuidle_board_params[i].target_residency;
 311         }
 312         return;
 313 }
 314
 315 struct cpuidle_driver omap3_idle_driver = {
 316         .name =         "omap3_idle",
 317         .owner =        THIS_MODULE,
 318 };
 319
 320 /* Helper to fill the C-state common data*/
 321 static inline void _fill_cstate(struct cpuidle_driver *drv,
 322                                         int idx, const char *descr)
 323 {
 324         struct cpuidle_state *state = &drv->states[idx];
 325
 326         state->exit_latency     = cpuidle_params_table[idx].exit_latency;
 327         state->target_residency = cpuidle_params_table[idx].target_residency;
 328         state->flags            = CPUIDLE_FLAG_TIME_VALID;
 329         state->enter            = omap3_enter_idle_bm;
 330         sprintf(state->name, "C%d", idx + 1);
 331         strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
 332
 333 }
 334
 335 /* Helper to register the driver_data */
 336 static inline struct omap3_idle_statedata *_fill_cstate_usage(
 337                                         struct cpuidle_device *dev,
 338                                         int idx)
 339 {
 340         struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
 341         struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
 342
 343         cx->valid               = cpuidle_params_table[idx].valid;
 344         cpuidle_set_statedata(state_usage, cx);
 345
 346         return cx;
 347 }
 348
 349 /**
 350  * omap3_idle_init - Init routine for OMAP3 idle
 351  *
 352  * Registers the OMAP3 specific cpuidle driver to the cpuidle
 353  * framework with the valid set of states.
 354  */
 355 int __init omap3_idle_init(void)
 356 {
 357         struct cpuidle_device *dev;
 358         struct cpuidle_driver *drv = &omap3_idle_driver;
 359         struct omap3_idle_statedata *cx;
 360
 361         mpu_pd = pwrdm_lookup("mpu_pwrdm");
 362         core_pd = pwrdm_lookup("core_pwrdm");
 363         per_pd = pwrdm_lookup("per_pwrdm");
 364         cam_pd = pwrdm_lookup("cam_pwrdm");
 365
 366
 367         drv->safe_state_index = -1;
 368         dev = &per_cpu(omap3_idle_dev, smp_processor_id());
 369
 370         /* C1 . MPU WFI + Core active */
 371         _fill_cstate(drv, 0, "MPU ON + CORE ON");
 372         (&drv->states[0])->enter = omap3_enter_idle;
 373         drv->safe_state_index = 0;
 374         cx = _fill_cstate_usage(dev, 0);
 375         cx->valid = 1;  /* C1 is always valid */
 376         cx->mpu_state = PWRDM_POWER_ON;
 377         cx->core_state = PWRDM_POWER_ON;
 378
 379         /* C2 . MPU WFI + Core inactive */
 380         _fill_cstate(drv, 1, "MPU ON + CORE ON");
 381         cx = _fill_cstate_usage(dev, 1);
 382         cx->mpu_state = PWRDM_POWER_ON;
 383         cx->core_state = PWRDM_POWER_ON;
 384
 385         /* C3 . MPU CSWR + Core inactive */
 386         _fill_cstate(drv, 2, "MPU RET + CORE ON");
 387         cx = _fill_cstate_usage(dev, 2);
 388         cx->mpu_state = PWRDM_POWER_RET;
 389         cx->core_state = PWRDM_POWER_ON;
 390
 391         /* C4 . MPU OFF + Core inactive */
 392         _fill_cstate(drv, 3, "MPU OFF + CORE ON");
 393         cx = _fill_cstate_usage(dev, 3);
 394         cx->mpu_state = PWRDM_POWER_OFF;
 395         cx->core_state = PWRDM_POWER_ON;
 396
 397         /* C5 . MPU RET + Core RET */
 398         _fill_cstate(drv, 4, "MPU RET + CORE RET");
 399         cx = _fill_cstate_usage(dev, 4);
 400         cx->mpu_state = PWRDM_POWER_RET;
 401         cx->core_state = PWRDM_POWER_RET;
 402
 403         /* C6 . MPU OFF + Core RET */
 404         _fill_cstate(drv, 5, "MPU OFF + CORE RET");
 405         cx = _fill_cstate_usage(dev, 5);
 406         cx->mpu_state = PWRDM_POWER_OFF;
 407         cx->core_state = PWRDM_POWER_RET;
 408
 409         /* C7 . MPU OFF + Core OFF */
 410         _fill_cstate(drv, 6, "MPU OFF + CORE OFF");
 411         cx = _fill_cstate_usage(dev, 6);
 412         /*
 413          * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
 414          * enable OFF mode in a stable form for previous revisions.
 415          * We disable C7 state as a result.
 416          */
 417         if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
 418                 cx->valid = 0;
 419                 pr_warn("%s: core off state C7 disabled due to i583\n",
 420                         __func__);
 421         }
 422         cx->mpu_state = PWRDM_POWER_OFF;
 423         cx->core_state = PWRDM_POWER_OFF;
 424
 425         drv->state_count = OMAP3_NUM_STATES;
 426         cpuidle_register_driver(&omap3_idle_driver);
 427
 428         dev->state_count = OMAP3_NUM_STATES;
 429         if (cpuidle_register_device(dev)) {
 430                 printk(KERN_ERR "%s: CPUidle register device failed\n",
 431                        __func__);
 432                 return -EIO;
 433         }
 434
 435         return 0;
 436 }
 437 #else
 438 int __init omap3_idle_init(void)
 439 {
 440         return 0;
 441 }
 442 #endif /* CONFIG_CPU_IDLE */