arch/arm/mach-omap2/cpuidle34xx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/cpuidle34xx.c
   3  *
   4  * OMAP3 CPU IDLE Routines
   5  *
   6  * Copyright (C) 2008 Texas Instruments, Inc.
   7  * Rajendra Nayak <rnayak@ti.com>
   8  *
   9  * Copyright (C) 2007 Texas Instruments, Inc.
  10  * Karthik Dasu <karthik-dp@ti.com>
  11  *
  12  * Copyright (C) 2006 Nokia Corporation
  13  * Tony Lindgren <tony@atomide.com>
  14  *
  15  * Copyright (C) 2005 Texas Instruments, Inc.
  16  * Richard Woodruff <r-woodruff2@ti.com>
  17  *
  18  * Based on pm.c for omap2
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License version 2 as
  22  * published by the Free Software Foundation.
  23  */
  24
  25 #include <linux/sched.h>
  26 #include <linux/cpuidle.h>
  27 #include <linux/export.h>
  28 #include <linux/cpu_pm.h>
  29
  30 #include <plat/prcm.h>
  31 #include <plat/irqs.h>
  32 #include "powerdomain.h"
  33 #include "clockdomain.h"
  34
  35 #include "pm.h"
  36 #include "control.h"
  37 #include "common.h"
  38
  39 #ifdef CONFIG_CPU_IDLE
  40
  41 /* Mach specific information to be recorded in the C-state driver_data */
  42 struct omap3_idle_statedata {
  43         u32 mpu_state;
  44         u32 core_state;
  45 };
  46
  47 struct omap3_idle_statedata omap3_idle_data[] = {
  48         {
  49                 .mpu_state = PWRDM_POWER_ON,
  50                 .core_state = PWRDM_POWER_ON,
  51         },
  52         {
  53                 .mpu_state = PWRDM_POWER_ON,
  54                 .core_state = PWRDM_POWER_ON,
  55         },
  56         {
  57                 .mpu_state = PWRDM_POWER_RET,
  58                 .core_state = PWRDM_POWER_ON,
  59         },
  60         {
  61                 .mpu_state = PWRDM_POWER_OFF,
  62                 .core_state = PWRDM_POWER_ON,
  63         },
  64         {
  65                 .mpu_state = PWRDM_POWER_RET,
  66                 .core_state = PWRDM_POWER_RET,
  67         },
  68         {
  69                 .mpu_state = PWRDM_POWER_OFF,
  70                 .core_state = PWRDM_POWER_RET,
  71         },
  72         {
  73                 .mpu_state = PWRDM_POWER_OFF,
  74                 .core_state = PWRDM_POWER_OFF,
  75         },
  76 };
  77
  78 struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
  79
  80 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
  81                                 struct clockdomain *clkdm)
  82 {
  83         clkdm_allow_idle(clkdm);
  84         return 0;
  85 }
  86
  87 static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
  88                                 struct clockdomain *clkdm)
  89 {
  90         clkdm_deny_idle(clkdm);
  91         return 0;
  92 }
  93
  94 static int __omap3_enter_idle(struct cpuidle_device *dev,
  95                                 struct cpuidle_driver *drv,
  96                                 int index)
  97 {
  98         struct omap3_idle_statedata *cx = &omap3_idle_data[index];
  99         u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
 100
 101         local_fiq_disable();
 102
 103         pwrdm_set_next_pwrst(mpu_pd, mpu_state);
 104         pwrdm_set_next_pwrst(core_pd, core_state);
 105
 106         if (omap_irq_pending() || need_resched())
 107                 goto return_sleep_time;
 108
 109         /* Deny idle for C1 */
 110         if (index == 0) {
 111                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
 112                 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
 113         }
 114
 115         /*
 116          * Call idle CPU PM enter notifier chain so that
 117          * VFP context is saved.
 118          */
 119         if (mpu_state == PWRDM_POWER_OFF)
 120                 cpu_pm_enter();
 121
 122         /* Execute ARM wfi */
 123         omap_sram_idle();
 124
 125         /*
 126          * Call idle CPU PM enter notifier chain to restore
 127          * VFP context.
 128          */
 129         if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
 130                 cpu_pm_exit();
 131
 132         /* Re-allow idle for C1 */
 133         if (index == 0) {
 134                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
 135                 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
 136         }
 137
 138 return_sleep_time:
 139
 140         local_fiq_enable();
 141
 142         return index;
 143 }
 144
 145 /**
 146  * omap3_enter_idle - Programs OMAP3 to enter the specified state
 147  * @dev: cpuidle device
 148  * @drv: cpuidle driver
 149  * @index: the index of state to be entered
 150  *
 151  * Called from the CPUidle framework to program the device to the
 152  * specified target state selected by the governor.
 153  */
 154 static inline int omap3_enter_idle(struct cpuidle_device *dev,
 155                                 struct cpuidle_driver *drv,
 156                                 int index)
 157 {
 158         return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
 159 }
 160
 161 /**
 162  * next_valid_state - Find next valid C-state
 163  * @dev: cpuidle device
 164  * @drv: cpuidle driver
 165  * @index: Index of currently selected c-state
 166  *
 167  * If the state corresponding to index is valid, index is returned back
 168  * to the caller. Else, this function searches for a lower c-state which is
 169  * still valid (as defined in omap3_power_states[]) and returns its index.
 170  *
 171  * A state is valid if the 'valid' field is enabled and
 172  * if it satisfies the enable_off_mode condition.
 173  */
 174 static int next_valid_state(struct cpuidle_device *dev,
 175                         struct cpuidle_driver *drv,
 176                                 int index)
 177 {
 178         struct cpuidle_state *curr = &drv->states[index];
 179         struct omap3_idle_statedata *cx = &omap3_idle_data[index];
 180         u32 mpu_deepest_state = PWRDM_POWER_RET;
 181         u32 core_deepest_state = PWRDM_POWER_RET;
 182         int next_index = -1;
 183
 184         if (enable_off_mode) {
 185                 mpu_deepest_state = PWRDM_POWER_OFF;
 186                 /*
 187                  * Erratum i583: valable for ES rev < Es1.2 on 3630.
 188                  * CORE OFF mode is not supported in a stable form, restrict
 189                  * instead the CORE state to RET.
 190                  */
 191                 if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
 192                         core_deepest_state = PWRDM_POWER_OFF;
 193         }
 194
 195         /* Check if current state is valid */
 196         if ((cx->mpu_state >= mpu_deepest_state) &&
 197             (cx->core_state >= core_deepest_state)) {
 198                 return index;
 199         } else {
 200                 int idx = ARRAY_SIZE(omap3_idle_data) - 1;
 201
 202                 /* Reach the current state starting at highest C-state */
 203                 for (; idx >= 0; idx--) {
 204                         if (&drv->states[idx] == curr) {
 205                                 next_index = idx;
 206                                 break;
 207                         }
 208                 }
 209
 210                 /* Should never hit this condition */
 211                 WARN_ON(next_index == -1);
 212
 213                 /*
 214                  * Drop to next valid state.
 215                  * Start search from the next (lower) state.
 216                  */
 217                 idx--;
 218                 for (; idx >= 0; idx--) {
 219                         cx =  &omap3_idle_data[idx];
 220                         if ((cx->mpu_state >= mpu_deepest_state) &&
 221                             (cx->core_state >= core_deepest_state)) {
 222                                 next_index = idx;
 223                                 break;
 224                         }
 225                 }
 226                 /*
 227                  * C1 is always valid.
 228                  * So, no need to check for 'next_index == -1' outside
 229                  * this loop.
 230                  */
 231         }
 232
 233         return next_index;
 234 }
 235
 236 /**
 237  * omap3_enter_idle_bm - Checks for any bus activity
 238  * @dev: cpuidle device
 239  * @drv: cpuidle driver
 240  * @index: array index of target state to be programmed
 241  *
 242  * This function checks for any pending activity and then programs
 243  * the device to the specified or a safer state.
 244  */
 245 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 246                                 struct cpuidle_driver *drv,
 247                                int index)
 248 {
 249         int new_state_idx;
 250         u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
 251         struct omap3_idle_statedata *cx;
 252         int ret;
 253
 254         /*
 255          * Prevent idle completely if CAM is active.
 256          * CAM does not have wakeup capability in OMAP3.
 257          */
 258         cam_state = pwrdm_read_pwrst(cam_pd);
 259         if (cam_state == PWRDM_POWER_ON) {
 260                 new_state_idx = drv->safe_state_index;
 261                 goto select_state;
 262         }
 263
 264         /*
 265          * FIXME: we currently manage device-specific idle states
 266          *        for PER and CORE in combination with CPU-specific
 267          *        idle states.  This is wrong, and device-specific
 268          *        idle management needs to be separated out into
 269          *        its own code.
 270          */
 271
 272         /*
 273          * Prevent PER off if CORE is not in retention or off as this
 274          * would disable PER wakeups completely.
 275          */
 276         cx = &omap3_idle_data[index];
 277         core_next_state = cx->core_state;
 278         per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
 279         if ((per_next_state == PWRDM_POWER_OFF) &&
 280             (core_next_state > PWRDM_POWER_RET))
 281                 per_next_state = PWRDM_POWER_RET;
 282
 283         /* Are we changing PER target state? */
 284         if (per_next_state != per_saved_state)
 285                 pwrdm_set_next_pwrst(per_pd, per_next_state);
 286
 287         new_state_idx = next_valid_state(dev, drv, index);
 288
 289 select_state:
 290         ret = omap3_enter_idle(dev, drv, new_state_idx);
 291
 292         /* Restore original PER state if it was modified */
 293         if (per_next_state != per_saved_state)
 294                 pwrdm_set_next_pwrst(per_pd, per_saved_state);
 295
 296         return ret;
 297 }
 298
 299 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 300
 301 struct cpuidle_driver omap3_idle_driver = {
 302         .name =         "omap3_idle",
 303         .owner =        THIS_MODULE,
 304         .states = {
 305                 {
 306                         .enter            = omap3_enter_idle,
 307                         .exit_latency     = 2 + 2,
 308                         .target_residency = 5,
 309                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 310                         .name             = "C1",
 311                         .desc             = "MPU ON + CORE ON",
 312                 },
 313                 {
 314                         .enter            = omap3_enter_idle_bm,
 315                         .exit_latency     = 10 + 10,
 316                         .target_residency = 30,
 317                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 318                         .name             = "C2",
 319                         .desc             = "MPU ON + CORE ON",
 320                 },
 321                 {
 322                         .enter            = omap3_enter_idle_bm,
 323                         .exit_latency     = 50 + 50,
 324                         .target_residency = 300,
 325                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 326                         .name             = "C3",
 327                         .desc             = "MPU RET + CORE ON",
 328                 },
 329                 {
 330                         .enter            = omap3_enter_idle_bm,
 331                         .exit_latency     = 1500 + 1800,
 332                         .target_residency = 4000,
 333                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 334                         .name             = "C4",
 335                         .desc             = "MPU OFF + CORE ON",
 336                 },
 337                 {
 338                         .enter            = omap3_enter_idle_bm,
 339                         .exit_latency     = 2500 + 7500,
 340                         .target_residency = 12000,
 341                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 342                         .name             = "C5",
 343                         .desc             = "MPU RET + CORE RET",
 344                 },
 345                 {
 346                         .enter            = omap3_enter_idle_bm,
 347                         .exit_latency     = 3000 + 8500,
 348                         .target_residency = 15000,
 349                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 350                         .name             = "C6",
 351                         .desc             = "MPU OFF + CORE RET",
 352                 },
 353                 {
 354                         .enter            = omap3_enter_idle_bm,
 355                         .exit_latency     = 10000 + 30000,
 356                         .target_residency = 30000,
 357                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 358                         .name             = "C7",
 359                         .desc             = "MPU OFF + CORE OFF",
 360                 },
 361         },
 362         .state_count = ARRAY_SIZE(omap3_idle_data),
 363         .safe_state_index = 0,
 364 };
 365
 366 /**
 367  * omap3_idle_init - Init routine for OMAP3 idle
 368  *
 369  * Registers the OMAP3 specific cpuidle driver to the cpuidle
 370  * framework with the valid set of states.
 371  */
 372 int __init omap3_idle_init(void)
 373 {
 374         struct cpuidle_device *dev;
 375
 376         mpu_pd = pwrdm_lookup("mpu_pwrdm");
 377         core_pd = pwrdm_lookup("core_pwrdm");
 378         per_pd = pwrdm_lookup("per_pwrdm");
 379         cam_pd = pwrdm_lookup("cam_pwrdm");
 380
 381         cpuidle_register_driver(&omap3_idle_driver);
 382
 383         dev = &per_cpu(omap3_idle_dev, smp_processor_id());
 384         dev->cpu = 0;
 385
 386         if (cpuidle_register_device(dev)) {
 387                 printk(KERN_ERR "%s: CPUidle register device failed\n",
 388                        __func__);
 389                 return -EIO;
 390         }
 391
 392         return 0;
 393 }
 394 #else
 395 int __init omap3_idle_init(void)
 396 {
 397         return 0;
 398 }
 399 #endif /* CONFIG_CPU_IDLE */