arch/arm/mach-omap2/cpuidle34xx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/cpuidle34xx.c
   3  *
   4  * OMAP3 CPU IDLE Routines
   5  *
   6  * Copyright (C) 2008 Texas Instruments, Inc.
   7  * Rajendra Nayak <rnayak@ti.com>
   8  *
   9  * Copyright (C) 2007 Texas Instruments, Inc.
  10  * Karthik Dasu <karthik-dp@ti.com>
  11  *
  12  * Copyright (C) 2006 Nokia Corporation
  13  * Tony Lindgren <tony@atomide.com>
  14  *
  15  * Copyright (C) 2005 Texas Instruments, Inc.
  16  * Richard Woodruff <r-woodruff2@ti.com>
  17  *
  18  * Based on pm.c for omap2
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License version 2 as
  22  * published by the Free Software Foundation.
  23  */
  24
  25 #include <linux/sched.h>
  26 #include <linux/cpuidle.h>
  27 #include <linux/export.h>
  28 #include <linux/cpu_pm.h>
  29
  30 #include <plat/prcm.h>
  31 #include <plat/irqs.h>
  32 #include "powerdomain.h"
  33 #include "clockdomain.h"
  34
  35 #include "pm.h"
  36 #include "control.h"
  37 #include "common.h"
  38
  39 #ifdef CONFIG_CPU_IDLE
  40
  41 /*
  42  * The latencies/thresholds for various C states have
  43  * to be configured from the respective board files.
  44  * These are some default values (which might not provide
  45  * the best power savings) used on boards which do not
  46  * pass these details from the board file.
  47  */
  48 static struct cpuidle_params cpuidle_params_table[] = {
  49         /* C1 */
  50         {2 + 2, 5, 1},
  51         /* C2 */
  52         {10 + 10, 30, 1},
  53         /* C3 */
  54         {50 + 50, 300, 1},
  55         /* C4 */
  56         {1500 + 1800, 4000, 1},
  57         /* C5 */
  58         {2500 + 7500, 12000, 1},
  59         /* C6 */
  60         {3000 + 8500, 15000, 1},
  61         /* C7 */
  62         {10000 + 30000, 300000, 1},
  63 };
  64 #define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
  65
  66 /* Mach specific information to be recorded in the C-state driver_data */
  67 struct omap3_idle_statedata {
  68         u32 mpu_state;
  69         u32 core_state;
  70 };
  71 struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
  72
  73 struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
  74
  75 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
  76                                 struct clockdomain *clkdm)
  77 {
  78         clkdm_allow_idle(clkdm);
  79         return 0;
  80 }
  81
  82 static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
  83                                 struct clockdomain *clkdm)
  84 {
  85         clkdm_deny_idle(clkdm);
  86         return 0;
  87 }
  88
  89 static int __omap3_enter_idle(struct cpuidle_device *dev,
  90                                 struct cpuidle_driver *drv,
  91                                 int index)
  92 {
  93         struct omap3_idle_statedata *cx =
  94                         cpuidle_get_statedata(&dev->states_usage[index]);
  95         u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
  96
  97         local_fiq_disable();
  98
  99         pwrdm_set_next_pwrst(mpu_pd, mpu_state);
 100         pwrdm_set_next_pwrst(core_pd, core_state);
 101
 102         if (omap_irq_pending() || need_resched())
 103                 goto return_sleep_time;
 104
 105         /* Deny idle for C1 */
 106         if (index == 0) {
 107                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
 108                 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
 109         }
 110
 111         /*
 112          * Call idle CPU PM enter notifier chain so that
 113          * VFP context is saved.
 114          */
 115         if (mpu_state == PWRDM_POWER_OFF)
 116                 cpu_pm_enter();
 117
 118         /* Execute ARM wfi */
 119         omap_sram_idle();
 120
 121         /*
 122          * Call idle CPU PM enter notifier chain to restore
 123          * VFP context.
 124          */
 125         if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
 126                 cpu_pm_exit();
 127
 128         /* Re-allow idle for C1 */
 129         if (index == 0) {
 130                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
 131                 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
 132         }
 133
 134 return_sleep_time:
 135
 136         local_fiq_enable();
 137
 138         return index;
 139 }
 140
 141 /**
 142  * omap3_enter_idle - Programs OMAP3 to enter the specified state
 143  * @dev: cpuidle device
 144  * @drv: cpuidle driver
 145  * @index: the index of state to be entered
 146  *
 147  * Called from the CPUidle framework to program the device to the
 148  * specified target state selected by the governor.
 149  */
 150 static inline int omap3_enter_idle(struct cpuidle_device *dev,
 151                                 struct cpuidle_driver *drv,
 152                                 int index)
 153 {
 154         return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
 155 }
 156
 157 /**
 158  * next_valid_state - Find next valid C-state
 159  * @dev: cpuidle device
 160  * @drv: cpuidle driver
 161  * @index: Index of currently selected c-state
 162  *
 163  * If the state corresponding to index is valid, index is returned back
 164  * to the caller. Else, this function searches for a lower c-state which is
 165  * still valid (as defined in omap3_power_states[]) and returns its index.
 166  *
 167  * A state is valid if the 'valid' field is enabled and
 168  * if it satisfies the enable_off_mode condition.
 169  */
 170 static int next_valid_state(struct cpuidle_device *dev,
 171                         struct cpuidle_driver *drv,
 172                                 int index)
 173 {
 174         struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
 175         struct cpuidle_state *curr = &drv->states[index];
 176         struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
 177         u32 mpu_deepest_state = PWRDM_POWER_RET;
 178         u32 core_deepest_state = PWRDM_POWER_RET;
 179         int next_index = -1;
 180
 181         if (enable_off_mode) {
 182                 mpu_deepest_state = PWRDM_POWER_OFF;
 183                 /*
 184                  * Erratum i583: valable for ES rev < Es1.2 on 3630.
 185                  * CORE OFF mode is not supported in a stable form, restrict
 186                  * instead the CORE state to RET.
 187                  */
 188                 if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
 189                         core_deepest_state = PWRDM_POWER_OFF;
 190         }
 191
 192         /* Check if current state is valid */
 193         if ((cx->mpu_state >= mpu_deepest_state) &&
 194             (cx->core_state >= core_deepest_state)) {
 195                 return index;
 196         } else {
 197                 int idx = OMAP3_NUM_STATES - 1;
 198
 199                 /* Reach the current state starting at highest C-state */
 200                 for (; idx >= 0; idx--) {
 201                         if (&drv->states[idx] == curr) {
 202                                 next_index = idx;
 203                                 break;
 204                         }
 205                 }
 206
 207                 /* Should never hit this condition */
 208                 WARN_ON(next_index == -1);
 209
 210                 /*
 211                  * Drop to next valid state.
 212                  * Start search from the next (lower) state.
 213                  */
 214                 idx--;
 215                 for (; idx >= 0; idx--) {
 216                         cx = cpuidle_get_statedata(&dev->states_usage[idx]);
 217                         if ((cx->mpu_state >= mpu_deepest_state) &&
 218                             (cx->core_state >= core_deepest_state)) {
 219                                 next_index = idx;
 220                                 break;
 221                         }
 222                 }
 223                 /*
 224                  * C1 is always valid.
 225                  * So, no need to check for 'next_index == -1' outside
 226                  * this loop.
 227                  */
 228         }
 229
 230         return next_index;
 231 }
 232
 233 /**
 234  * omap3_enter_idle_bm - Checks for any bus activity
 235  * @dev: cpuidle device
 236  * @drv: cpuidle driver
 237  * @index: array index of target state to be programmed
 238  *
 239  * This function checks for any pending activity and then programs
 240  * the device to the specified or a safer state.
 241  */
 242 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 243                                 struct cpuidle_driver *drv,
 244                                int index)
 245 {
 246         int new_state_idx;
 247         u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
 248         struct omap3_idle_statedata *cx;
 249         int ret;
 250
 251         /*
 252          * Prevent idle completely if CAM is active.
 253          * CAM does not have wakeup capability in OMAP3.
 254          */
 255         cam_state = pwrdm_read_pwrst(cam_pd);
 256         if (cam_state == PWRDM_POWER_ON) {
 257                 new_state_idx = drv->safe_state_index;
 258                 goto select_state;
 259         }
 260
 261         /*
 262          * FIXME: we currently manage device-specific idle states
 263          *        for PER and CORE in combination with CPU-specific
 264          *        idle states.  This is wrong, and device-specific
 265          *        idle management needs to be separated out into
 266          *        its own code.
 267          */
 268
 269         /*
 270          * Prevent PER off if CORE is not in retention or off as this
 271          * would disable PER wakeups completely.
 272          */
 273         cx = cpuidle_get_statedata(&dev->states_usage[index]);
 274         core_next_state = cx->core_state;
 275         per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
 276         if ((per_next_state == PWRDM_POWER_OFF) &&
 277             (core_next_state > PWRDM_POWER_RET))
 278                 per_next_state = PWRDM_POWER_RET;
 279
 280         /* Are we changing PER target state? */
 281         if (per_next_state != per_saved_state)
 282                 pwrdm_set_next_pwrst(per_pd, per_next_state);
 283
 284         new_state_idx = next_valid_state(dev, drv, index);
 285
 286 select_state:
 287         ret = omap3_enter_idle(dev, drv, new_state_idx);
 288
 289         /* Restore original PER state if it was modified */
 290         if (per_next_state != per_saved_state)
 291                 pwrdm_set_next_pwrst(per_pd, per_saved_state);
 292
 293         return ret;
 294 }
 295
 296 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 297
 298 struct cpuidle_driver omap3_idle_driver = {
 299         .name =         "omap3_idle",
 300         .owner =        THIS_MODULE,
 301         .states = {
 302                 {
 303                         .enter            = omap3_enter_idle,
 304                         .exit_latency     = 2 + 2,
 305                         .target_residency = 5,
 306                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 307                         .name             = "C1",
 308                         .desc             = "MPU ON + CORE ON",
 309                 },
 310                 {
 311                         .enter            = omap3_enter_idle_bm,
 312                         .exit_latency     = 10 + 10,
 313                         .target_residency = 30,
 314                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 315                         .name             = "C2",
 316                         .desc             = "MPU ON + CORE ON",
 317                 },
 318                 {
 319                         .enter            = omap3_enter_idle_bm,
 320                         .exit_latency     = 50 + 50,
 321                         .target_residency = 300,
 322                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 323                         .name             = "C3",
 324                         .desc             = "MPU RET + CORE ON",
 325                 },
 326                 {
 327                         .enter            = omap3_enter_idle_bm,
 328                         .exit_latency     = 1500 + 1800,
 329                         .target_residency = 4000,
 330                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 331                         .name             = "C4",
 332                         .desc             = "MPU OFF + CORE ON",
 333                 },
 334                 {
 335                         .enter            = omap3_enter_idle_bm,
 336                         .exit_latency     = 2500 + 7500,
 337                         .target_residency = 12000,
 338                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 339                         .name             = "C5",
 340                         .desc             = "MPU RET + CORE RET",
 341                 },
 342                 {
 343                         .enter            = omap3_enter_idle_bm,
 344                         .exit_latency     = 3000 + 8500,
 345                         .target_residency = 15000,
 346                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 347                         .name             = "C6",
 348                         .desc             = "MPU OFF + CORE RET",
 349                 },
 350                 {
 351                         .enter            = omap3_enter_idle_bm,
 352                         .exit_latency     = 10000 + 30000,
 353                         .target_residency = 30000,
 354                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 355                         .name             = "C7",
 356                         .desc             = "MPU OFF + CORE OFF",
 357                 },
 358         },
 359         .state_count = OMAP3_NUM_STATES,
 360         .safe_state_index = 0,
 361 };
 362
 363 /* Helper to register the driver_data */
 364 static inline struct omap3_idle_statedata *_fill_cstate_usage(
 365                                         struct cpuidle_device *dev,
 366                                         int idx)
 367 {
 368         struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
 369         struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
 370
 371         cpuidle_set_statedata(state_usage, cx);
 372
 373         return cx;
 374 }
 375
 376 /**
 377  * omap3_idle_init - Init routine for OMAP3 idle
 378  *
 379  * Registers the OMAP3 specific cpuidle driver to the cpuidle
 380  * framework with the valid set of states.
 381  */
 382 int __init omap3_idle_init(void)
 383 {
 384         struct cpuidle_device *dev;
 385         struct omap3_idle_statedata *cx;
 386
 387         mpu_pd = pwrdm_lookup("mpu_pwrdm");
 388         core_pd = pwrdm_lookup("core_pwrdm");
 389         per_pd = pwrdm_lookup("per_pwrdm");
 390         cam_pd = pwrdm_lookup("cam_pwrdm");
 391
 392
 393         dev = &per_cpu(omap3_idle_dev, smp_processor_id());
 394
 395         /* C1 . MPU WFI + Core active */
 396         cx = _fill_cstate_usage(dev, 0);
 397         cx->mpu_state = PWRDM_POWER_ON;
 398         cx->core_state = PWRDM_POWER_ON;
 399
 400         /* C2 . MPU WFI + Core inactive */
 401         cx = _fill_cstate_usage(dev, 1);
 402         cx->mpu_state = PWRDM_POWER_ON;
 403         cx->core_state = PWRDM_POWER_ON;
 404
 405         /* C3 . MPU CSWR + Core inactive */
 406         cx = _fill_cstate_usage(dev, 2);
 407         cx->mpu_state = PWRDM_POWER_RET;
 408         cx->core_state = PWRDM_POWER_ON;
 409
 410         /* C4 . MPU OFF + Core inactive */
 411         cx = _fill_cstate_usage(dev, 3);
 412         cx->mpu_state = PWRDM_POWER_OFF;
 413         cx->core_state = PWRDM_POWER_ON;
 414
 415         /* C5 . MPU RET + Core RET */
 416         cx = _fill_cstate_usage(dev, 4);
 417         cx->mpu_state = PWRDM_POWER_RET;
 418         cx->core_state = PWRDM_POWER_RET;
 419
 420         /* C6 . MPU OFF + Core RET */
 421         cx = _fill_cstate_usage(dev, 5);
 422         cx->mpu_state = PWRDM_POWER_OFF;
 423         cx->core_state = PWRDM_POWER_RET;
 424
 425         /* C7 . MPU OFF + Core OFF */
 426         cx = _fill_cstate_usage(dev, 6);
 427         cx->mpu_state = PWRDM_POWER_OFF;
 428         cx->core_state = PWRDM_POWER_OFF;
 429
 430         cpuidle_register_driver(&omap3_idle_driver);
 431
 432         if (cpuidle_register_device(dev)) {
 433                 printk(KERN_ERR "%s: CPUidle register device failed\n",
 434                        __func__);
 435                 return -EIO;
 436         }
 437
 438         return 0;
 439 }
 440 #else
 441 int __init omap3_idle_init(void)
 442 {
 443         return 0;
 444 }
 445 #endif /* CONFIG_CPU_IDLE */