2 * linux/arch/arm/mach-omap2/cpuidle34xx.c
4 * OMAP3 CPU IDLE Routines
6 * Copyright (C) 2008 Texas Instruments, Inc.
7 * Rajendra Nayak <rnayak@ti.com>
9 * Copyright (C) 2007 Texas Instruments, Inc.
10 * Karthik Dasu <karthik-dp@ti.com>
12 * Copyright (C) 2006 Nokia Corporation
13 * Tony Lindgren <tony@atomide.com>
15 * Copyright (C) 2005 Texas Instruments, Inc.
16 * Richard Woodruff <r-woodruff2@ti.com>
18 * Based on pm.c for omap2
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License version 2 as
22 * published by the Free Software Foundation.
25 #include <linux/sched.h>
26 #include <linux/cpuidle.h>
27 #include <linux/export.h>
28 #include <linux/cpu_pm.h>
30 #include <plat/prcm.h>
31 #include <plat/irqs.h>
32 #include "powerdomain.h"
33 #include "clockdomain.h"
39 #ifdef CONFIG_CPU_IDLE
42 * The latencies/thresholds for various C states have
43 * to be configured from the respective board files.
44 * These are some default values (which might not provide
45 * the best power savings) used on boards which do not
46 * pass these details from the board file.
48 static struct cpuidle_params cpuidle_params_table
[] = {
56 {1500 + 1800, 4000, 1},
58 {2500 + 7500, 12000, 1},
60 {3000 + 8500, 15000, 1},
62 {10000 + 30000, 300000, 1},
64 #define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
66 /* Mach specific information to be recorded in the C-state driver_data */
67 struct omap3_idle_statedata
{
71 struct omap3_idle_statedata omap3_idle_data
[OMAP3_NUM_STATES
];
73 struct powerdomain
*mpu_pd
, *core_pd
, *per_pd
, *cam_pd
;
75 static int _cpuidle_allow_idle(struct powerdomain
*pwrdm
,
76 struct clockdomain
*clkdm
)
78 clkdm_allow_idle(clkdm
);
82 static int _cpuidle_deny_idle(struct powerdomain
*pwrdm
,
83 struct clockdomain
*clkdm
)
85 clkdm_deny_idle(clkdm
);
89 static int __omap3_enter_idle(struct cpuidle_device
*dev
,
90 struct cpuidle_driver
*drv
,
93 struct omap3_idle_statedata
*cx
=
94 cpuidle_get_statedata(&dev
->states_usage
[index
]);
95 u32 mpu_state
= cx
->mpu_state
, core_state
= cx
->core_state
;
99 pwrdm_set_next_pwrst(mpu_pd
, mpu_state
);
100 pwrdm_set_next_pwrst(core_pd
, core_state
);
102 if (omap_irq_pending() || need_resched())
103 goto return_sleep_time
;
105 /* Deny idle for C1 */
107 pwrdm_for_each_clkdm(mpu_pd
, _cpuidle_deny_idle
);
108 pwrdm_for_each_clkdm(core_pd
, _cpuidle_deny_idle
);
112 * Call idle CPU PM enter notifier chain so that
113 * VFP context is saved.
115 if (mpu_state
== PWRDM_POWER_OFF
)
118 /* Execute ARM wfi */
122 * Call idle CPU PM enter notifier chain to restore
125 if (pwrdm_read_prev_pwrst(mpu_pd
) == PWRDM_POWER_OFF
)
128 /* Re-allow idle for C1 */
130 pwrdm_for_each_clkdm(mpu_pd
, _cpuidle_allow_idle
);
131 pwrdm_for_each_clkdm(core_pd
, _cpuidle_allow_idle
);
142 * omap3_enter_idle - Programs OMAP3 to enter the specified state
143 * @dev: cpuidle device
144 * @drv: cpuidle driver
145 * @index: the index of state to be entered
147 * Called from the CPUidle framework to program the device to the
148 * specified target state selected by the governor.
150 static inline int omap3_enter_idle(struct cpuidle_device
*dev
,
151 struct cpuidle_driver
*drv
,
154 return cpuidle_wrap_enter(dev
, drv
, index
, __omap3_enter_idle
);
158 * next_valid_state - Find next valid C-state
159 * @dev: cpuidle device
160 * @drv: cpuidle driver
161 * @index: Index of currently selected c-state
163 * If the state corresponding to index is valid, index is returned back
164 * to the caller. Else, this function searches for a lower c-state which is
165 * still valid (as defined in omap3_power_states[]) and returns its index.
167 * A state is valid if the 'valid' field is enabled and
168 * if it satisfies the enable_off_mode condition.
170 static int next_valid_state(struct cpuidle_device
*dev
,
171 struct cpuidle_driver
*drv
,
174 struct cpuidle_state_usage
*curr_usage
= &dev
->states_usage
[index
];
175 struct cpuidle_state
*curr
= &drv
->states
[index
];
176 struct omap3_idle_statedata
*cx
= cpuidle_get_statedata(curr_usage
);
177 u32 mpu_deepest_state
= PWRDM_POWER_RET
;
178 u32 core_deepest_state
= PWRDM_POWER_RET
;
181 if (enable_off_mode
) {
182 mpu_deepest_state
= PWRDM_POWER_OFF
;
184 * Erratum i583: valable for ES rev < Es1.2 on 3630.
185 * CORE OFF mode is not supported in a stable form, restrict
186 * instead the CORE state to RET.
188 if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583
))
189 core_deepest_state
= PWRDM_POWER_OFF
;
192 /* Check if current state is valid */
193 if ((cx
->mpu_state
>= mpu_deepest_state
) &&
194 (cx
->core_state
>= core_deepest_state
)) {
197 int idx
= OMAP3_NUM_STATES
- 1;
199 /* Reach the current state starting at highest C-state */
200 for (; idx
>= 0; idx
--) {
201 if (&drv
->states
[idx
] == curr
) {
207 /* Should never hit this condition */
208 WARN_ON(next_index
== -1);
211 * Drop to next valid state.
212 * Start search from the next (lower) state.
215 for (; idx
>= 0; idx
--) {
216 cx
= cpuidle_get_statedata(&dev
->states_usage
[idx
]);
217 if ((cx
->mpu_state
>= mpu_deepest_state
) &&
218 (cx
->core_state
>= core_deepest_state
)) {
224 * C1 is always valid.
225 * So, no need to check for 'next_index == -1' outside
234 * omap3_enter_idle_bm - Checks for any bus activity
235 * @dev: cpuidle device
236 * @drv: cpuidle driver
237 * @index: array index of target state to be programmed
239 * This function checks for any pending activity and then programs
240 * the device to the specified or a safer state.
242 static int omap3_enter_idle_bm(struct cpuidle_device
*dev
,
243 struct cpuidle_driver
*drv
,
247 u32 core_next_state
, per_next_state
= 0, per_saved_state
= 0, cam_state
;
248 struct omap3_idle_statedata
*cx
;
252 * Prevent idle completely if CAM is active.
253 * CAM does not have wakeup capability in OMAP3.
255 cam_state
= pwrdm_read_pwrst(cam_pd
);
256 if (cam_state
== PWRDM_POWER_ON
) {
257 new_state_idx
= drv
->safe_state_index
;
262 * FIXME: we currently manage device-specific idle states
263 * for PER and CORE in combination with CPU-specific
264 * idle states. This is wrong, and device-specific
265 * idle management needs to be separated out into
270 * Prevent PER off if CORE is not in retention or off as this
271 * would disable PER wakeups completely.
273 cx
= cpuidle_get_statedata(&dev
->states_usage
[index
]);
274 core_next_state
= cx
->core_state
;
275 per_next_state
= per_saved_state
= pwrdm_read_next_pwrst(per_pd
);
276 if ((per_next_state
== PWRDM_POWER_OFF
) &&
277 (core_next_state
> PWRDM_POWER_RET
))
278 per_next_state
= PWRDM_POWER_RET
;
280 /* Are we changing PER target state? */
281 if (per_next_state
!= per_saved_state
)
282 pwrdm_set_next_pwrst(per_pd
, per_next_state
);
284 new_state_idx
= next_valid_state(dev
, drv
, index
);
287 ret
= omap3_enter_idle(dev
, drv
, new_state_idx
);
289 /* Restore original PER state if it was modified */
290 if (per_next_state
!= per_saved_state
)
291 pwrdm_set_next_pwrst(per_pd
, per_saved_state
);
296 DEFINE_PER_CPU(struct cpuidle_device
, omap3_idle_dev
);
298 struct cpuidle_driver omap3_idle_driver
= {
299 .name
= "omap3_idle",
300 .owner
= THIS_MODULE
,
303 .enter
= omap3_enter_idle
,
304 .exit_latency
= 2 + 2,
305 .target_residency
= 5,
306 .flags
= CPUIDLE_FLAG_TIME_VALID
,
308 .desc
= "MPU ON + CORE ON",
311 .enter
= omap3_enter_idle_bm
,
312 .exit_latency
= 10 + 10,
313 .target_residency
= 30,
314 .flags
= CPUIDLE_FLAG_TIME_VALID
,
316 .desc
= "MPU ON + CORE ON",
319 .enter
= omap3_enter_idle_bm
,
320 .exit_latency
= 50 + 50,
321 .target_residency
= 300,
322 .flags
= CPUIDLE_FLAG_TIME_VALID
,
324 .desc
= "MPU RET + CORE ON",
327 .enter
= omap3_enter_idle_bm
,
328 .exit_latency
= 1500 + 1800,
329 .target_residency
= 4000,
330 .flags
= CPUIDLE_FLAG_TIME_VALID
,
332 .desc
= "MPU OFF + CORE ON",
335 .enter
= omap3_enter_idle_bm
,
336 .exit_latency
= 2500 + 7500,
337 .target_residency
= 12000,
338 .flags
= CPUIDLE_FLAG_TIME_VALID
,
340 .desc
= "MPU RET + CORE RET",
343 .enter
= omap3_enter_idle_bm
,
344 .exit_latency
= 3000 + 8500,
345 .target_residency
= 15000,
346 .flags
= CPUIDLE_FLAG_TIME_VALID
,
348 .desc
= "MPU OFF + CORE RET",
351 .enter
= omap3_enter_idle_bm
,
352 .exit_latency
= 10000 + 30000,
353 .target_residency
= 30000,
354 .flags
= CPUIDLE_FLAG_TIME_VALID
,
356 .desc
= "MPU OFF + CORE OFF",
359 .state_count
= OMAP3_NUM_STATES
,
360 .safe_state_index
= 0,
363 /* Helper to register the driver_data */
364 static inline struct omap3_idle_statedata
*_fill_cstate_usage(
365 struct cpuidle_device
*dev
,
368 struct omap3_idle_statedata
*cx
= &omap3_idle_data
[idx
];
369 struct cpuidle_state_usage
*state_usage
= &dev
->states_usage
[idx
];
371 cpuidle_set_statedata(state_usage
, cx
);
377 * omap3_idle_init - Init routine for OMAP3 idle
379 * Registers the OMAP3 specific cpuidle driver to the cpuidle
380 * framework with the valid set of states.
382 int __init
omap3_idle_init(void)
384 struct cpuidle_device
*dev
;
385 struct omap3_idle_statedata
*cx
;
387 mpu_pd
= pwrdm_lookup("mpu_pwrdm");
388 core_pd
= pwrdm_lookup("core_pwrdm");
389 per_pd
= pwrdm_lookup("per_pwrdm");
390 cam_pd
= pwrdm_lookup("cam_pwrdm");
393 dev
= &per_cpu(omap3_idle_dev
, smp_processor_id());
395 /* C1 . MPU WFI + Core active */
396 cx
= _fill_cstate_usage(dev
, 0);
397 cx
->mpu_state
= PWRDM_POWER_ON
;
398 cx
->core_state
= PWRDM_POWER_ON
;
400 /* C2 . MPU WFI + Core inactive */
401 cx
= _fill_cstate_usage(dev
, 1);
402 cx
->mpu_state
= PWRDM_POWER_ON
;
403 cx
->core_state
= PWRDM_POWER_ON
;
405 /* C3 . MPU CSWR + Core inactive */
406 cx
= _fill_cstate_usage(dev
, 2);
407 cx
->mpu_state
= PWRDM_POWER_RET
;
408 cx
->core_state
= PWRDM_POWER_ON
;
410 /* C4 . MPU OFF + Core inactive */
411 cx
= _fill_cstate_usage(dev
, 3);
412 cx
->mpu_state
= PWRDM_POWER_OFF
;
413 cx
->core_state
= PWRDM_POWER_ON
;
415 /* C5 . MPU RET + Core RET */
416 cx
= _fill_cstate_usage(dev
, 4);
417 cx
->mpu_state
= PWRDM_POWER_RET
;
418 cx
->core_state
= PWRDM_POWER_RET
;
420 /* C6 . MPU OFF + Core RET */
421 cx
= _fill_cstate_usage(dev
, 5);
422 cx
->mpu_state
= PWRDM_POWER_OFF
;
423 cx
->core_state
= PWRDM_POWER_RET
;
425 /* C7 . MPU OFF + Core OFF */
426 cx
= _fill_cstate_usage(dev
, 6);
427 cx
->mpu_state
= PWRDM_POWER_OFF
;
428 cx
->core_state
= PWRDM_POWER_OFF
;
430 cpuidle_register_driver(&omap3_idle_driver
);
432 if (cpuidle_register_device(dev
)) {
433 printk(KERN_ERR
"%s: CPUidle register device failed\n",
441 int __init
omap3_idle_init(void)
445 #endif /* CONFIG_CPU_IDLE */