arch/arm/mach-omap2/cpuidle34xx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/cpuidle34xx.c
   3  *
   4  * OMAP3 CPU IDLE Routines
   5  *
   6  * Copyright (C) 2008 Texas Instruments, Inc.
   7  * Rajendra Nayak <rnayak@ti.com>
   8  *
   9  * Copyright (C) 2007 Texas Instruments, Inc.
  10  * Karthik Dasu <karthik-dp@ti.com>
  11  *
  12  * Copyright (C) 2006 Nokia Corporation
  13  * Tony Lindgren <tony@atomide.com>
  14  *
  15  * Copyright (C) 2005 Texas Instruments, Inc.
  16  * Richard Woodruff <r-woodruff2@ti.com>
  17  *
  18  * Based on pm.c for omap2
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License version 2 as
  22  * published by the Free Software Foundation.
  23  */
  24
  25 #include <linux/sched.h>
  26 #include <linux/cpuidle.h>
  27 #include <linux/export.h>
  28 #include <linux/cpu_pm.h>
  29
  30 #include <plat/prcm.h>
  31 #include <plat/irqs.h>
  32 #include "powerdomain.h"
  33 #include "clockdomain.h"
  34
  35 #include "pm.h"
  36 #include "control.h"
  37 #include "common.h"
  38
  39 /* Mach specific information to be recorded in the C-state driver_data */
  40 struct omap3_idle_statedata {
  41         u32 mpu_state;
  42         u32 core_state;
  43 };
  44
  45 static struct omap3_idle_statedata omap3_idle_data[] = {
  46         {
  47                 .mpu_state = PWRDM_POWER_ON,
  48                 .core_state = PWRDM_POWER_ON,
  49         },
  50         {
  51                 .mpu_state = PWRDM_POWER_ON,
  52                 .core_state = PWRDM_POWER_ON,
  53         },
  54         {
  55                 .mpu_state = PWRDM_POWER_RET,
  56                 .core_state = PWRDM_POWER_ON,
  57         },
  58         {
  59                 .mpu_state = PWRDM_POWER_OFF,
  60                 .core_state = PWRDM_POWER_ON,
  61         },
  62         {
  63                 .mpu_state = PWRDM_POWER_RET,
  64                 .core_state = PWRDM_POWER_RET,
  65         },
  66         {
  67                 .mpu_state = PWRDM_POWER_OFF,
  68                 .core_state = PWRDM_POWER_RET,
  69         },
  70         {
  71                 .mpu_state = PWRDM_POWER_OFF,
  72                 .core_state = PWRDM_POWER_OFF,
  73         },
  74 };
  75
  76 static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
  77
  78 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
  79                                 struct clockdomain *clkdm)
  80 {
  81         clkdm_allow_idle(clkdm);
  82         return 0;
  83 }
  84
  85 static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
  86                                 struct clockdomain *clkdm)
  87 {
  88         clkdm_deny_idle(clkdm);
  89         return 0;
  90 }
  91
  92 static int __omap3_enter_idle(struct cpuidle_device *dev,
  93                                 struct cpuidle_driver *drv,
  94                                 int index)
  95 {
  96         struct omap3_idle_statedata *cx = &omap3_idle_data[index];
  97         u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
  98
  99         local_fiq_disable();
 100
 101         pwrdm_set_next_pwrst(mpu_pd, mpu_state);
 102         pwrdm_set_next_pwrst(core_pd, core_state);
 103
 104         if (omap_irq_pending() || need_resched())
 105                 goto return_sleep_time;
 106
 107         /* Deny idle for C1 */
 108         if (index == 0) {
 109                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
 110                 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
 111         }
 112
 113         /*
 114          * Call idle CPU PM enter notifier chain so that
 115          * VFP context is saved.
 116          */
 117         if (mpu_state == PWRDM_POWER_OFF)
 118                 cpu_pm_enter();
 119
 120         /* Execute ARM wfi */
 121         omap_sram_idle();
 122
 123         /*
 124          * Call idle CPU PM enter notifier chain to restore
 125          * VFP context.
 126          */
 127         if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
 128                 cpu_pm_exit();
 129
 130         /* Re-allow idle for C1 */
 131         if (index == 0) {
 132                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
 133                 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
 134         }
 135
 136 return_sleep_time:
 137
 138         local_fiq_enable();
 139
 140         return index;
 141 }
 142
 143 /**
 144  * omap3_enter_idle - Programs OMAP3 to enter the specified state
 145  * @dev: cpuidle device
 146  * @drv: cpuidle driver
 147  * @index: the index of state to be entered
 148  *
 149  * Called from the CPUidle framework to program the device to the
 150  * specified target state selected by the governor.
 151  */
 152 static inline int omap3_enter_idle(struct cpuidle_device *dev,
 153                                 struct cpuidle_driver *drv,
 154                                 int index)
 155 {
 156         return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
 157 }
 158
 159 /**
 160  * next_valid_state - Find next valid C-state
 161  * @dev: cpuidle device
 162  * @drv: cpuidle driver
 163  * @index: Index of currently selected c-state
 164  *
 165  * If the state corresponding to index is valid, index is returned back
 166  * to the caller. Else, this function searches for a lower c-state which is
 167  * still valid (as defined in omap3_power_states[]) and returns its index.
 168  *
 169  * A state is valid if the 'valid' field is enabled and
 170  * if it satisfies the enable_off_mode condition.
 171  */
 172 static int next_valid_state(struct cpuidle_device *dev,
 173                             struct cpuidle_driver *drv, int index)
 174 {
 175         struct omap3_idle_statedata *cx = &omap3_idle_data[index];
 176         u32 mpu_deepest_state = PWRDM_POWER_RET;
 177         u32 core_deepest_state = PWRDM_POWER_RET;
 178         int idx;
 179         int next_index = -1;
 180
 181         if (enable_off_mode) {
 182                 mpu_deepest_state = PWRDM_POWER_OFF;
 183                 /*
 184                  * Erratum i583: valable for ES rev < Es1.2 on 3630.
 185                  * CORE OFF mode is not supported in a stable form, restrict
 186                  * instead the CORE state to RET.
 187                  */
 188                 if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
 189                         core_deepest_state = PWRDM_POWER_OFF;
 190         }
 191
 192         /* Check if current state is valid */
 193         if ((cx->mpu_state >= mpu_deepest_state) &&
 194             (cx->core_state >= core_deepest_state))
 195                 return index;
 196
 197         /*
 198          * Drop to next valid state.
 199          * Start search from the next (lower) state.
 200          */
 201         for (idx = index - 1; idx >= 0; idx--) {
 202                 cx =  &omap3_idle_data[idx];
 203                 if ((cx->mpu_state >= mpu_deepest_state) &&
 204                     (cx->core_state >= core_deepest_state)) {
 205                         next_index = idx;
 206                         break;
 207                 }
 208         }
 209
 210         /*
 211          * C1 is always valid.
 212          * So, no need to check for 'next_index == -1' outside
 213          * this loop.
 214          */
 215
 216         return next_index;
 217 }
 218
 219 /**
 220  * omap3_enter_idle_bm - Checks for any bus activity
 221  * @dev: cpuidle device
 222  * @drv: cpuidle driver
 223  * @index: array index of target state to be programmed
 224  *
 225  * This function checks for any pending activity and then programs
 226  * the device to the specified or a safer state.
 227  */
 228 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 229                                 struct cpuidle_driver *drv,
 230                                int index)
 231 {
 232         int new_state_idx;
 233         u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
 234         struct omap3_idle_statedata *cx;
 235         int ret;
 236
 237         /*
 238          * Prevent idle completely if CAM is active.
 239          * CAM does not have wakeup capability in OMAP3.
 240          */
 241         cam_state = pwrdm_read_pwrst(cam_pd);
 242         if (cam_state == PWRDM_POWER_ON) {
 243                 new_state_idx = drv->safe_state_index;
 244                 goto select_state;
 245         }
 246
 247         /*
 248          * FIXME: we currently manage device-specific idle states
 249          *        for PER and CORE in combination with CPU-specific
 250          *        idle states.  This is wrong, and device-specific
 251          *        idle management needs to be separated out into
 252          *        its own code.
 253          */
 254
 255         /*
 256          * Prevent PER off if CORE is not in retention or off as this
 257          * would disable PER wakeups completely.
 258          */
 259         cx = &omap3_idle_data[index];
 260         core_next_state = cx->core_state;
 261         per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
 262         if ((per_next_state == PWRDM_POWER_OFF) &&
 263             (core_next_state > PWRDM_POWER_RET))
 264                 per_next_state = PWRDM_POWER_RET;
 265
 266         /* Are we changing PER target state? */
 267         if (per_next_state != per_saved_state)
 268                 pwrdm_set_next_pwrst(per_pd, per_next_state);
 269
 270         new_state_idx = next_valid_state(dev, drv, index);
 271
 272 select_state:
 273         ret = omap3_enter_idle(dev, drv, new_state_idx);
 274
 275         /* Restore original PER state if it was modified */
 276         if (per_next_state != per_saved_state)
 277                 pwrdm_set_next_pwrst(per_pd, per_saved_state);
 278
 279         return ret;
 280 }
 281
 282 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 283
 284 struct cpuidle_driver omap3_idle_driver = {
 285         .name =         "omap3_idle",
 286         .owner =        THIS_MODULE,
 287         .states = {
 288                 {
 289                         .enter            = omap3_enter_idle,
 290                         .exit_latency     = 2 + 2,
 291                         .target_residency = 5,
 292                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 293                         .name             = "C1",
 294                         .desc             = "MPU ON + CORE ON",
 295                 },
 296                 {
 297                         .enter            = omap3_enter_idle_bm,
 298                         .exit_latency     = 10 + 10,
 299                         .target_residency = 30,
 300                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 301                         .name             = "C2",
 302                         .desc             = "MPU ON + CORE ON",
 303                 },
 304                 {
 305                         .enter            = omap3_enter_idle_bm,
 306                         .exit_latency     = 50 + 50,
 307                         .target_residency = 300,
 308                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 309                         .name             = "C3",
 310                         .desc             = "MPU RET + CORE ON",
 311                 },
 312                 {
 313                         .enter            = omap3_enter_idle_bm,
 314                         .exit_latency     = 1500 + 1800,
 315                         .target_residency = 4000,
 316                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 317                         .name             = "C4",
 318                         .desc             = "MPU OFF + CORE ON",
 319                 },
 320                 {
 321                         .enter            = omap3_enter_idle_bm,
 322                         .exit_latency     = 2500 + 7500,
 323                         .target_residency = 12000,
 324                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 325                         .name             = "C5",
 326                         .desc             = "MPU RET + CORE RET",
 327                 },
 328                 {
 329                         .enter            = omap3_enter_idle_bm,
 330                         .exit_latency     = 3000 + 8500,
 331                         .target_residency = 15000,
 332                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 333                         .name             = "C6",
 334                         .desc             = "MPU OFF + CORE RET",
 335                 },
 336                 {
 337                         .enter            = omap3_enter_idle_bm,
 338                         .exit_latency     = 10000 + 30000,
 339                         .target_residency = 30000,
 340                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 341                         .name             = "C7",
 342                         .desc             = "MPU OFF + CORE OFF",
 343                 },
 344         },
 345         .state_count = ARRAY_SIZE(omap3_idle_data),
 346         .safe_state_index = 0,
 347 };
 348
 349 /**
 350  * omap3_idle_init - Init routine for OMAP3 idle
 351  *
 352  * Registers the OMAP3 specific cpuidle driver to the cpuidle
 353  * framework with the valid set of states.
 354  */
 355 int __init omap3_idle_init(void)
 356 {
 357         struct cpuidle_device *dev;
 358
 359         mpu_pd = pwrdm_lookup("mpu_pwrdm");
 360         core_pd = pwrdm_lookup("core_pwrdm");
 361         per_pd = pwrdm_lookup("per_pwrdm");
 362         cam_pd = pwrdm_lookup("cam_pwrdm");
 363
 364         if (!mpu_pd || !core_pd || !per_pd || !cam_pd)
 365                 return -ENODEV;
 366
 367         cpuidle_register_driver(&omap3_idle_driver);
 368
 369         dev = &per_cpu(omap3_idle_dev, smp_processor_id());
 370         dev->cpu = 0;
 371
 372         if (cpuidle_register_device(dev)) {
 373                 printk(KERN_ERR "%s: CPUidle register device failed\n",
 374                        __func__);
 375                 return -EIO;
 376         }
 377
 378         return 0;
 379 }