arch/arm/mach-omap2/cpuidle34xx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/cpuidle34xx.c
   3  *
   4  * OMAP3 CPU IDLE Routines
   5  *
   6  * Copyright (C) 2008 Texas Instruments, Inc.
   7  * Rajendra Nayak <rnayak@ti.com>
   8  *
   9  * Copyright (C) 2007 Texas Instruments, Inc.
  10  * Karthik Dasu <karthik-dp@ti.com>
  11  *
  12  * Copyright (C) 2006 Nokia Corporation
  13  * Tony Lindgren <tony@atomide.com>
  14  *
  15  * Copyright (C) 2005 Texas Instruments, Inc.
  16  * Richard Woodruff <r-woodruff2@ti.com>
  17  *
  18  * Based on pm.c for omap2
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License version 2 as
  22  * published by the Free Software Foundation.
  23  */
  24
  25 #include <linux/sched.h>
  26 #include <linux/cpuidle.h>
  27 #include <linux/export.h>
  28 #include <linux/cpu_pm.h>
  29
  30 #include "powerdomain.h"
  31 #include "clockdomain.h"
  32
  33 #include "pm.h"
  34 #include "control.h"
  35 #include "common.h"
  36
  37 /* Mach specific information to be recorded in the C-state driver_data */
  38 struct omap3_idle_statedata {
  39         u8 mpu_state;
  40         u8 core_state;
  41         u8 per_min_state;
  42         u8 flags;
  43 };
  44
  45 static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
  46
  47 /*
  48  * Possible flag bits for struct omap3_idle_statedata.flags:
  49  *
  50  * OMAP_CPUIDLE_CX_NO_CLKDM_IDLE: don't allow the MPU clockdomain to go
  51  *    inactive.  This in turn prevents the MPU DPLL from entering autoidle
  52  *    mode, so wakeup latency is greatly reduced, at the cost of additional
  53  *    energy consumption.  This also prevents the CORE clockdomain from
  54  *    entering idle.
  55  */
  56 #define OMAP_CPUIDLE_CX_NO_CLKDM_IDLE           BIT(0)
  57
  58 /*
  59  * Prevent PER OFF if CORE is not in RETention or OFF as this would
  60  * disable PER wakeups completely.
  61  */
  62 static struct omap3_idle_statedata omap3_idle_data[] = {
  63         {
  64                 .mpu_state = PWRDM_POWER_ON,
  65                 .core_state = PWRDM_POWER_ON,
  66                 /* In C1 do not allow PER state lower than CORE state */
  67                 .per_min_state = PWRDM_POWER_ON,
  68                 .flags = OMAP_CPUIDLE_CX_NO_CLKDM_IDLE,
  69         },
  70         {
  71                 .mpu_state = PWRDM_POWER_ON,
  72                 .core_state = PWRDM_POWER_ON,
  73                 .per_min_state = PWRDM_POWER_RET,
  74         },
  75         {
  76                 .mpu_state = PWRDM_POWER_RET,
  77                 .core_state = PWRDM_POWER_ON,
  78                 .per_min_state = PWRDM_POWER_RET,
  79         },
  80         {
  81                 .mpu_state = PWRDM_POWER_OFF,
  82                 .core_state = PWRDM_POWER_ON,
  83                 .per_min_state = PWRDM_POWER_RET,
  84         },
  85         {
  86                 .mpu_state = PWRDM_POWER_RET,
  87                 .core_state = PWRDM_POWER_RET,
  88                 .per_min_state = PWRDM_POWER_OFF,
  89         },
  90         {
  91                 .mpu_state = PWRDM_POWER_OFF,
  92                 .core_state = PWRDM_POWER_RET,
  93                 .per_min_state = PWRDM_POWER_OFF,
  94         },
  95         {
  96                 .mpu_state = PWRDM_POWER_OFF,
  97                 .core_state = PWRDM_POWER_OFF,
  98                 .per_min_state = PWRDM_POWER_OFF,
  99         },
 100 };
 101
 102 /* Private functions */
 103
 104 static int __omap3_enter_idle(struct cpuidle_device *dev,
 105                                 struct cpuidle_driver *drv,
 106                                 int index)
 107 {
 108         struct omap3_idle_statedata *cx = &omap3_idle_data[index];
 109
 110         if (omap_irq_pending() || need_resched())
 111                 goto return_sleep_time;
 112
 113         /* Deny idle for C1 */
 114         if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE) {
 115                 clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
 116         } else {
 117                 pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
 118                 pwrdm_set_next_pwrst(core_pd, cx->core_state);
 119         }
 120
 121         /*
 122          * Call idle CPU PM enter notifier chain so that
 123          * VFP context is saved.
 124          */
 125         if (cx->mpu_state == PWRDM_POWER_OFF)
 126                 cpu_pm_enter();
 127
 128         /* Execute ARM wfi */
 129         omap_sram_idle();
 130
 131         /*
 132          * Call idle CPU PM enter notifier chain to restore
 133          * VFP context.
 134          */
 135         if (cx->mpu_state == PWRDM_POWER_OFF &&
 136             pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
 137                 cpu_pm_exit();
 138
 139         /* Re-allow idle for C1 */
 140         if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE)
 141                 clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
 142
 143 return_sleep_time:
 144
 145         return index;
 146 }
 147
 148 /**
 149  * omap3_enter_idle - Programs OMAP3 to enter the specified state
 150  * @dev: cpuidle device
 151  * @drv: cpuidle driver
 152  * @index: the index of state to be entered
 153  *
 154  * Called from the CPUidle framework to program the device to the
 155  * specified target state selected by the governor.
 156  */
 157 static inline int omap3_enter_idle(struct cpuidle_device *dev,
 158                                 struct cpuidle_driver *drv,
 159                                 int index)
 160 {
 161         return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
 162 }
 163
 164 /**
 165  * next_valid_state - Find next valid C-state
 166  * @dev: cpuidle device
 167  * @drv: cpuidle driver
 168  * @index: Index of currently selected c-state
 169  *
 170  * If the state corresponding to index is valid, index is returned back
 171  * to the caller. Else, this function searches for a lower c-state which is
 172  * still valid (as defined in omap3_power_states[]) and returns its index.
 173  *
 174  * A state is valid if the 'valid' field is enabled and
 175  * if it satisfies the enable_off_mode condition.
 176  */
 177 static int next_valid_state(struct cpuidle_device *dev,
 178                             struct cpuidle_driver *drv, int index)
 179 {
 180         struct omap3_idle_statedata *cx = &omap3_idle_data[index];
 181         u32 mpu_deepest_state = PWRDM_POWER_RET;
 182         u32 core_deepest_state = PWRDM_POWER_RET;
 183         int idx;
 184         int next_index = 0; /* C1 is the default value */
 185
 186         if (enable_off_mode) {
 187                 mpu_deepest_state = PWRDM_POWER_OFF;
 188                 /*
 189                  * Erratum i583: valable for ES rev < Es1.2 on 3630.
 190                  * CORE OFF mode is not supported in a stable form, restrict
 191                  * instead the CORE state to RET.
 192                  */
 193                 if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
 194                         core_deepest_state = PWRDM_POWER_OFF;
 195         }
 196
 197         /* Check if current state is valid */
 198         if ((cx->mpu_state >= mpu_deepest_state) &&
 199             (cx->core_state >= core_deepest_state))
 200                 return index;
 201
 202         /*
 203          * Drop to next valid state.
 204          * Start search from the next (lower) state.
 205          */
 206         for (idx = index - 1; idx >= 0; idx--) {
 207                 cx = &omap3_idle_data[idx];
 208                 if ((cx->mpu_state >= mpu_deepest_state) &&
 209                     (cx->core_state >= core_deepest_state)) {
 210                         next_index = idx;
 211                         break;
 212                 }
 213         }
 214
 215         return next_index;
 216 }
 217
 218 /**
 219  * omap3_enter_idle_bm - Checks for any bus activity
 220  * @dev: cpuidle device
 221  * @drv: cpuidle driver
 222  * @index: array index of target state to be programmed
 223  *
 224  * This function checks for any pending activity and then programs
 225  * the device to the specified or a safer state.
 226  */
 227 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 228                                struct cpuidle_driver *drv,
 229                                int index)
 230 {
 231         int new_state_idx, ret;
 232         u8 per_next_state, per_saved_state;
 233         struct omap3_idle_statedata *cx;
 234
 235         /*
 236          * Use only C1 if CAM is active.
 237          * CAM does not have wakeup capability in OMAP3.
 238          */
 239         if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON)
 240                 new_state_idx = drv->safe_state_index;
 241         else
 242                 new_state_idx = next_valid_state(dev, drv, index);
 243
 244         /*
 245          * FIXME: we currently manage device-specific idle states
 246          *        for PER and CORE in combination with CPU-specific
 247          *        idle states.  This is wrong, and device-specific
 248          *        idle management needs to be separated out into
 249          *        its own code.
 250          */
 251
 252         /* Program PER state */
 253         cx = &omap3_idle_data[new_state_idx];
 254
 255         per_next_state = pwrdm_read_next_pwrst(per_pd);
 256         per_saved_state = per_next_state;
 257         if (per_next_state < cx->per_min_state) {
 258                 per_next_state = cx->per_min_state;
 259                 pwrdm_set_next_pwrst(per_pd, per_next_state);
 260         }
 261
 262         ret = omap3_enter_idle(dev, drv, new_state_idx);
 263
 264         /* Restore original PER state if it was modified */
 265         if (per_next_state != per_saved_state)
 266                 pwrdm_set_next_pwrst(per_pd, per_saved_state);
 267
 268         return ret;
 269 }
 270
 271 static DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 272
 273 static struct cpuidle_driver omap3_idle_driver = {
 274         .name =         "omap3_idle",
 275         .owner =        THIS_MODULE,
 276         .states = {
 277                 {
 278                         .enter            = omap3_enter_idle_bm,
 279                         .exit_latency     = 2 + 2,
 280                         .target_residency = 5,
 281                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 282                         .name             = "C1",
 283                         .desc             = "MPU ON + CORE ON",
 284                 },
 285                 {
 286                         .enter            = omap3_enter_idle_bm,
 287                         .exit_latency     = 10 + 10,
 288                         .target_residency = 30,
 289                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 290                         .name             = "C2",
 291                         .desc             = "MPU ON + CORE ON",
 292                 },
 293                 {
 294                         .enter            = omap3_enter_idle_bm,
 295                         .exit_latency     = 50 + 50,
 296                         .target_residency = 300,
 297                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 298                         .name             = "C3",
 299                         .desc             = "MPU RET + CORE ON",
 300                 },
 301                 {
 302                         .enter            = omap3_enter_idle_bm,
 303                         .exit_latency     = 1500 + 1800,
 304                         .target_residency = 4000,
 305                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 306                         .name             = "C4",
 307                         .desc             = "MPU OFF + CORE ON",
 308                 },
 309                 {
 310                         .enter            = omap3_enter_idle_bm,
 311                         .exit_latency     = 2500 + 7500,
 312                         .target_residency = 12000,
 313                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 314                         .name             = "C5",
 315                         .desc             = "MPU RET + CORE RET",
 316                 },
 317                 {
 318                         .enter            = omap3_enter_idle_bm,
 319                         .exit_latency     = 3000 + 8500,
 320                         .target_residency = 15000,
 321                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 322                         .name             = "C6",
 323                         .desc             = "MPU OFF + CORE RET",
 324                 },
 325                 {
 326                         .enter            = omap3_enter_idle_bm,
 327                         .exit_latency     = 10000 + 30000,
 328                         .target_residency = 30000,
 329                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 330                         .name             = "C7",
 331                         .desc             = "MPU OFF + CORE OFF",
 332                 },
 333         },
 334         .state_count = ARRAY_SIZE(omap3_idle_data),
 335         .safe_state_index = 0,
 336 };
 337
 338 /* Public functions */
 339
 340 /**
 341  * omap3_idle_init - Init routine for OMAP3 idle
 342  *
 343  * Registers the OMAP3 specific cpuidle driver to the cpuidle
 344  * framework with the valid set of states.
 345  */
 346 int __init omap3_idle_init(void)
 347 {
 348         struct cpuidle_device *dev;
 349
 350         mpu_pd = pwrdm_lookup("mpu_pwrdm");
 351         core_pd = pwrdm_lookup("core_pwrdm");
 352         per_pd = pwrdm_lookup("per_pwrdm");
 353         cam_pd = pwrdm_lookup("cam_pwrdm");
 354
 355         if (!mpu_pd || !core_pd || !per_pd || !cam_pd)
 356                 return -ENODEV;
 357
 358         cpuidle_register_driver(&omap3_idle_driver);
 359
 360         dev = &per_cpu(omap3_idle_dev, smp_processor_id());
 361         dev->cpu = 0;
 362
 363         if (cpuidle_register_device(dev)) {
 364                 printk(KERN_ERR "%s: CPUidle register device failed\n",
 365                        __func__);
 366                 return -EIO;
 367         }
 368
 369         return 0;
 370 }