2 * linux/arch/arm/mach-omap2/cpuidle34xx.c
4 * OMAP3 CPU IDLE Routines
6 * Copyright (C) 2008 Texas Instruments, Inc.
7 * Rajendra Nayak <rnayak@ti.com>
9 * Copyright (C) 2007 Texas Instruments, Inc.
10 * Karthik Dasu <karthik-dp@ti.com>
12 * Copyright (C) 2006 Nokia Corporation
13 * Tony Lindgren <tony@atomide.com>
15 * Copyright (C) 2005 Texas Instruments, Inc.
16 * Richard Woodruff <r-woodruff2@ti.com>
18 * Based on pm.c for omap2
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License version 2 as
22 * published by the Free Software Foundation.
25 #include <linux/sched.h>
26 #include <linux/cpuidle.h>
27 #include <linux/export.h>
28 #include <linux/cpu_pm.h>
30 #include "powerdomain.h"
31 #include "clockdomain.h"
37 /* Mach specific information to be recorded in the C-state driver_data */
38 struct omap3_idle_statedata
{
43 static struct omap3_idle_statedata omap3_idle_data
[] = {
45 .mpu_state
= PWRDM_POWER_ON
,
46 .core_state
= PWRDM_POWER_ON
,
49 .mpu_state
= PWRDM_POWER_ON
,
50 .core_state
= PWRDM_POWER_ON
,
53 .mpu_state
= PWRDM_POWER_RET
,
54 .core_state
= PWRDM_POWER_ON
,
57 .mpu_state
= PWRDM_POWER_OFF
,
58 .core_state
= PWRDM_POWER_ON
,
61 .mpu_state
= PWRDM_POWER_RET
,
62 .core_state
= PWRDM_POWER_RET
,
65 .mpu_state
= PWRDM_POWER_OFF
,
66 .core_state
= PWRDM_POWER_RET
,
69 .mpu_state
= PWRDM_POWER_OFF
,
70 .core_state
= PWRDM_POWER_OFF
,
74 static struct powerdomain
*mpu_pd
, *core_pd
, *per_pd
, *cam_pd
;
76 static int __omap3_enter_idle(struct cpuidle_device
*dev
,
77 struct cpuidle_driver
*drv
,
80 struct omap3_idle_statedata
*cx
= &omap3_idle_data
[index
];
81 u32 mpu_state
= cx
->mpu_state
, core_state
= cx
->core_state
;
85 pwrdm_set_next_pwrst(mpu_pd
, mpu_state
);
86 pwrdm_set_next_pwrst(core_pd
, core_state
);
88 if (omap_irq_pending() || need_resched())
89 goto return_sleep_time
;
91 /* Deny idle for C1 */
93 clkdm_deny_idle(mpu_pd
->pwrdm_clkdms
[0]);
94 clkdm_deny_idle(core_pd
->pwrdm_clkdms
[0]);
98 * Call idle CPU PM enter notifier chain so that
99 * VFP context is saved.
101 if (mpu_state
== PWRDM_POWER_OFF
)
104 /* Execute ARM wfi */
108 * Call idle CPU PM enter notifier chain to restore
111 if (pwrdm_read_prev_pwrst(mpu_pd
) == PWRDM_POWER_OFF
)
114 /* Re-allow idle for C1 */
116 clkdm_allow_idle(mpu_pd
->pwrdm_clkdms
[0]);
117 clkdm_allow_idle(core_pd
->pwrdm_clkdms
[0]);
128 * omap3_enter_idle - Programs OMAP3 to enter the specified state
129 * @dev: cpuidle device
130 * @drv: cpuidle driver
131 * @index: the index of state to be entered
133 * Called from the CPUidle framework to program the device to the
134 * specified target state selected by the governor.
136 static inline int omap3_enter_idle(struct cpuidle_device
*dev
,
137 struct cpuidle_driver
*drv
,
140 return cpuidle_wrap_enter(dev
, drv
, index
, __omap3_enter_idle
);
144 * next_valid_state - Find next valid C-state
145 * @dev: cpuidle device
146 * @drv: cpuidle driver
147 * @index: Index of currently selected c-state
149 * If the state corresponding to index is valid, index is returned back
150 * to the caller. Else, this function searches for a lower c-state which is
151 * still valid (as defined in omap3_power_states[]) and returns its index.
153 * A state is valid if the 'valid' field is enabled and
154 * if it satisfies the enable_off_mode condition.
156 static int next_valid_state(struct cpuidle_device
*dev
,
157 struct cpuidle_driver
*drv
, int index
)
159 struct omap3_idle_statedata
*cx
= &omap3_idle_data
[index
];
160 u32 mpu_deepest_state
= PWRDM_POWER_RET
;
161 u32 core_deepest_state
= PWRDM_POWER_RET
;
163 int next_index
= 0; /* C1 is the default value */
165 if (enable_off_mode
) {
166 mpu_deepest_state
= PWRDM_POWER_OFF
;
168 * Erratum i583: valable for ES rev < Es1.2 on 3630.
169 * CORE OFF mode is not supported in a stable form, restrict
170 * instead the CORE state to RET.
172 if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583
))
173 core_deepest_state
= PWRDM_POWER_OFF
;
176 /* Check if current state is valid */
177 if ((cx
->mpu_state
>= mpu_deepest_state
) &&
178 (cx
->core_state
>= core_deepest_state
))
182 * Drop to next valid state.
183 * Start search from the next (lower) state.
185 for (idx
= index
- 1; idx
>= 0; idx
--) {
186 cx
= &omap3_idle_data
[idx
];
187 if ((cx
->mpu_state
>= mpu_deepest_state
) &&
188 (cx
->core_state
>= core_deepest_state
)) {
198 * omap3_enter_idle_bm - Checks for any bus activity
199 * @dev: cpuidle device
200 * @drv: cpuidle driver
201 * @index: array index of target state to be programmed
203 * This function checks for any pending activity and then programs
204 * the device to the specified or a safer state.
206 static int omap3_enter_idle_bm(struct cpuidle_device
*dev
,
207 struct cpuidle_driver
*drv
,
211 u32 core_next_state
, per_next_state
= 0, per_saved_state
= 0;
212 struct omap3_idle_statedata
*cx
;
216 * Use only C1 if CAM is active.
217 * CAM does not have wakeup capability in OMAP3.
219 if (pwrdm_read_pwrst(cam_pd
) == PWRDM_POWER_ON
)
220 new_state_idx
= drv
->safe_state_index
;
222 new_state_idx
= next_valid_state(dev
, drv
, index
);
225 * FIXME: we currently manage device-specific idle states
226 * for PER and CORE in combination with CPU-specific
227 * idle states. This is wrong, and device-specific
228 * idle management needs to be separated out into
232 /* Program PER state */
233 cx
= &omap3_idle_data
[new_state_idx
];
234 core_next_state
= cx
->core_state
;
235 per_next_state
= per_saved_state
= pwrdm_read_next_pwrst(per_pd
);
236 if (new_state_idx
== 0) {
237 /* In C1 do not allow PER state lower than CORE state */
238 if (per_next_state
< core_next_state
)
239 per_next_state
= core_next_state
;
242 * Prevent PER OFF if CORE is not in RETention or OFF as this
243 * would disable PER wakeups completely.
245 if ((per_next_state
== PWRDM_POWER_OFF
) &&
246 (core_next_state
> PWRDM_POWER_RET
))
247 per_next_state
= PWRDM_POWER_RET
;
250 /* Are we changing PER target state? */
251 if (per_next_state
!= per_saved_state
)
252 pwrdm_set_next_pwrst(per_pd
, per_next_state
);
254 ret
= omap3_enter_idle(dev
, drv
, new_state_idx
);
256 /* Restore original PER state if it was modified */
257 if (per_next_state
!= per_saved_state
)
258 pwrdm_set_next_pwrst(per_pd
, per_saved_state
);
263 DEFINE_PER_CPU(struct cpuidle_device
, omap3_idle_dev
);
265 struct cpuidle_driver omap3_idle_driver
= {
266 .name
= "omap3_idle",
267 .owner
= THIS_MODULE
,
270 .enter
= omap3_enter_idle_bm
,
271 .exit_latency
= 2 + 2,
272 .target_residency
= 5,
273 .flags
= CPUIDLE_FLAG_TIME_VALID
,
275 .desc
= "MPU ON + CORE ON",
278 .enter
= omap3_enter_idle_bm
,
279 .exit_latency
= 10 + 10,
280 .target_residency
= 30,
281 .flags
= CPUIDLE_FLAG_TIME_VALID
,
283 .desc
= "MPU ON + CORE ON",
286 .enter
= omap3_enter_idle_bm
,
287 .exit_latency
= 50 + 50,
288 .target_residency
= 300,
289 .flags
= CPUIDLE_FLAG_TIME_VALID
,
291 .desc
= "MPU RET + CORE ON",
294 .enter
= omap3_enter_idle_bm
,
295 .exit_latency
= 1500 + 1800,
296 .target_residency
= 4000,
297 .flags
= CPUIDLE_FLAG_TIME_VALID
,
299 .desc
= "MPU OFF + CORE ON",
302 .enter
= omap3_enter_idle_bm
,
303 .exit_latency
= 2500 + 7500,
304 .target_residency
= 12000,
305 .flags
= CPUIDLE_FLAG_TIME_VALID
,
307 .desc
= "MPU RET + CORE RET",
310 .enter
= omap3_enter_idle_bm
,
311 .exit_latency
= 3000 + 8500,
312 .target_residency
= 15000,
313 .flags
= CPUIDLE_FLAG_TIME_VALID
,
315 .desc
= "MPU OFF + CORE RET",
318 .enter
= omap3_enter_idle_bm
,
319 .exit_latency
= 10000 + 30000,
320 .target_residency
= 30000,
321 .flags
= CPUIDLE_FLAG_TIME_VALID
,
323 .desc
= "MPU OFF + CORE OFF",
326 .state_count
= ARRAY_SIZE(omap3_idle_data
),
327 .safe_state_index
= 0,
331 * omap3_idle_init - Init routine for OMAP3 idle
333 * Registers the OMAP3 specific cpuidle driver to the cpuidle
334 * framework with the valid set of states.
336 int __init
omap3_idle_init(void)
338 struct cpuidle_device
*dev
;
340 mpu_pd
= pwrdm_lookup("mpu_pwrdm");
341 core_pd
= pwrdm_lookup("core_pwrdm");
342 per_pd
= pwrdm_lookup("per_pwrdm");
343 cam_pd
= pwrdm_lookup("cam_pwrdm");
345 if (!mpu_pd
|| !core_pd
|| !per_pd
|| !cam_pd
)
348 cpuidle_register_driver(&omap3_idle_driver
);
350 dev
= &per_cpu(omap3_idle_dev
, smp_processor_id());
353 if (cpuidle_register_device(dev
)) {
354 printk(KERN_ERR
"%s: CPUidle register device failed\n",