2 * OMAP4+ CPU idle Routines
4 * Copyright (C) 2011-2013 Texas Instruments, Inc.
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Rajendra Nayak <rnayak@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/sched.h>
14 #include <linux/cpuidle.h>
15 #include <linux/cpu_pm.h>
16 #include <linux/export.h>
18 #include <asm/proc-fns.h>
23 #include "clockdomain.h"
25 /* Machine specific information */
26 struct idle_statedata
{
32 static struct idle_statedata omap4_idle_data
[] = {
34 .cpu_state
= PWRDM_POWER_ON
,
35 .mpu_state
= PWRDM_POWER_ON
,
36 .mpu_logic_state
= PWRDM_POWER_RET
,
39 .cpu_state
= PWRDM_POWER_OFF
,
40 .mpu_state
= PWRDM_POWER_RET
,
41 .mpu_logic_state
= PWRDM_POWER_RET
,
44 .cpu_state
= PWRDM_POWER_OFF
,
45 .mpu_state
= PWRDM_POWER_RET
,
46 .mpu_logic_state
= PWRDM_POWER_OFF
,
50 static struct powerdomain
*mpu_pd
, *cpu_pd
[NR_CPUS
];
51 static struct clockdomain
*cpu_clkdm
[NR_CPUS
];
53 static atomic_t abort_barrier
;
54 static bool cpu_done
[NR_CPUS
];
55 static struct idle_statedata
*state_ptr
= &omap4_idle_data
[0];
57 /* Private functions */
60 * omap_enter_idle_[simple/coupled] - OMAP4PLUS cpuidle entry functions
61 * @dev: cpuidle device
62 * @drv: cpuidle driver
63 * @index: the index of state to be entered
65 * Called from the CPUidle framework to program the device to the
66 * specified low power state selected by the governor.
67 * Returns the amount of time spent in the low power state.
69 static int omap_enter_idle_simple(struct cpuidle_device
*dev
,
70 struct cpuidle_driver
*drv
,
80 static int omap_enter_idle_coupled(struct cpuidle_device
*dev
,
81 struct cpuidle_driver
*drv
,
84 struct idle_statedata
*cx
= state_ptr
+ index
;
89 * CPU0 has to wait and stay ON until CPU1 is OFF state.
90 * This is necessary to honour hardware recommondation
91 * of triggeing all the possible low power modes once CPU1 is
92 * out of coherency and in OFF mode.
94 if (dev
->cpu
== 0 && cpumask_test_cpu(1, cpu_online_mask
)) {
95 while (pwrdm_read_pwrst(cpu_pd
[1]) != PWRDM_POWER_OFF
) {
99 * CPU1 could have already entered & exited idle
100 * without hitting off because of a wakeup
101 * or a failed attempt to hit off mode. Check for
102 * that here, otherwise we could spin forever
103 * waiting for CPU1 off.
112 * Call idle CPU PM enter notifier chain so that
113 * VFP and per CPU interrupt context is saved.
118 pwrdm_set_logic_retst(mpu_pd
, cx
->mpu_logic_state
);
119 omap_set_pwrdm_state(mpu_pd
, cx
->mpu_state
);
122 * Call idle CPU cluster PM enter notifier chain
123 * to save GIC and wakeupgen context.
125 if ((cx
->mpu_state
== PWRDM_POWER_RET
) &&
126 (cx
->mpu_logic_state
== PWRDM_POWER_OFF
))
127 cpu_cluster_pm_enter();
130 omap4_enter_lowpower(dev
->cpu
, cx
->cpu_state
);
131 cpu_done
[dev
->cpu
] = true;
133 /* Wakeup CPU1 only if it is not offlined */
134 if (dev
->cpu
== 0 && cpumask_test_cpu(1, cpu_online_mask
)) {
135 clkdm_wakeup(cpu_clkdm
[1]);
136 clkdm_allow_idle(cpu_clkdm
[1]);
140 * Call idle CPU PM exit notifier chain to restore
141 * VFP and per CPU IRQ context.
146 * Call idle CPU cluster PM exit notifier chain
147 * to restore GIC and wakeupgen context.
149 if ((cx
->mpu_state
== PWRDM_POWER_RET
) &&
150 (cx
->mpu_logic_state
== PWRDM_POWER_OFF
))
151 cpu_cluster_pm_exit();
154 cpuidle_coupled_parallel_barrier(dev
, &abort_barrier
);
155 cpu_done
[dev
->cpu
] = false;
162 static DEFINE_PER_CPU(struct cpuidle_device
, omap_idle_dev
);
164 static struct cpuidle_driver omap4_idle_driver
= {
165 .name
= "omap4_idle",
166 .owner
= THIS_MODULE
,
169 /* C1 - CPU0 ON + CPU1 ON + MPU ON */
170 .exit_latency
= 2 + 2,
171 .target_residency
= 5,
172 .flags
= CPUIDLE_FLAG_TIME_VALID
,
173 .enter
= omap_enter_idle_simple
,
175 .desc
= "CPUx ON, MPUSS ON"
178 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
179 .exit_latency
= 328 + 440,
180 .target_residency
= 960,
181 .flags
= CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_COUPLED
|
182 CPUIDLE_FLAG_TIMER_STOP
,
183 .enter
= omap_enter_idle_coupled
,
185 .desc
= "CPUx OFF, MPUSS CSWR",
188 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
189 .exit_latency
= 460 + 518,
190 .target_residency
= 1100,
191 .flags
= CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_COUPLED
|
192 CPUIDLE_FLAG_TIMER_STOP
,
193 .enter
= omap_enter_idle_coupled
,
195 .desc
= "CPUx OFF, MPUSS OSWR",
198 .state_count
= ARRAY_SIZE(omap4_idle_data
),
199 .safe_state_index
= 0,
202 /* Public functions */
205 * omap4_idle_init - Init routine for OMAP4+ idle
207 * Registers the OMAP4+ specific cpuidle driver to the cpuidle
208 * framework with the valid set of states.
210 int __init
omap4_idle_init(void)
212 struct cpuidle_device
*dev
;
213 unsigned int cpu_id
= 0;
215 mpu_pd
= pwrdm_lookup("mpu_pwrdm");
216 cpu_pd
[0] = pwrdm_lookup("cpu0_pwrdm");
217 cpu_pd
[1] = pwrdm_lookup("cpu1_pwrdm");
218 if ((!mpu_pd
) || (!cpu_pd
[0]) || (!cpu_pd
[1]))
221 cpu_clkdm
[0] = clkdm_lookup("mpu0_clkdm");
222 cpu_clkdm
[1] = clkdm_lookup("mpu1_clkdm");
223 if (!cpu_clkdm
[0] || !cpu_clkdm
[1])
226 if (cpuidle_register_driver(&omap4_idle_driver
)) {
227 pr_err("%s: CPUidle driver register failed\n", __func__
);
231 for_each_cpu(cpu_id
, cpu_online_mask
) {
232 dev
= &per_cpu(omap_idle_dev
, cpu_id
);
234 #ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
235 dev
->coupled_cpus
= *cpu_online_mask
;
237 if (cpuidle_register_device(dev
)) {
238 pr_err("%s: CPUidle register failed\n", __func__
);
239 cpuidle_unregister_driver(&omap4_idle_driver
);