2 * OMAP4 CPU idle Routines
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Rajendra Nayak <rnayak@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/sched.h>
14 #include <linux/cpuidle.h>
15 #include <linux/cpu_pm.h>
16 #include <linux/export.h>
17 #include <linux/clockchips.h>
19 #include <asm/proc-fns.h>
24 #include "clockdomain.h"
26 /* Machine specific information */
27 struct omap4_idle_statedata
{
33 static struct omap4_idle_statedata omap4_idle_data
[] = {
35 .cpu_state
= PWRDM_POWER_ON
,
36 .mpu_state
= PWRDM_POWER_ON
,
37 .mpu_logic_state
= PWRDM_POWER_RET
,
40 .cpu_state
= PWRDM_POWER_OFF
,
41 .mpu_state
= PWRDM_POWER_RET
,
42 .mpu_logic_state
= PWRDM_POWER_RET
,
45 .cpu_state
= PWRDM_POWER_OFF
,
46 .mpu_state
= PWRDM_POWER_RET
,
47 .mpu_logic_state
= PWRDM_POWER_OFF
,
51 static struct powerdomain
*mpu_pd
, *cpu_pd
[NR_CPUS
];
52 static struct clockdomain
*cpu_clkdm
[NR_CPUS
];
54 static atomic_t abort_barrier
;
55 static bool cpu_done
[NR_CPUS
];
57 /* Private functions */
60 * omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions
61 * @dev: cpuidle device
62 * @drv: cpuidle driver
63 * @index: the index of state to be entered
65 * Called from the CPUidle framework to program the device to the
66 * specified low power state selected by the governor.
67 * Returns the amount of time spent in the low power state.
69 static int omap4_enter_idle_simple(struct cpuidle_device
*dev
,
70 struct cpuidle_driver
*drv
,
77 static int omap4_enter_idle_coupled(struct cpuidle_device
*dev
,
78 struct cpuidle_driver
*drv
,
81 struct omap4_idle_statedata
*cx
= &omap4_idle_data
[index
];
82 int cpu_id
= smp_processor_id();
85 * CPU0 has to wait and stay ON until CPU1 is OFF state.
86 * This is necessary to honour hardware recommondation
87 * of triggeing all the possible low power modes once CPU1 is
88 * out of coherency and in OFF mode.
90 if (dev
->cpu
== 0 && cpumask_test_cpu(1, cpu_online_mask
)) {
91 while (pwrdm_read_pwrst(cpu_pd
[1]) != PWRDM_POWER_OFF
) {
95 * CPU1 could have already entered & exited idle
96 * without hitting off because of a wakeup
97 * or a failed attempt to hit off mode. Check for
98 * that here, otherwise we could spin forever
99 * waiting for CPU1 off.
107 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER
, &cpu_id
);
110 * Call idle CPU PM enter notifier chain so that
111 * VFP and per CPU interrupt context is saved.
116 pwrdm_set_logic_retst(mpu_pd
, cx
->mpu_logic_state
);
117 omap_set_pwrdm_state(mpu_pd
, cx
->mpu_state
);
120 * Call idle CPU cluster PM enter notifier chain
121 * to save GIC and wakeupgen context.
123 if ((cx
->mpu_state
== PWRDM_POWER_RET
) &&
124 (cx
->mpu_logic_state
== PWRDM_POWER_OFF
))
125 cpu_cluster_pm_enter();
128 omap4_enter_lowpower(dev
->cpu
, cx
->cpu_state
);
129 cpu_done
[dev
->cpu
] = true;
131 /* Wakeup CPU1 only if it is not offlined */
132 if (dev
->cpu
== 0 && cpumask_test_cpu(1, cpu_online_mask
)) {
133 clkdm_wakeup(cpu_clkdm
[1]);
134 omap_set_pwrdm_state(cpu_pd
[1], PWRDM_POWER_ON
);
135 clkdm_allow_idle(cpu_clkdm
[1]);
139 * Call idle CPU PM exit notifier chain to restore
140 * VFP and per CPU IRQ context.
145 * Call idle CPU cluster PM exit notifier chain
146 * to restore GIC and wakeupgen context.
148 if (omap4_mpuss_read_prev_context_state())
149 cpu_cluster_pm_exit();
151 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT
, &cpu_id
);
154 cpuidle_coupled_parallel_barrier(dev
, &abort_barrier
);
155 cpu_done
[dev
->cpu
] = false;
161 * For each cpu, setup the broadcast timer because local timers
162 * stops for the states above C1.
164 static void omap_setup_broadcast_timer(void *arg
)
166 int cpu
= smp_processor_id();
167 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON
, &cpu
);
170 static DEFINE_PER_CPU(struct cpuidle_device
, omap4_idle_dev
);
172 static struct cpuidle_driver omap4_idle_driver
= {
173 .name
= "omap4_idle",
174 .owner
= THIS_MODULE
,
175 .en_core_tk_irqen
= 1,
178 /* C1 - CPU0 ON + CPU1 ON + MPU ON */
179 .exit_latency
= 2 + 2,
180 .target_residency
= 5,
181 .flags
= CPUIDLE_FLAG_TIME_VALID
,
182 .enter
= omap4_enter_idle_simple
,
187 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
188 .exit_latency
= 328 + 440,
189 .target_residency
= 960,
190 .flags
= CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_COUPLED
,
191 .enter
= omap4_enter_idle_coupled
,
193 .desc
= "MPUSS CSWR",
196 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
197 .exit_latency
= 460 + 518,
198 .target_residency
= 1100,
199 .flags
= CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_COUPLED
,
200 .enter
= omap4_enter_idle_coupled
,
202 .desc
= "MPUSS OSWR",
205 .state_count
= ARRAY_SIZE(omap4_idle_data
),
206 .safe_state_index
= 0,
209 /* Public functions */
212 * omap4_idle_init - Init routine for OMAP4 idle
214 * Registers the OMAP4 specific cpuidle driver to the cpuidle
215 * framework with the valid set of states.
217 int __init
omap4_idle_init(void)
219 struct cpuidle_device
*dev
;
220 unsigned int cpu_id
= 0;
222 mpu_pd
= pwrdm_lookup("mpu_pwrdm");
223 cpu_pd
[0] = pwrdm_lookup("cpu0_pwrdm");
224 cpu_pd
[1] = pwrdm_lookup("cpu1_pwrdm");
225 if ((!mpu_pd
) || (!cpu_pd
[0]) || (!cpu_pd
[1]))
228 cpu_clkdm
[0] = clkdm_lookup("mpu0_clkdm");
229 cpu_clkdm
[1] = clkdm_lookup("mpu1_clkdm");
230 if (!cpu_clkdm
[0] || !cpu_clkdm
[1])
233 /* Configure the broadcast timer on each cpu */
234 on_each_cpu(omap_setup_broadcast_timer
, NULL
, 1);
236 for_each_cpu(cpu_id
, cpu_online_mask
) {
237 dev
= &per_cpu(omap4_idle_dev
, cpu_id
);
239 #ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
240 dev
->coupled_cpus
= *cpu_online_mask
;
242 cpuidle_register_driver(&omap4_idle_driver
);
244 if (cpuidle_register_device(dev
)) {
245 pr_err("%s: CPUidle register failed\n", __func__
);