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Merge branch 'devel-stable' into devel
[deliverable/linux.git] / arch / arm / mach-omap2 / devices.c
1 /*
2 * linux/arch/arm/mach-omap2/devices.c
3 *
4 * OMAP2 platform device setup/initialization
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/io.h>
17 #include <linux/clk.h>
18
19 #include <mach/hardware.h>
20 #include <mach/irqs.h>
21 #include <asm/mach-types.h>
22 #include <asm/mach/map.h>
23 #include <asm/pmu.h>
24
25 #include <plat/control.h>
26 #include <plat/tc.h>
27 #include <plat/board.h>
28 #include <plat/mux.h>
29 #include <mach/gpio.h>
30 #include <plat/mmc.h>
31
32 #include "mux.h"
33
34 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
35
36 static struct resource cam_resources[] = {
37 {
38 .start = OMAP24XX_CAMERA_BASE,
39 .end = OMAP24XX_CAMERA_BASE + 0xfff,
40 .flags = IORESOURCE_MEM,
41 },
42 {
43 .start = INT_24XX_CAM_IRQ,
44 .flags = IORESOURCE_IRQ,
45 }
46 };
47
48 static struct platform_device omap_cam_device = {
49 .name = "omap24xxcam",
50 .id = -1,
51 .num_resources = ARRAY_SIZE(cam_resources),
52 .resource = cam_resources,
53 };
54
55 static inline void omap_init_camera(void)
56 {
57 platform_device_register(&omap_cam_device);
58 }
59
60 #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
61
62 static struct resource omap3isp_resources[] = {
63 {
64 .start = OMAP3430_ISP_BASE,
65 .end = OMAP3430_ISP_END,
66 .flags = IORESOURCE_MEM,
67 },
68 {
69 .start = OMAP3430_ISP_CBUFF_BASE,
70 .end = OMAP3430_ISP_CBUFF_END,
71 .flags = IORESOURCE_MEM,
72 },
73 {
74 .start = OMAP3430_ISP_CCP2_BASE,
75 .end = OMAP3430_ISP_CCP2_END,
76 .flags = IORESOURCE_MEM,
77 },
78 {
79 .start = OMAP3430_ISP_CCDC_BASE,
80 .end = OMAP3430_ISP_CCDC_END,
81 .flags = IORESOURCE_MEM,
82 },
83 {
84 .start = OMAP3430_ISP_HIST_BASE,
85 .end = OMAP3430_ISP_HIST_END,
86 .flags = IORESOURCE_MEM,
87 },
88 {
89 .start = OMAP3430_ISP_H3A_BASE,
90 .end = OMAP3430_ISP_H3A_END,
91 .flags = IORESOURCE_MEM,
92 },
93 {
94 .start = OMAP3430_ISP_PREV_BASE,
95 .end = OMAP3430_ISP_PREV_END,
96 .flags = IORESOURCE_MEM,
97 },
98 {
99 .start = OMAP3430_ISP_RESZ_BASE,
100 .end = OMAP3430_ISP_RESZ_END,
101 .flags = IORESOURCE_MEM,
102 },
103 {
104 .start = OMAP3430_ISP_SBL_BASE,
105 .end = OMAP3430_ISP_SBL_END,
106 .flags = IORESOURCE_MEM,
107 },
108 {
109 .start = OMAP3430_ISP_CSI2A_BASE,
110 .end = OMAP3430_ISP_CSI2A_END,
111 .flags = IORESOURCE_MEM,
112 },
113 {
114 .start = OMAP3430_ISP_CSI2PHY_BASE,
115 .end = OMAP3430_ISP_CSI2PHY_END,
116 .flags = IORESOURCE_MEM,
117 },
118 {
119 .start = INT_34XX_CAM_IRQ,
120 .flags = IORESOURCE_IRQ,
121 }
122 };
123
124 static struct platform_device omap3isp_device = {
125 .name = "omap3isp",
126 .id = -1,
127 .num_resources = ARRAY_SIZE(omap3isp_resources),
128 .resource = omap3isp_resources,
129 };
130
131 static inline void omap_init_camera(void)
132 {
133 platform_device_register(&omap3isp_device);
134 }
135 #else
136 static inline void omap_init_camera(void)
137 {
138 }
139 #endif
140
141 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
142
143 #define MBOX_REG_SIZE 0x120
144
145 #ifdef CONFIG_ARCH_OMAP2
146 static struct resource omap2_mbox_resources[] = {
147 {
148 .start = OMAP24XX_MAILBOX_BASE,
149 .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
150 .flags = IORESOURCE_MEM,
151 },
152 {
153 .start = INT_24XX_MAIL_U0_MPU,
154 .flags = IORESOURCE_IRQ,
155 },
156 {
157 .start = INT_24XX_MAIL_U3_MPU,
158 .flags = IORESOURCE_IRQ,
159 },
160 };
161 static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
162 #else
163 #define omap2_mbox_resources NULL
164 #define omap2_mbox_resources_sz 0
165 #endif
166
167 #ifdef CONFIG_ARCH_OMAP3
168 static struct resource omap3_mbox_resources[] = {
169 {
170 .start = OMAP34XX_MAILBOX_BASE,
171 .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
172 .flags = IORESOURCE_MEM,
173 },
174 {
175 .start = INT_24XX_MAIL_U0_MPU,
176 .flags = IORESOURCE_IRQ,
177 },
178 };
179 static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
180 #else
181 #define omap3_mbox_resources NULL
182 #define omap3_mbox_resources_sz 0
183 #endif
184
185 #ifdef CONFIG_ARCH_OMAP4
186
187 #define OMAP4_MBOX_REG_SIZE 0x130
188 static struct resource omap4_mbox_resources[] = {
189 {
190 .start = OMAP44XX_MAILBOX_BASE,
191 .end = OMAP44XX_MAILBOX_BASE +
192 OMAP4_MBOX_REG_SIZE - 1,
193 .flags = IORESOURCE_MEM,
194 },
195 {
196 .start = OMAP44XX_IRQ_MAIL_U0,
197 .flags = IORESOURCE_IRQ,
198 },
199 };
200 static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
201 #else
202 #define omap4_mbox_resources NULL
203 #define omap4_mbox_resources_sz 0
204 #endif
205
206 static struct platform_device mbox_device = {
207 .name = "omap2-mailbox",
208 .id = -1,
209 };
210
211 static inline void omap_init_mbox(void)
212 {
213 if (cpu_is_omap24xx()) {
214 mbox_device.resource = omap2_mbox_resources;
215 mbox_device.num_resources = omap2_mbox_resources_sz;
216 } else if (cpu_is_omap34xx()) {
217 mbox_device.resource = omap3_mbox_resources;
218 mbox_device.num_resources = omap3_mbox_resources_sz;
219 } else if (cpu_is_omap44xx()) {
220 mbox_device.resource = omap4_mbox_resources;
221 mbox_device.num_resources = omap4_mbox_resources_sz;
222 } else {
223 pr_err("%s: platform not supported\n", __func__);
224 return;
225 }
226 platform_device_register(&mbox_device);
227 }
228 #else
229 static inline void omap_init_mbox(void) { }
230 #endif /* CONFIG_OMAP_MBOX_FWK */
231
232 #if defined(CONFIG_OMAP_STI)
233
234 #if defined(CONFIG_ARCH_OMAP2)
235
236 #define OMAP2_STI_BASE 0x48068000
237 #define OMAP2_STI_CHANNEL_BASE 0x54000000
238 #define OMAP2_STI_IRQ 4
239
240 static struct resource sti_resources[] = {
241 {
242 .start = OMAP2_STI_BASE,
243 .end = OMAP2_STI_BASE + 0x7ff,
244 .flags = IORESOURCE_MEM,
245 },
246 {
247 .start = OMAP2_STI_CHANNEL_BASE,
248 .end = OMAP2_STI_CHANNEL_BASE + SZ_64K - 1,
249 .flags = IORESOURCE_MEM,
250 },
251 {
252 .start = OMAP2_STI_IRQ,
253 .flags = IORESOURCE_IRQ,
254 }
255 };
256 #elif defined(CONFIG_ARCH_OMAP3)
257
258 #define OMAP3_SDTI_BASE 0x54500000
259 #define OMAP3_SDTI_CHANNEL_BASE 0x54600000
260
261 static struct resource sti_resources[] = {
262 {
263 .start = OMAP3_SDTI_BASE,
264 .end = OMAP3_SDTI_BASE + 0xFFF,
265 .flags = IORESOURCE_MEM,
266 },
267 {
268 .start = OMAP3_SDTI_CHANNEL_BASE,
269 .end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
270 .flags = IORESOURCE_MEM,
271 }
272 };
273
274 #endif
275
276 static struct platform_device sti_device = {
277 .name = "sti",
278 .id = -1,
279 .num_resources = ARRAY_SIZE(sti_resources),
280 .resource = sti_resources,
281 };
282
283 static inline void omap_init_sti(void)
284 {
285 platform_device_register(&sti_device);
286 }
287 #else
288 static inline void omap_init_sti(void) {}
289 #endif
290
291 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
292
293 #include <plat/mcspi.h>
294
295 #define OMAP2_MCSPI1_BASE 0x48098000
296 #define OMAP2_MCSPI2_BASE 0x4809a000
297 #define OMAP2_MCSPI3_BASE 0x480b8000
298 #define OMAP2_MCSPI4_BASE 0x480ba000
299
300 #define OMAP4_MCSPI1_BASE 0x48098100
301 #define OMAP4_MCSPI2_BASE 0x4809a100
302 #define OMAP4_MCSPI3_BASE 0x480b8100
303 #define OMAP4_MCSPI4_BASE 0x480ba100
304
305 static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
306 .num_cs = 4,
307 };
308
309 static struct resource omap2_mcspi1_resources[] = {
310 {
311 .start = OMAP2_MCSPI1_BASE,
312 .end = OMAP2_MCSPI1_BASE + 0xff,
313 .flags = IORESOURCE_MEM,
314 },
315 };
316
317 static struct platform_device omap2_mcspi1 = {
318 .name = "omap2_mcspi",
319 .id = 1,
320 .num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
321 .resource = omap2_mcspi1_resources,
322 .dev = {
323 .platform_data = &omap2_mcspi1_config,
324 },
325 };
326
327 static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
328 .num_cs = 2,
329 };
330
331 static struct resource omap2_mcspi2_resources[] = {
332 {
333 .start = OMAP2_MCSPI2_BASE,
334 .end = OMAP2_MCSPI2_BASE + 0xff,
335 .flags = IORESOURCE_MEM,
336 },
337 };
338
339 static struct platform_device omap2_mcspi2 = {
340 .name = "omap2_mcspi",
341 .id = 2,
342 .num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
343 .resource = omap2_mcspi2_resources,
344 .dev = {
345 .platform_data = &omap2_mcspi2_config,
346 },
347 };
348
349 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
350 defined(CONFIG_ARCH_OMAP4)
351 static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
352 .num_cs = 2,
353 };
354
355 static struct resource omap2_mcspi3_resources[] = {
356 {
357 .start = OMAP2_MCSPI3_BASE,
358 .end = OMAP2_MCSPI3_BASE + 0xff,
359 .flags = IORESOURCE_MEM,
360 },
361 };
362
363 static struct platform_device omap2_mcspi3 = {
364 .name = "omap2_mcspi",
365 .id = 3,
366 .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
367 .resource = omap2_mcspi3_resources,
368 .dev = {
369 .platform_data = &omap2_mcspi3_config,
370 },
371 };
372 #endif
373
374 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
375 static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
376 .num_cs = 1,
377 };
378
379 static struct resource omap2_mcspi4_resources[] = {
380 {
381 .start = OMAP2_MCSPI4_BASE,
382 .end = OMAP2_MCSPI4_BASE + 0xff,
383 .flags = IORESOURCE_MEM,
384 },
385 };
386
387 static struct platform_device omap2_mcspi4 = {
388 .name = "omap2_mcspi",
389 .id = 4,
390 .num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
391 .resource = omap2_mcspi4_resources,
392 .dev = {
393 .platform_data = &omap2_mcspi4_config,
394 },
395 };
396 #endif
397
398 #ifdef CONFIG_ARCH_OMAP4
399 static inline void omap4_mcspi_fixup(void)
400 {
401 omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
402 omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff;
403 omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
404 omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff;
405 omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
406 omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff;
407 omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
408 omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff;
409 }
410 #else
411 static inline void omap4_mcspi_fixup(void)
412 {
413 }
414 #endif
415
416 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
417 defined(CONFIG_ARCH_OMAP4)
418 static inline void omap2_mcspi3_init(void)
419 {
420 platform_device_register(&omap2_mcspi3);
421 }
422 #else
423 static inline void omap2_mcspi3_init(void)
424 {
425 }
426 #endif
427
428 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
429 static inline void omap2_mcspi4_init(void)
430 {
431 platform_device_register(&omap2_mcspi4);
432 }
433 #else
434 static inline void omap2_mcspi4_init(void)
435 {
436 }
437 #endif
438
439 static void omap_init_mcspi(void)
440 {
441 if (cpu_is_omap44xx())
442 omap4_mcspi_fixup();
443
444 platform_device_register(&omap2_mcspi1);
445 platform_device_register(&omap2_mcspi2);
446
447 if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
448 omap2_mcspi3_init();
449
450 if (cpu_is_omap343x() || cpu_is_omap44xx())
451 omap2_mcspi4_init();
452 }
453
454 #else
455 static inline void omap_init_mcspi(void) {}
456 #endif
457
458 static struct resource omap2_pmu_resource = {
459 .start = 3,
460 .end = 3,
461 .flags = IORESOURCE_IRQ,
462 };
463
464 static struct resource omap3_pmu_resource = {
465 .start = INT_34XX_BENCH_MPU_EMUL,
466 .end = INT_34XX_BENCH_MPU_EMUL,
467 .flags = IORESOURCE_IRQ,
468 };
469
470 static struct platform_device omap_pmu_device = {
471 .name = "arm-pmu",
472 .id = ARM_PMU_DEVICE_CPU,
473 .num_resources = 1,
474 };
475
476 static void omap_init_pmu(void)
477 {
478 if (cpu_is_omap24xx())
479 omap_pmu_device.resource = &omap2_pmu_resource;
480 else if (cpu_is_omap34xx())
481 omap_pmu_device.resource = &omap3_pmu_resource;
482 else
483 return;
484
485 platform_device_register(&omap_pmu_device);
486 }
487
488
489 #ifdef CONFIG_OMAP_SHA1_MD5
490 static struct resource sha1_md5_resources[] = {
491 {
492 .start = OMAP24XX_SEC_SHA1MD5_BASE,
493 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
494 .flags = IORESOURCE_MEM,
495 },
496 {
497 .start = INT_24XX_SHA1MD5,
498 .flags = IORESOURCE_IRQ,
499 }
500 };
501
502 static struct platform_device sha1_md5_device = {
503 .name = "OMAP SHA1/MD5",
504 .id = -1,
505 .num_resources = ARRAY_SIZE(sha1_md5_resources),
506 .resource = sha1_md5_resources,
507 };
508
509 static void omap_init_sha1_md5(void)
510 {
511 platform_device_register(&sha1_md5_device);
512 }
513 #else
514 static inline void omap_init_sha1_md5(void) { }
515 #endif
516
517 /*-------------------------------------------------------------------------*/
518
519 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
520
521 #define MMCHS_SYSCONFIG 0x0010
522 #define MMCHS_SYSCONFIG_SWRESET (1 << 1)
523 #define MMCHS_SYSSTATUS 0x0014
524 #define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
525
526 static struct platform_device dummy_pdev = {
527 .dev = {
528 .bus = &platform_bus_type,
529 },
530 };
531
532 /**
533 * omap_hsmmc_reset() - Full reset of each HS-MMC controller
534 *
535 * Ensure that each MMC controller is fully reset. Controllers
536 * left in an unknown state (by bootloader) may prevent retention
537 * or OFF-mode. This is especially important in cases where the
538 * MMC driver is not enabled, _or_ built as a module.
539 *
540 * In order for reset to work, interface, functional and debounce
541 * clocks must be enabled. The debounce clock comes from func_32k_clk
542 * and is not under SW control, so we only enable i- and f-clocks.
543 **/
544 static void __init omap_hsmmc_reset(void)
545 {
546 u32 i, nr_controllers;
547
548 if (cpu_is_omap242x())
549 return;
550
551 nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
552 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
553
554 for (i = 0; i < nr_controllers; i++) {
555 u32 v, base = 0;
556 struct clk *iclk, *fclk;
557 struct device *dev = &dummy_pdev.dev;
558
559 switch (i) {
560 case 0:
561 base = OMAP2_MMC1_BASE;
562 break;
563 case 1:
564 base = OMAP2_MMC2_BASE;
565 break;
566 case 2:
567 base = OMAP3_MMC3_BASE;
568 break;
569 case 3:
570 if (!cpu_is_omap44xx())
571 return;
572 base = OMAP4_MMC4_BASE;
573 break;
574 case 4:
575 if (!cpu_is_omap44xx())
576 return;
577 base = OMAP4_MMC5_BASE;
578 break;
579 }
580
581 if (cpu_is_omap44xx())
582 base += OMAP4_MMC_REG_OFFSET;
583
584 dummy_pdev.id = i;
585 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
586 iclk = clk_get(dev, "ick");
587 if (iclk && clk_enable(iclk))
588 iclk = NULL;
589
590 fclk = clk_get(dev, "fck");
591 if (fclk && clk_enable(fclk))
592 fclk = NULL;
593
594 if (!iclk || !fclk) {
595 printk(KERN_WARNING
596 "%s: Unable to enable clocks for MMC%d, "
597 "cannot reset.\n", __func__, i);
598 break;
599 }
600
601 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
602 v = omap_readl(base + MMCHS_SYSSTATUS);
603 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
604 MMCHS_SYSSTATUS_RESETDONE))
605 cpu_relax();
606
607 if (fclk) {
608 clk_disable(fclk);
609 clk_put(fclk);
610 }
611 if (iclk) {
612 clk_disable(iclk);
613 clk_put(iclk);
614 }
615 }
616 }
617 #else
618 static inline void omap_hsmmc_reset(void) {}
619 #endif
620
621 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
622 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
623
624 static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
625 int controller_nr)
626 {
627 if (cpu_is_omap2420() && controller_nr == 0) {
628 omap_cfg_reg(H18_24XX_MMC_CMD);
629 omap_cfg_reg(H15_24XX_MMC_CLKI);
630 omap_cfg_reg(G19_24XX_MMC_CLKO);
631 omap_cfg_reg(F20_24XX_MMC_DAT0);
632 omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
633 omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
634 if (mmc_controller->slots[0].wires == 4) {
635 omap_cfg_reg(H14_24XX_MMC_DAT1);
636 omap_cfg_reg(E19_24XX_MMC_DAT2);
637 omap_cfg_reg(D19_24XX_MMC_DAT3);
638 omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
639 omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
640 omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
641 }
642
643 /*
644 * Use internal loop-back in MMC/SDIO Module Input Clock
645 * selection
646 */
647 if (mmc_controller->slots[0].internal_clock) {
648 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
649 v |= (1 << 24);
650 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
651 }
652 }
653
654 if (cpu_is_omap34xx()) {
655 if (controller_nr == 0) {
656 omap_mux_init_signal("sdmmc1_clk",
657 OMAP_PIN_INPUT_PULLUP);
658 omap_mux_init_signal("sdmmc1_cmd",
659 OMAP_PIN_INPUT_PULLUP);
660 omap_mux_init_signal("sdmmc1_dat0",
661 OMAP_PIN_INPUT_PULLUP);
662 if (mmc_controller->slots[0].wires == 4 ||
663 mmc_controller->slots[0].wires == 8) {
664 omap_mux_init_signal("sdmmc1_dat1",
665 OMAP_PIN_INPUT_PULLUP);
666 omap_mux_init_signal("sdmmc1_dat2",
667 OMAP_PIN_INPUT_PULLUP);
668 omap_mux_init_signal("sdmmc1_dat3",
669 OMAP_PIN_INPUT_PULLUP);
670 }
671 if (mmc_controller->slots[0].wires == 8) {
672 omap_mux_init_signal("sdmmc1_dat4",
673 OMAP_PIN_INPUT_PULLUP);
674 omap_mux_init_signal("sdmmc1_dat5",
675 OMAP_PIN_INPUT_PULLUP);
676 omap_mux_init_signal("sdmmc1_dat6",
677 OMAP_PIN_INPUT_PULLUP);
678 omap_mux_init_signal("sdmmc1_dat7",
679 OMAP_PIN_INPUT_PULLUP);
680 }
681 }
682 if (controller_nr == 1) {
683 /* MMC2 */
684 omap_mux_init_signal("sdmmc2_clk",
685 OMAP_PIN_INPUT_PULLUP);
686 omap_mux_init_signal("sdmmc2_cmd",
687 OMAP_PIN_INPUT_PULLUP);
688 omap_mux_init_signal("sdmmc2_dat0",
689 OMAP_PIN_INPUT_PULLUP);
690
691 /*
692 * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
693 * in the board-*.c files
694 */
695 if (mmc_controller->slots[0].wires == 4 ||
696 mmc_controller->slots[0].wires == 8) {
697 omap_mux_init_signal("sdmmc2_dat1",
698 OMAP_PIN_INPUT_PULLUP);
699 omap_mux_init_signal("sdmmc2_dat2",
700 OMAP_PIN_INPUT_PULLUP);
701 omap_mux_init_signal("sdmmc2_dat3",
702 OMAP_PIN_INPUT_PULLUP);
703 }
704 if (mmc_controller->slots[0].wires == 8) {
705 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
706 OMAP_PIN_INPUT_PULLUP);
707 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
708 OMAP_PIN_INPUT_PULLUP);
709 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
710 OMAP_PIN_INPUT_PULLUP);
711 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
712 OMAP_PIN_INPUT_PULLUP);
713 }
714 }
715
716 /*
717 * For MMC3 the pins need to be muxed in the board-*.c files
718 */
719 }
720 }
721
722 void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
723 int nr_controllers)
724 {
725 int i;
726 char *name;
727
728 for (i = 0; i < nr_controllers; i++) {
729 unsigned long base, size;
730 unsigned int irq = 0;
731
732 if (!mmc_data[i])
733 continue;
734
735 omap2_mmc_mux(mmc_data[i], i);
736
737 switch (i) {
738 case 0:
739 base = OMAP2_MMC1_BASE;
740 irq = INT_24XX_MMC_IRQ;
741 break;
742 case 1:
743 base = OMAP2_MMC2_BASE;
744 irq = INT_24XX_MMC2_IRQ;
745 break;
746 case 2:
747 if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
748 return;
749 base = OMAP3_MMC3_BASE;
750 irq = INT_34XX_MMC3_IRQ;
751 break;
752 case 3:
753 if (!cpu_is_omap44xx())
754 return;
755 base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
756 irq = OMAP44XX_IRQ_MMC4;
757 break;
758 case 4:
759 if (!cpu_is_omap44xx())
760 return;
761 base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
762 irq = OMAP44XX_IRQ_MMC5;
763 break;
764 default:
765 continue;
766 }
767
768 if (cpu_is_omap2420()) {
769 size = OMAP2420_MMC_SIZE;
770 name = "mmci-omap";
771 } else if (cpu_is_omap44xx()) {
772 if (i < 3) {
773 base += OMAP4_MMC_REG_OFFSET;
774 irq += OMAP44XX_IRQ_GIC_START;
775 }
776 size = OMAP4_HSMMC_SIZE;
777 name = "mmci-omap-hs";
778 } else {
779 size = OMAP3_HSMMC_SIZE;
780 name = "mmci-omap-hs";
781 }
782 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
783 };
784 }
785
786 #endif
787
788 /*-------------------------------------------------------------------------*/
789
790 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
791 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
792 #define OMAP_HDQ_BASE 0x480B2000
793 #endif
794 static struct resource omap_hdq_resources[] = {
795 {
796 .start = OMAP_HDQ_BASE,
797 .end = OMAP_HDQ_BASE + 0x1C,
798 .flags = IORESOURCE_MEM,
799 },
800 {
801 .start = INT_24XX_HDQ_IRQ,
802 .flags = IORESOURCE_IRQ,
803 },
804 };
805 static struct platform_device omap_hdq_dev = {
806 .name = "omap_hdq",
807 .id = 0,
808 .dev = {
809 .platform_data = NULL,
810 },
811 .num_resources = ARRAY_SIZE(omap_hdq_resources),
812 .resource = omap_hdq_resources,
813 };
814 static inline void omap_hdq_init(void)
815 {
816 (void) platform_device_register(&omap_hdq_dev);
817 }
818 #else
819 static inline void omap_hdq_init(void) {}
820 #endif
821
822 /*-------------------------------------------------------------------------*/
823
824 static int __init omap2_init_devices(void)
825 {
826 /* please keep these calls, and their implementations above,
827 * in alphabetical order so they're easier to sort through.
828 */
829 omap_hsmmc_reset();
830 omap_init_camera();
831 omap_init_mbox();
832 omap_init_mcspi();
833 omap_init_pmu();
834 omap_hdq_init();
835 omap_init_sti();
836 omap_init_sha1_md5();
837
838 return 0;
839 }
840 arch_initcall(omap2_init_devices);
Linux kernel - Deliverables
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