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OMAP: devices: Modify McSPI device to adapt to hwmod framework
[deliverable/linux.git] / arch / arm / mach-omap2 / devices.c
1 /*
2 * linux/arch/arm/mach-omap2/devices.c
3 *
4 * OMAP2 platform device setup/initialization
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/io.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
18 #include <linux/slab.h>
19
20 #include <mach/hardware.h>
21 #include <mach/irqs.h>
22 #include <asm/mach-types.h>
23 #include <asm/mach/map.h>
24 #include <asm/pmu.h>
25
26 #include <plat/tc.h>
27 #include <plat/board.h>
28 #include <plat/mcbsp.h>
29 #include <mach/gpio.h>
30 #include <plat/mmc.h>
31 #include <plat/dma.h>
32 #include <plat/omap_hwmod.h>
33 #include <plat/omap_device.h>
34
35 #include "mux.h"
36 #include "control.h"
37
38 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
39
40 static struct resource cam_resources[] = {
41 {
42 .start = OMAP24XX_CAMERA_BASE,
43 .end = OMAP24XX_CAMERA_BASE + 0xfff,
44 .flags = IORESOURCE_MEM,
45 },
46 {
47 .start = INT_24XX_CAM_IRQ,
48 .flags = IORESOURCE_IRQ,
49 }
50 };
51
52 static struct platform_device omap_cam_device = {
53 .name = "omap24xxcam",
54 .id = -1,
55 .num_resources = ARRAY_SIZE(cam_resources),
56 .resource = cam_resources,
57 };
58
59 static inline void omap_init_camera(void)
60 {
61 platform_device_register(&omap_cam_device);
62 }
63
64 #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
65
66 static struct resource omap3isp_resources[] = {
67 {
68 .start = OMAP3430_ISP_BASE,
69 .end = OMAP3430_ISP_END,
70 .flags = IORESOURCE_MEM,
71 },
72 {
73 .start = OMAP3430_ISP_CBUFF_BASE,
74 .end = OMAP3430_ISP_CBUFF_END,
75 .flags = IORESOURCE_MEM,
76 },
77 {
78 .start = OMAP3430_ISP_CCP2_BASE,
79 .end = OMAP3430_ISP_CCP2_END,
80 .flags = IORESOURCE_MEM,
81 },
82 {
83 .start = OMAP3430_ISP_CCDC_BASE,
84 .end = OMAP3430_ISP_CCDC_END,
85 .flags = IORESOURCE_MEM,
86 },
87 {
88 .start = OMAP3430_ISP_HIST_BASE,
89 .end = OMAP3430_ISP_HIST_END,
90 .flags = IORESOURCE_MEM,
91 },
92 {
93 .start = OMAP3430_ISP_H3A_BASE,
94 .end = OMAP3430_ISP_H3A_END,
95 .flags = IORESOURCE_MEM,
96 },
97 {
98 .start = OMAP3430_ISP_PREV_BASE,
99 .end = OMAP3430_ISP_PREV_END,
100 .flags = IORESOURCE_MEM,
101 },
102 {
103 .start = OMAP3430_ISP_RESZ_BASE,
104 .end = OMAP3430_ISP_RESZ_END,
105 .flags = IORESOURCE_MEM,
106 },
107 {
108 .start = OMAP3430_ISP_SBL_BASE,
109 .end = OMAP3430_ISP_SBL_END,
110 .flags = IORESOURCE_MEM,
111 },
112 {
113 .start = OMAP3430_ISP_CSI2A_BASE,
114 .end = OMAP3430_ISP_CSI2A_END,
115 .flags = IORESOURCE_MEM,
116 },
117 {
118 .start = OMAP3430_ISP_CSI2PHY_BASE,
119 .end = OMAP3430_ISP_CSI2PHY_END,
120 .flags = IORESOURCE_MEM,
121 },
122 {
123 .start = INT_34XX_CAM_IRQ,
124 .flags = IORESOURCE_IRQ,
125 }
126 };
127
128 static struct platform_device omap3isp_device = {
129 .name = "omap3isp",
130 .id = -1,
131 .num_resources = ARRAY_SIZE(omap3isp_resources),
132 .resource = omap3isp_resources,
133 };
134
135 static inline void omap_init_camera(void)
136 {
137 platform_device_register(&omap3isp_device);
138 }
139 #else
140 static inline void omap_init_camera(void)
141 {
142 }
143 #endif
144
145 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
146
147 #define MBOX_REG_SIZE 0x120
148
149 #ifdef CONFIG_ARCH_OMAP2
150 static struct resource omap2_mbox_resources[] = {
151 {
152 .start = OMAP24XX_MAILBOX_BASE,
153 .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
154 .flags = IORESOURCE_MEM,
155 },
156 {
157 .start = INT_24XX_MAIL_U0_MPU,
158 .flags = IORESOURCE_IRQ,
159 .name = "dsp",
160 },
161 {
162 .start = INT_24XX_MAIL_U3_MPU,
163 .flags = IORESOURCE_IRQ,
164 .name = "iva",
165 },
166 };
167 static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
168 #else
169 #define omap2_mbox_resources NULL
170 #define omap2_mbox_resources_sz 0
171 #endif
172
173 #ifdef CONFIG_ARCH_OMAP3
174 static struct resource omap3_mbox_resources[] = {
175 {
176 .start = OMAP34XX_MAILBOX_BASE,
177 .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
178 .flags = IORESOURCE_MEM,
179 },
180 {
181 .start = INT_24XX_MAIL_U0_MPU,
182 .flags = IORESOURCE_IRQ,
183 .name = "dsp",
184 },
185 };
186 static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
187 #else
188 #define omap3_mbox_resources NULL
189 #define omap3_mbox_resources_sz 0
190 #endif
191
192 #ifdef CONFIG_ARCH_OMAP4
193
194 #define OMAP4_MBOX_REG_SIZE 0x130
195 static struct resource omap4_mbox_resources[] = {
196 {
197 .start = OMAP44XX_MAILBOX_BASE,
198 .end = OMAP44XX_MAILBOX_BASE +
199 OMAP4_MBOX_REG_SIZE - 1,
200 .flags = IORESOURCE_MEM,
201 },
202 {
203 .start = OMAP44XX_IRQ_MAIL_U0,
204 .flags = IORESOURCE_IRQ,
205 .name = "mbox",
206 },
207 };
208 static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
209 #else
210 #define omap4_mbox_resources NULL
211 #define omap4_mbox_resources_sz 0
212 #endif
213
214 static struct platform_device mbox_device = {
215 .name = "omap-mailbox",
216 .id = -1,
217 };
218
219 static inline void omap_init_mbox(void)
220 {
221 if (cpu_is_omap24xx()) {
222 mbox_device.resource = omap2_mbox_resources;
223 mbox_device.num_resources = omap2_mbox_resources_sz;
224 } else if (cpu_is_omap34xx()) {
225 mbox_device.resource = omap3_mbox_resources;
226 mbox_device.num_resources = omap3_mbox_resources_sz;
227 } else if (cpu_is_omap44xx()) {
228 mbox_device.resource = omap4_mbox_resources;
229 mbox_device.num_resources = omap4_mbox_resources_sz;
230 } else {
231 pr_err("%s: platform not supported\n", __func__);
232 return;
233 }
234 platform_device_register(&mbox_device);
235 }
236 #else
237 static inline void omap_init_mbox(void) { }
238 #endif /* CONFIG_OMAP_MBOX_FWK */
239
240 static inline void omap_init_sti(void) {}
241
242 #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
243
244 static struct platform_device omap_pcm = {
245 .name = "omap-pcm-audio",
246 .id = -1,
247 };
248
249 /*
250 * OMAP2420 has 2 McBSP ports
251 * OMAP2430 has 5 McBSP ports
252 * OMAP3 has 5 McBSP ports
253 * OMAP4 has 4 McBSP ports
254 */
255 OMAP_MCBSP_PLATFORM_DEVICE(1);
256 OMAP_MCBSP_PLATFORM_DEVICE(2);
257 OMAP_MCBSP_PLATFORM_DEVICE(3);
258 OMAP_MCBSP_PLATFORM_DEVICE(4);
259 OMAP_MCBSP_PLATFORM_DEVICE(5);
260
261 static void omap_init_audio(void)
262 {
263 platform_device_register(&omap_mcbsp1);
264 platform_device_register(&omap_mcbsp2);
265 if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
266 platform_device_register(&omap_mcbsp3);
267 platform_device_register(&omap_mcbsp4);
268 }
269 if (cpu_is_omap243x() || cpu_is_omap34xx())
270 platform_device_register(&omap_mcbsp5);
271
272 platform_device_register(&omap_pcm);
273 }
274
275 #else
276 static inline void omap_init_audio(void) {}
277 #endif
278
279 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
280
281 #include <plat/mcspi.h>
282
283 struct omap_device_pm_latency omap_mcspi_latency[] = {
284 [0] = {
285 .deactivate_func = omap_device_idle_hwmods,
286 .activate_func = omap_device_enable_hwmods,
287 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
288 },
289 };
290
291 static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
292 {
293 struct omap_device *od;
294 char *name = "omap2_mcspi";
295 struct omap2_mcspi_platform_config *pdata;
296 static int spi_num;
297 struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
298
299 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
300 if (!pdata) {
301 pr_err("Memory allocation for McSPI device failed\n");
302 return -ENOMEM;
303 }
304
305 pdata->num_cs = mcspi_attrib->num_chipselect;
306 switch (oh->class->rev) {
307 case OMAP2_MCSPI_REV:
308 case OMAP3_MCSPI_REV:
309 pdata->regs_offset = 0;
310 break;
311 case OMAP4_MCSPI_REV:
312 pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
313 break;
314 default:
315 pr_err("Invalid McSPI Revision value\n");
316 return -EINVAL;
317 }
318
319 spi_num++;
320 od = omap_device_build(name, spi_num, oh, pdata,
321 sizeof(*pdata), omap_mcspi_latency,
322 ARRAY_SIZE(omap_mcspi_latency), 0);
323 WARN(IS_ERR(od), "Cant build omap_device for %s:%s\n",
324 name, oh->name);
325 kfree(pdata);
326 return 0;
327 }
328
329 static void omap_init_mcspi(void)
330 {
331 omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
332 }
333
334 #else
335 static inline void omap_init_mcspi(void) {}
336 #endif
337
338 static struct resource omap2_pmu_resource = {
339 .start = 3,
340 .end = 3,
341 .flags = IORESOURCE_IRQ,
342 };
343
344 static struct resource omap3_pmu_resource = {
345 .start = INT_34XX_BENCH_MPU_EMUL,
346 .end = INT_34XX_BENCH_MPU_EMUL,
347 .flags = IORESOURCE_IRQ,
348 };
349
350 static struct platform_device omap_pmu_device = {
351 .name = "arm-pmu",
352 .id = ARM_PMU_DEVICE_CPU,
353 .num_resources = 1,
354 };
355
356 static void omap_init_pmu(void)
357 {
358 if (cpu_is_omap24xx())
359 omap_pmu_device.resource = &omap2_pmu_resource;
360 else if (cpu_is_omap34xx())
361 omap_pmu_device.resource = &omap3_pmu_resource;
362 else
363 return;
364
365 platform_device_register(&omap_pmu_device);
366 }
367
368
369 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
370
371 #ifdef CONFIG_ARCH_OMAP2
372 static struct resource omap2_sham_resources[] = {
373 {
374 .start = OMAP24XX_SEC_SHA1MD5_BASE,
375 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
376 .flags = IORESOURCE_MEM,
377 },
378 {
379 .start = INT_24XX_SHA1MD5,
380 .flags = IORESOURCE_IRQ,
381 }
382 };
383 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
384 #else
385 #define omap2_sham_resources NULL
386 #define omap2_sham_resources_sz 0
387 #endif
388
389 #ifdef CONFIG_ARCH_OMAP3
390 static struct resource omap3_sham_resources[] = {
391 {
392 .start = OMAP34XX_SEC_SHA1MD5_BASE,
393 .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
394 .flags = IORESOURCE_MEM,
395 },
396 {
397 .start = INT_34XX_SHA1MD52_IRQ,
398 .flags = IORESOURCE_IRQ,
399 },
400 {
401 .start = OMAP34XX_DMA_SHA1MD5_RX,
402 .flags = IORESOURCE_DMA,
403 }
404 };
405 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
406 #else
407 #define omap3_sham_resources NULL
408 #define omap3_sham_resources_sz 0
409 #endif
410
411 static struct platform_device sham_device = {
412 .name = "omap-sham",
413 .id = -1,
414 };
415
416 static void omap_init_sham(void)
417 {
418 if (cpu_is_omap24xx()) {
419 sham_device.resource = omap2_sham_resources;
420 sham_device.num_resources = omap2_sham_resources_sz;
421 } else if (cpu_is_omap34xx()) {
422 sham_device.resource = omap3_sham_resources;
423 sham_device.num_resources = omap3_sham_resources_sz;
424 } else {
425 pr_err("%s: platform not supported\n", __func__);
426 return;
427 }
428 platform_device_register(&sham_device);
429 }
430 #else
431 static inline void omap_init_sham(void) { }
432 #endif
433
434 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
435
436 #ifdef CONFIG_ARCH_OMAP2
437 static struct resource omap2_aes_resources[] = {
438 {
439 .start = OMAP24XX_SEC_AES_BASE,
440 .end = OMAP24XX_SEC_AES_BASE + 0x4C,
441 .flags = IORESOURCE_MEM,
442 },
443 {
444 .start = OMAP24XX_DMA_AES_TX,
445 .flags = IORESOURCE_DMA,
446 },
447 {
448 .start = OMAP24XX_DMA_AES_RX,
449 .flags = IORESOURCE_DMA,
450 }
451 };
452 static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
453 #else
454 #define omap2_aes_resources NULL
455 #define omap2_aes_resources_sz 0
456 #endif
457
458 #ifdef CONFIG_ARCH_OMAP3
459 static struct resource omap3_aes_resources[] = {
460 {
461 .start = OMAP34XX_SEC_AES_BASE,
462 .end = OMAP34XX_SEC_AES_BASE + 0x4C,
463 .flags = IORESOURCE_MEM,
464 },
465 {
466 .start = OMAP34XX_DMA_AES2_TX,
467 .flags = IORESOURCE_DMA,
468 },
469 {
470 .start = OMAP34XX_DMA_AES2_RX,
471 .flags = IORESOURCE_DMA,
472 }
473 };
474 static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
475 #else
476 #define omap3_aes_resources NULL
477 #define omap3_aes_resources_sz 0
478 #endif
479
480 static struct platform_device aes_device = {
481 .name = "omap-aes",
482 .id = -1,
483 };
484
485 static void omap_init_aes(void)
486 {
487 if (cpu_is_omap24xx()) {
488 aes_device.resource = omap2_aes_resources;
489 aes_device.num_resources = omap2_aes_resources_sz;
490 } else if (cpu_is_omap34xx()) {
491 aes_device.resource = omap3_aes_resources;
492 aes_device.num_resources = omap3_aes_resources_sz;
493 } else {
494 pr_err("%s: platform not supported\n", __func__);
495 return;
496 }
497 platform_device_register(&aes_device);
498 }
499
500 #else
501 static inline void omap_init_aes(void) { }
502 #endif
503
504 /*-------------------------------------------------------------------------*/
505
506 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
507
508 #define MMCHS_SYSCONFIG 0x0010
509 #define MMCHS_SYSCONFIG_SWRESET (1 << 1)
510 #define MMCHS_SYSSTATUS 0x0014
511 #define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
512
513 static struct platform_device dummy_pdev = {
514 .dev = {
515 .bus = &platform_bus_type,
516 },
517 };
518
519 /**
520 * omap_hsmmc_reset() - Full reset of each HS-MMC controller
521 *
522 * Ensure that each MMC controller is fully reset. Controllers
523 * left in an unknown state (by bootloader) may prevent retention
524 * or OFF-mode. This is especially important in cases where the
525 * MMC driver is not enabled, _or_ built as a module.
526 *
527 * In order for reset to work, interface, functional and debounce
528 * clocks must be enabled. The debounce clock comes from func_32k_clk
529 * and is not under SW control, so we only enable i- and f-clocks.
530 **/
531 static void __init omap_hsmmc_reset(void)
532 {
533 u32 i, nr_controllers;
534 struct clk *iclk, *fclk;
535
536 if (cpu_is_omap242x())
537 return;
538
539 nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
540 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
541
542 for (i = 0; i < nr_controllers; i++) {
543 u32 v, base = 0;
544 struct device *dev = &dummy_pdev.dev;
545
546 switch (i) {
547 case 0:
548 base = OMAP2_MMC1_BASE;
549 break;
550 case 1:
551 base = OMAP2_MMC2_BASE;
552 break;
553 case 2:
554 base = OMAP3_MMC3_BASE;
555 break;
556 case 3:
557 if (!cpu_is_omap44xx())
558 return;
559 base = OMAP4_MMC4_BASE;
560 break;
561 case 4:
562 if (!cpu_is_omap44xx())
563 return;
564 base = OMAP4_MMC5_BASE;
565 break;
566 }
567
568 if (cpu_is_omap44xx())
569 base += OMAP4_MMC_REG_OFFSET;
570
571 dummy_pdev.id = i;
572 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
573 iclk = clk_get(dev, "ick");
574 if (IS_ERR(iclk))
575 goto err1;
576 if (clk_enable(iclk))
577 goto err2;
578
579 fclk = clk_get(dev, "fck");
580 if (IS_ERR(fclk))
581 goto err3;
582 if (clk_enable(fclk))
583 goto err4;
584
585 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
586 v = omap_readl(base + MMCHS_SYSSTATUS);
587 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
588 MMCHS_SYSSTATUS_RESETDONE))
589 cpu_relax();
590
591 clk_disable(fclk);
592 clk_put(fclk);
593 clk_disable(iclk);
594 clk_put(iclk);
595 }
596 return;
597
598 err4:
599 clk_put(fclk);
600 err3:
601 clk_disable(iclk);
602 err2:
603 clk_put(iclk);
604 err1:
605 printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, "
606 "cannot reset.\n", __func__, i);
607 }
608 #else
609 static inline void omap_hsmmc_reset(void) {}
610 #endif
611
612 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
613 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
614
615 static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
616 int controller_nr)
617 {
618 if ((mmc_controller->slots[0].switch_pin > 0) && \
619 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
620 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
621 OMAP_PIN_INPUT_PULLUP);
622 if ((mmc_controller->slots[0].gpio_wp > 0) && \
623 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
624 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
625 OMAP_PIN_INPUT_PULLUP);
626
627 if (cpu_is_omap2420() && controller_nr == 0) {
628 omap_mux_init_signal("sdmmc_cmd", 0);
629 omap_mux_init_signal("sdmmc_clki", 0);
630 omap_mux_init_signal("sdmmc_clko", 0);
631 omap_mux_init_signal("sdmmc_dat0", 0);
632 omap_mux_init_signal("sdmmc_dat_dir0", 0);
633 omap_mux_init_signal("sdmmc_cmd_dir", 0);
634 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
635 omap_mux_init_signal("sdmmc_dat1", 0);
636 omap_mux_init_signal("sdmmc_dat2", 0);
637 omap_mux_init_signal("sdmmc_dat3", 0);
638 omap_mux_init_signal("sdmmc_dat_dir1", 0);
639 omap_mux_init_signal("sdmmc_dat_dir2", 0);
640 omap_mux_init_signal("sdmmc_dat_dir3", 0);
641 }
642
643 /*
644 * Use internal loop-back in MMC/SDIO Module Input Clock
645 * selection
646 */
647 if (mmc_controller->slots[0].internal_clock) {
648 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
649 v |= (1 << 24);
650 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
651 }
652 }
653
654 if (cpu_is_omap34xx()) {
655 if (controller_nr == 0) {
656 omap_mux_init_signal("sdmmc1_clk",
657 OMAP_PIN_INPUT_PULLUP);
658 omap_mux_init_signal("sdmmc1_cmd",
659 OMAP_PIN_INPUT_PULLUP);
660 omap_mux_init_signal("sdmmc1_dat0",
661 OMAP_PIN_INPUT_PULLUP);
662 if (mmc_controller->slots[0].caps &
663 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
664 omap_mux_init_signal("sdmmc1_dat1",
665 OMAP_PIN_INPUT_PULLUP);
666 omap_mux_init_signal("sdmmc1_dat2",
667 OMAP_PIN_INPUT_PULLUP);
668 omap_mux_init_signal("sdmmc1_dat3",
669 OMAP_PIN_INPUT_PULLUP);
670 }
671 if (mmc_controller->slots[0].caps &
672 MMC_CAP_8_BIT_DATA) {
673 omap_mux_init_signal("sdmmc1_dat4",
674 OMAP_PIN_INPUT_PULLUP);
675 omap_mux_init_signal("sdmmc1_dat5",
676 OMAP_PIN_INPUT_PULLUP);
677 omap_mux_init_signal("sdmmc1_dat6",
678 OMAP_PIN_INPUT_PULLUP);
679 omap_mux_init_signal("sdmmc1_dat7",
680 OMAP_PIN_INPUT_PULLUP);
681 }
682 }
683 if (controller_nr == 1) {
684 /* MMC2 */
685 omap_mux_init_signal("sdmmc2_clk",
686 OMAP_PIN_INPUT_PULLUP);
687 omap_mux_init_signal("sdmmc2_cmd",
688 OMAP_PIN_INPUT_PULLUP);
689 omap_mux_init_signal("sdmmc2_dat0",
690 OMAP_PIN_INPUT_PULLUP);
691
692 /*
693 * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
694 * in the board-*.c files
695 */
696 if (mmc_controller->slots[0].caps &
697 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
698 omap_mux_init_signal("sdmmc2_dat1",
699 OMAP_PIN_INPUT_PULLUP);
700 omap_mux_init_signal("sdmmc2_dat2",
701 OMAP_PIN_INPUT_PULLUP);
702 omap_mux_init_signal("sdmmc2_dat3",
703 OMAP_PIN_INPUT_PULLUP);
704 }
705 if (mmc_controller->slots[0].caps &
706 MMC_CAP_8_BIT_DATA) {
707 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
708 OMAP_PIN_INPUT_PULLUP);
709 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
710 OMAP_PIN_INPUT_PULLUP);
711 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
712 OMAP_PIN_INPUT_PULLUP);
713 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
714 OMAP_PIN_INPUT_PULLUP);
715 }
716 }
717
718 /*
719 * For MMC3 the pins need to be muxed in the board-*.c files
720 */
721 }
722 }
723
724 void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
725 int nr_controllers)
726 {
727 int i;
728 char *name;
729
730 for (i = 0; i < nr_controllers; i++) {
731 unsigned long base, size;
732 unsigned int irq = 0;
733
734 if (!mmc_data[i])
735 continue;
736
737 omap2_mmc_mux(mmc_data[i], i);
738
739 switch (i) {
740 case 0:
741 base = OMAP2_MMC1_BASE;
742 irq = INT_24XX_MMC_IRQ;
743 break;
744 case 1:
745 base = OMAP2_MMC2_BASE;
746 irq = INT_24XX_MMC2_IRQ;
747 break;
748 case 2:
749 if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
750 return;
751 base = OMAP3_MMC3_BASE;
752 irq = INT_34XX_MMC3_IRQ;
753 break;
754 case 3:
755 if (!cpu_is_omap44xx())
756 return;
757 base = OMAP4_MMC4_BASE;
758 irq = OMAP44XX_IRQ_MMC4;
759 break;
760 case 4:
761 if (!cpu_is_omap44xx())
762 return;
763 base = OMAP4_MMC5_BASE;
764 irq = OMAP44XX_IRQ_MMC5;
765 break;
766 default:
767 continue;
768 }
769
770 if (cpu_is_omap2420()) {
771 size = OMAP2420_MMC_SIZE;
772 name = "mmci-omap";
773 } else if (cpu_is_omap44xx()) {
774 if (i < 3)
775 irq += OMAP44XX_IRQ_GIC_START;
776 size = OMAP4_HSMMC_SIZE;
777 name = "mmci-omap-hs";
778 } else {
779 size = OMAP3_HSMMC_SIZE;
780 name = "mmci-omap-hs";
781 }
782 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
783 };
784 }
785
786 #endif
787
788 /*-------------------------------------------------------------------------*/
789
790 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
791 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
792 #define OMAP_HDQ_BASE 0x480B2000
793 #endif
794 static struct resource omap_hdq_resources[] = {
795 {
796 .start = OMAP_HDQ_BASE,
797 .end = OMAP_HDQ_BASE + 0x1C,
798 .flags = IORESOURCE_MEM,
799 },
800 {
801 .start = INT_24XX_HDQ_IRQ,
802 .flags = IORESOURCE_IRQ,
803 },
804 };
805 static struct platform_device omap_hdq_dev = {
806 .name = "omap_hdq",
807 .id = 0,
808 .dev = {
809 .platform_data = NULL,
810 },
811 .num_resources = ARRAY_SIZE(omap_hdq_resources),
812 .resource = omap_hdq_resources,
813 };
814 static inline void omap_hdq_init(void)
815 {
816 (void) platform_device_register(&omap_hdq_dev);
817 }
818 #else
819 static inline void omap_hdq_init(void) {}
820 #endif
821
822 /*---------------------------------------------------------------------------*/
823
824 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
825 defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
826 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
827 static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
828 };
829 #else
830 static struct resource omap_vout_resource[2] = {
831 };
832 #endif
833
834 static struct platform_device omap_vout_device = {
835 .name = "omap_vout",
836 .num_resources = ARRAY_SIZE(omap_vout_resource),
837 .resource = &omap_vout_resource[0],
838 .id = -1,
839 };
840 static void omap_init_vout(void)
841 {
842 if (platform_device_register(&omap_vout_device) < 0)
843 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
844 }
845 #else
846 static inline void omap_init_vout(void) {}
847 #endif
848
849 /*-------------------------------------------------------------------------*/
850
851 static int __init omap2_init_devices(void)
852 {
853 /*
854 * please keep these calls, and their implementations above,
855 * in alphabetical order so they're easier to sort through.
856 */
857 omap_hsmmc_reset();
858 omap_init_audio();
859 omap_init_camera();
860 omap_init_mbox();
861 omap_init_mcspi();
862 omap_init_pmu();
863 omap_hdq_init();
864 omap_init_sti();
865 omap_init_sham();
866 omap_init_aes();
867 omap_init_vout();
868
869 return 0;
870 }
871 arch_initcall(omap2_init_devices);
872
873 #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
874 static struct omap_device_pm_latency omap_wdt_latency[] = {
875 [0] = {
876 .deactivate_func = omap_device_idle_hwmods,
877 .activate_func = omap_device_enable_hwmods,
878 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
879 },
880 };
881
882 static int __init omap_init_wdt(void)
883 {
884 int id = -1;
885 struct omap_device *od;
886 struct omap_hwmod *oh;
887 char *oh_name = "wd_timer2";
888 char *dev_name = "omap_wdt";
889
890 if (!cpu_class_is_omap2())
891 return 0;
892
893 oh = omap_hwmod_lookup(oh_name);
894 if (!oh) {
895 pr_err("Could not look up wd_timer%d hwmod\n", id);
896 return -EINVAL;
897 }
898
899 od = omap_device_build(dev_name, id, oh, NULL, 0,
900 omap_wdt_latency,
901 ARRAY_SIZE(omap_wdt_latency), 0);
902 WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n",
903 dev_name, oh->name);
904 return 0;
905 }
906 subsys_initcall(omap_init_wdt);
907 #endif
Linux kernel - Deliverables
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