2 * OMAP2plus display device setup / initialization.
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Senthilvadivu Guruswamy
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/string.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
23 #include <linux/clk.h>
24 #include <linux/err.h>
25 #include <linux/delay.h>
27 #include <video/omapdss.h>
28 #include <plat/omap_hwmod.h>
29 #include <plat/omap_device.h>
30 #include <plat/omap-pm.h>
38 #define DISPC_CONTROL 0x0040
39 #define DISPC_CONTROL2 0x0238
40 #define DISPC_CONTROL3 0x0848
41 #define DISPC_IRQSTATUS 0x0018
43 #define DSS_SYSCONFIG 0x10
44 #define DSS_SYSSTATUS 0x14
45 #define DSS_CONTROL 0x40
46 #define DSS_SDI_CONTROL 0x44
47 #define DSS_PLL_CONTROL 0x48
49 #define LCD_EN_MASK (0x1 << 0)
50 #define DIGIT_EN_MASK (0x1 << 1)
52 #define FRAMEDONE_IRQ_SHIFT 0
53 #define EVSYNC_EVEN_IRQ_SHIFT 2
54 #define EVSYNC_ODD_IRQ_SHIFT 3
55 #define FRAMEDONE2_IRQ_SHIFT 22
56 #define FRAMEDONE3_IRQ_SHIFT 30
57 #define FRAMEDONETV_IRQ_SHIFT 24
60 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
61 * reset before deciding that something has gone wrong
63 #define FRAMEDONE_IRQ_TIMEOUT 100
65 static struct platform_device omap_display_device
= {
69 .platform_data
= NULL
,
73 struct omap_dss_hwmod_data
{
79 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data
[] __initconst
= {
80 { "dss_core", "omapdss_dss", -1 },
81 { "dss_dispc", "omapdss_dispc", -1 },
82 { "dss_rfbi", "omapdss_rfbi", -1 },
83 { "dss_venc", "omapdss_venc", -1 },
86 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data
[] __initconst
= {
87 { "dss_core", "omapdss_dss", -1 },
88 { "dss_dispc", "omapdss_dispc", -1 },
89 { "dss_rfbi", "omapdss_rfbi", -1 },
90 { "dss_venc", "omapdss_venc", -1 },
91 { "dss_dsi1", "omapdss_dsi", 0 },
94 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data
[] __initconst
= {
95 { "dss_core", "omapdss_dss", -1 },
96 { "dss_dispc", "omapdss_dispc", -1 },
97 { "dss_rfbi", "omapdss_rfbi", -1 },
98 { "dss_dsi1", "omapdss_dsi", 0 },
99 { "dss_dsi2", "omapdss_dsi", 1 },
100 { "dss_hdmi", "omapdss_hdmi", -1 },
103 static void __init
omap4_hdmi_mux_pads(enum omap_hdmi_flags flags
)
108 omap_mux_init_signal("hdmi_cec",
109 OMAP_PIN_INPUT_PULLUP
);
110 omap_mux_init_signal("hdmi_ddc_scl",
111 OMAP_PIN_INPUT_PULLUP
);
112 omap_mux_init_signal("hdmi_ddc_sda",
113 OMAP_PIN_INPUT_PULLUP
);
116 * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
117 * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
118 * internal pull up resistor.
120 if (flags
& OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP
) {
121 control_i2c_1
= OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1
;
122 reg
= omap4_ctrl_pad_readl(control_i2c_1
);
123 reg
|= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK
|
124 OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK
);
125 omap4_ctrl_pad_writel(reg
, control_i2c_1
);
129 static int omap4_dsi_mux_pads(int dsi_id
, unsigned lanes
)
131 u32 enable_mask
, enable_shift
;
132 u32 pipd_mask
, pipd_shift
;
136 enable_mask
= OMAP4_DSI1_LANEENABLE_MASK
;
137 enable_shift
= OMAP4_DSI1_LANEENABLE_SHIFT
;
138 pipd_mask
= OMAP4_DSI1_PIPD_MASK
;
139 pipd_shift
= OMAP4_DSI1_PIPD_SHIFT
;
140 } else if (dsi_id
== 1) {
141 enable_mask
= OMAP4_DSI2_LANEENABLE_MASK
;
142 enable_shift
= OMAP4_DSI2_LANEENABLE_SHIFT
;
143 pipd_mask
= OMAP4_DSI2_PIPD_MASK
;
144 pipd_shift
= OMAP4_DSI2_PIPD_SHIFT
;
149 reg
= omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY
);
154 reg
|= (lanes
<< enable_shift
) & enable_mask
;
155 reg
|= (lanes
<< pipd_shift
) & pipd_mask
;
157 omap4_ctrl_pad_writel(reg
, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY
);
162 int __init
omap_hdmi_init(enum omap_hdmi_flags flags
)
164 if (cpu_is_omap44xx())
165 omap4_hdmi_mux_pads(flags
);
170 static int omap_dsi_enable_pads(int dsi_id
, unsigned lane_mask
)
172 if (cpu_is_omap44xx())
173 return omap4_dsi_mux_pads(dsi_id
, lane_mask
);
178 static void omap_dsi_disable_pads(int dsi_id
, unsigned lane_mask
)
180 if (cpu_is_omap44xx())
181 omap4_dsi_mux_pads(dsi_id
, 0);
184 static int omap_dss_set_min_bus_tput(struct device
*dev
, unsigned long tput
)
186 return omap_pm_set_min_bus_tput(dev
, OCP_INITIATOR_AGENT
, tput
);
189 static struct platform_device
*create_dss_pdev(const char *pdev_name
,
190 int pdev_id
, const char *oh_name
, void *pdata
, int pdata_len
,
191 struct platform_device
*parent
)
193 struct platform_device
*pdev
;
194 struct omap_device
*od
;
195 struct omap_hwmod
*ohs
[1];
196 struct omap_hwmod
*oh
;
199 oh
= omap_hwmod_lookup(oh_name
);
201 pr_err("Could not look up %s\n", oh_name
);
206 pdev
= platform_device_alloc(pdev_name
, pdev_id
);
208 pr_err("Could not create pdev for %s\n", pdev_name
);
214 pdev
->dev
.parent
= &parent
->dev
;
217 dev_set_name(&pdev
->dev
, "%s.%d", pdev
->name
, pdev
->id
);
219 dev_set_name(&pdev
->dev
, "%s", pdev
->name
);
222 od
= omap_device_alloc(pdev
, ohs
, 1, NULL
, 0);
224 pr_err("Could not alloc omap_device for %s\n", pdev_name
);
229 r
= platform_device_add_data(pdev
, pdata
, pdata_len
);
231 pr_err("Could not set pdata for %s\n", pdev_name
);
235 r
= omap_device_register(pdev
);
237 pr_err("Could not register omap_device for %s\n", pdev_name
);
247 static struct platform_device
*create_simple_dss_pdev(const char *pdev_name
,
248 int pdev_id
, void *pdata
, int pdata_len
,
249 struct platform_device
*parent
)
251 struct platform_device
*pdev
;
254 pdev
= platform_device_alloc(pdev_name
, pdev_id
);
256 pr_err("Could not create pdev for %s\n", pdev_name
);
262 pdev
->dev
.parent
= &parent
->dev
;
265 dev_set_name(&pdev
->dev
, "%s.%d", pdev
->name
, pdev
->id
);
267 dev_set_name(&pdev
->dev
, "%s", pdev
->name
);
269 r
= platform_device_add_data(pdev
, pdata
, pdata_len
);
271 pr_err("Could not set pdata for %s\n", pdev_name
);
275 r
= platform_device_add(pdev
);
277 pr_err("Could not register platform_device for %s\n", pdev_name
);
287 static enum omapdss_version __init
omap_display_get_version(void)
289 if (cpu_is_omap24xx())
290 return OMAPDSS_VER_OMAP24xx
;
291 else if (cpu_is_omap3630())
292 return OMAPDSS_VER_OMAP3630
;
293 else if (cpu_is_omap34xx()) {
294 if (soc_is_am35xx()) {
295 return OMAPDSS_VER_AM35xx
;
297 if (omap_rev() < OMAP3430_REV_ES3_0
)
298 return OMAPDSS_VER_OMAP34xx_ES1
;
300 return OMAPDSS_VER_OMAP34xx_ES3
;
302 } else if (omap_rev() == OMAP4430_REV_ES1_0
)
303 return OMAPDSS_VER_OMAP4430_ES1
;
304 else if (omap_rev() == OMAP4430_REV_ES2_0
||
305 omap_rev() == OMAP4430_REV_ES2_1
||
306 omap_rev() == OMAP4430_REV_ES2_2
)
307 return OMAPDSS_VER_OMAP4430_ES2
;
308 else if (cpu_is_omap44xx())
309 return OMAPDSS_VER_OMAP4
;
310 else if (soc_is_omap54xx())
311 return OMAPDSS_VER_OMAP5
;
313 return OMAPDSS_VER_UNKNOWN
;
316 int __init
omap_display_init(struct omap_dss_board_info
*board_data
)
319 struct platform_device
*pdev
;
321 const struct omap_dss_hwmod_data
*curr_dss_hwmod
;
322 struct platform_device
*dss_pdev
;
323 enum omapdss_version ver
;
325 /* create omapdss device */
327 ver
= omap_display_get_version();
329 if (ver
== OMAPDSS_VER_UNKNOWN
) {
330 pr_err("DSS not supported on this SoC\n");
334 board_data
->version
= ver
;
335 board_data
->dsi_enable_pads
= omap_dsi_enable_pads
;
336 board_data
->dsi_disable_pads
= omap_dsi_disable_pads
;
337 board_data
->get_context_loss_count
= omap_pm_get_dev_context_loss_count
;
338 board_data
->set_min_bus_tput
= omap_dss_set_min_bus_tput
;
340 omap_display_device
.dev
.platform_data
= board_data
;
342 r
= platform_device_register(&omap_display_device
);
344 pr_err("Unable to register omapdss device\n");
348 /* create devices for dss hwmods */
350 if (cpu_is_omap24xx()) {
351 curr_dss_hwmod
= omap2_dss_hwmod_data
;
352 oh_count
= ARRAY_SIZE(omap2_dss_hwmod_data
);
353 } else if (cpu_is_omap34xx()) {
354 curr_dss_hwmod
= omap3_dss_hwmod_data
;
355 oh_count
= ARRAY_SIZE(omap3_dss_hwmod_data
);
357 curr_dss_hwmod
= omap4_dss_hwmod_data
;
358 oh_count
= ARRAY_SIZE(omap4_dss_hwmod_data
);
362 * First create the pdev for dss_core, which is used as a parent device
363 * by the other dss pdevs. Note: dss_core has to be the first item in
366 dss_pdev
= create_dss_pdev(curr_dss_hwmod
[0].dev_name
,
367 curr_dss_hwmod
[0].id
,
368 curr_dss_hwmod
[0].oh_name
,
369 board_data
, sizeof(*board_data
),
372 if (IS_ERR(dss_pdev
)) {
373 pr_err("Could not build omap_device for %s\n",
374 curr_dss_hwmod
[0].oh_name
);
376 return PTR_ERR(dss_pdev
);
379 for (i
= 1; i
< oh_count
; i
++) {
380 pdev
= create_dss_pdev(curr_dss_hwmod
[i
].dev_name
,
381 curr_dss_hwmod
[i
].id
,
382 curr_dss_hwmod
[i
].oh_name
,
383 board_data
, sizeof(*board_data
),
387 pr_err("Could not build omap_device for %s\n",
388 curr_dss_hwmod
[i
].oh_name
);
390 return PTR_ERR(pdev
);
394 /* Create devices for DPI and SDI */
396 pdev
= create_simple_dss_pdev("omapdss_dpi", -1,
397 board_data
, sizeof(*board_data
), dss_pdev
);
399 pr_err("Could not build platform_device for omapdss_dpi\n");
400 return PTR_ERR(pdev
);
403 if (cpu_is_omap34xx()) {
404 pdev
= create_simple_dss_pdev("omapdss_sdi", -1,
405 board_data
, sizeof(*board_data
), dss_pdev
);
407 pr_err("Could not build platform_device for omapdss_sdi\n");
408 return PTR_ERR(pdev
);
415 static void dispc_disable_outputs(void)
418 bool lcd_en
, digit_en
, lcd2_en
= false, lcd3_en
= false;
420 struct omap_dss_dispc_dev_attr
*da
;
421 struct omap_hwmod
*oh
;
423 oh
= omap_hwmod_lookup("dss_dispc");
425 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
430 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
434 da
= (struct omap_dss_dispc_dev_attr
*)oh
->dev_attr
;
436 /* store value of LCDENABLE and DIGITENABLE bits */
437 v
= omap_hwmod_read(oh
, DISPC_CONTROL
);
438 lcd_en
= v
& LCD_EN_MASK
;
439 digit_en
= v
& DIGIT_EN_MASK
;
441 /* store value of LCDENABLE for LCD2 */
442 if (da
->manager_count
> 2) {
443 v
= omap_hwmod_read(oh
, DISPC_CONTROL2
);
444 lcd2_en
= v
& LCD_EN_MASK
;
447 /* store value of LCDENABLE for LCD3 */
448 if (da
->manager_count
> 3) {
449 v
= omap_hwmod_read(oh
, DISPC_CONTROL3
);
450 lcd3_en
= v
& LCD_EN_MASK
;
453 if (!(lcd_en
| digit_en
| lcd2_en
| lcd3_en
))
454 return; /* no managers currently enabled */
457 * If any manager was enabled, we need to disable it before
458 * DSS clocks are disabled or DISPC module is reset
461 irq_mask
|= 1 << FRAMEDONE_IRQ_SHIFT
;
464 if (da
->has_framedonetv_irq
) {
465 irq_mask
|= 1 << FRAMEDONETV_IRQ_SHIFT
;
467 irq_mask
|= 1 << EVSYNC_EVEN_IRQ_SHIFT
|
468 1 << EVSYNC_ODD_IRQ_SHIFT
;
473 irq_mask
|= 1 << FRAMEDONE2_IRQ_SHIFT
;
475 irq_mask
|= 1 << FRAMEDONE3_IRQ_SHIFT
;
478 * clear any previous FRAMEDONE, FRAMEDONETV,
479 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
481 omap_hwmod_write(irq_mask
, oh
, DISPC_IRQSTATUS
);
483 /* disable LCD and TV managers */
484 v
= omap_hwmod_read(oh
, DISPC_CONTROL
);
485 v
&= ~(LCD_EN_MASK
| DIGIT_EN_MASK
);
486 omap_hwmod_write(v
, oh
, DISPC_CONTROL
);
488 /* disable LCD2 manager */
489 if (da
->manager_count
> 2) {
490 v
= omap_hwmod_read(oh
, DISPC_CONTROL2
);
492 omap_hwmod_write(v
, oh
, DISPC_CONTROL2
);
495 /* disable LCD3 manager */
496 if (da
->manager_count
> 3) {
497 v
= omap_hwmod_read(oh
, DISPC_CONTROL3
);
499 omap_hwmod_write(v
, oh
, DISPC_CONTROL3
);
503 while ((omap_hwmod_read(oh
, DISPC_IRQSTATUS
) & irq_mask
) !=
506 if (i
> FRAMEDONE_IRQ_TIMEOUT
) {
507 pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
514 #define MAX_MODULE_SOFTRESET_WAIT 10000
515 int omap_dss_reset(struct omap_hwmod
*oh
)
517 struct omap_hwmod_opt_clk
*oc
;
521 if (!(oh
->class->sysc
->sysc_flags
& SYSS_HAS_RESET_STATUS
)) {
522 pr_err("dss_core: hwmod data doesn't contain reset data\n");
526 for (i
= oh
->opt_clks_cnt
, oc
= oh
->opt_clks
; i
> 0; i
--, oc
++)
528 clk_prepare_enable(oc
->_clk
);
530 dispc_disable_outputs();
532 /* clear SDI registers */
533 if (cpu_is_omap3430()) {
534 omap_hwmod_write(0x0, oh
, DSS_SDI_CONTROL
);
535 omap_hwmod_write(0x0, oh
, DSS_PLL_CONTROL
);
539 * clear DSS_CONTROL register to switch DSS clock sources to
542 omap_hwmod_write(0x0, oh
, DSS_CONTROL
);
544 omap_test_timeout((omap_hwmod_read(oh
, oh
->class->sysc
->syss_offs
)
545 & SYSS_RESETDONE_MASK
),
546 MAX_MODULE_SOFTRESET_WAIT
, c
);
548 if (c
== MAX_MODULE_SOFTRESET_WAIT
)
549 pr_warning("dss_core: waiting for reset to finish failed\n");
551 pr_debug("dss_core: softreset done\n");
553 for (i
= oh
->opt_clks_cnt
, oc
= oh
->opt_clks
; i
> 0; i
--, oc
++)
555 clk_disable_unprepare(oc
->_clk
);
557 r
= (c
== MAX_MODULE_SOFTRESET_WAIT
) ? -ETIMEDOUT
: 0;