2 * OMAP2plus display device setup / initialization.
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Senthilvadivu Guruswamy
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/string.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
23 #include <linux/clk.h>
24 #include <linux/err.h>
25 #include <linux/delay.h>
27 #include <video/omapdss.h>
28 #include "omap_hwmod.h"
29 #include "omap_device.h"
39 #define DISPC_CONTROL 0x0040
40 #define DISPC_CONTROL2 0x0238
41 #define DISPC_CONTROL3 0x0848
42 #define DISPC_IRQSTATUS 0x0018
44 #define DSS_SYSCONFIG 0x10
45 #define DSS_SYSSTATUS 0x14
46 #define DSS_CONTROL 0x40
47 #define DSS_SDI_CONTROL 0x44
48 #define DSS_PLL_CONTROL 0x48
50 #define LCD_EN_MASK (0x1 << 0)
51 #define DIGIT_EN_MASK (0x1 << 1)
53 #define FRAMEDONE_IRQ_SHIFT 0
54 #define EVSYNC_EVEN_IRQ_SHIFT 2
55 #define EVSYNC_ODD_IRQ_SHIFT 3
56 #define FRAMEDONE2_IRQ_SHIFT 22
57 #define FRAMEDONE3_IRQ_SHIFT 30
58 #define FRAMEDONETV_IRQ_SHIFT 24
61 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
62 * reset before deciding that something has gone wrong
64 #define FRAMEDONE_IRQ_TIMEOUT 100
66 static struct platform_device omap_display_device
= {
70 .platform_data
= NULL
,
74 struct omap_dss_hwmod_data
{
80 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data
[] __initconst
= {
81 { "dss_core", "omapdss_dss", -1 },
82 { "dss_dispc", "omapdss_dispc", -1 },
83 { "dss_rfbi", "omapdss_rfbi", -1 },
84 { "dss_venc", "omapdss_venc", -1 },
87 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data
[] __initconst
= {
88 { "dss_core", "omapdss_dss", -1 },
89 { "dss_dispc", "omapdss_dispc", -1 },
90 { "dss_rfbi", "omapdss_rfbi", -1 },
91 { "dss_venc", "omapdss_venc", -1 },
92 { "dss_dsi1", "omapdss_dsi", 0 },
95 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data
[] __initconst
= {
96 { "dss_core", "omapdss_dss", -1 },
97 { "dss_dispc", "omapdss_dispc", -1 },
98 { "dss_rfbi", "omapdss_rfbi", -1 },
99 { "dss_dsi1", "omapdss_dsi", 0 },
100 { "dss_dsi2", "omapdss_dsi", 1 },
101 { "dss_hdmi", "omapdss_hdmi", -1 },
104 static void __init
omap4_hdmi_mux_pads(enum omap_hdmi_flags flags
)
109 omap_mux_init_signal("hdmi_cec",
110 OMAP_PIN_INPUT_PULLUP
);
111 omap_mux_init_signal("hdmi_ddc_scl",
112 OMAP_PIN_INPUT_PULLUP
);
113 omap_mux_init_signal("hdmi_ddc_sda",
114 OMAP_PIN_INPUT_PULLUP
);
117 * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
118 * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
119 * internal pull up resistor.
121 if (flags
& OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP
) {
122 control_i2c_1
= OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1
;
123 reg
= omap4_ctrl_pad_readl(control_i2c_1
);
124 reg
|= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK
|
125 OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK
);
126 omap4_ctrl_pad_writel(reg
, control_i2c_1
);
130 static int omap4_dsi_mux_pads(int dsi_id
, unsigned lanes
)
132 u32 enable_mask
, enable_shift
;
133 u32 pipd_mask
, pipd_shift
;
137 enable_mask
= OMAP4_DSI1_LANEENABLE_MASK
;
138 enable_shift
= OMAP4_DSI1_LANEENABLE_SHIFT
;
139 pipd_mask
= OMAP4_DSI1_PIPD_MASK
;
140 pipd_shift
= OMAP4_DSI1_PIPD_SHIFT
;
141 } else if (dsi_id
== 1) {
142 enable_mask
= OMAP4_DSI2_LANEENABLE_MASK
;
143 enable_shift
= OMAP4_DSI2_LANEENABLE_SHIFT
;
144 pipd_mask
= OMAP4_DSI2_PIPD_MASK
;
145 pipd_shift
= OMAP4_DSI2_PIPD_SHIFT
;
150 reg
= omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY
);
155 reg
|= (lanes
<< enable_shift
) & enable_mask
;
156 reg
|= (lanes
<< pipd_shift
) & pipd_mask
;
158 omap4_ctrl_pad_writel(reg
, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY
);
163 int __init
omap_hdmi_init(enum omap_hdmi_flags flags
)
165 if (cpu_is_omap44xx())
166 omap4_hdmi_mux_pads(flags
);
171 static int omap_dsi_enable_pads(int dsi_id
, unsigned lane_mask
)
173 if (cpu_is_omap44xx())
174 return omap4_dsi_mux_pads(dsi_id
, lane_mask
);
179 static void omap_dsi_disable_pads(int dsi_id
, unsigned lane_mask
)
181 if (cpu_is_omap44xx())
182 omap4_dsi_mux_pads(dsi_id
, 0);
185 static int omap_dss_set_min_bus_tput(struct device
*dev
, unsigned long tput
)
187 return omap_pm_set_min_bus_tput(dev
, OCP_INITIATOR_AGENT
, tput
);
190 static struct platform_device
*create_dss_pdev(const char *pdev_name
,
191 int pdev_id
, const char *oh_name
, void *pdata
, int pdata_len
,
192 struct platform_device
*parent
)
194 struct platform_device
*pdev
;
195 struct omap_device
*od
;
196 struct omap_hwmod
*ohs
[1];
197 struct omap_hwmod
*oh
;
200 oh
= omap_hwmod_lookup(oh_name
);
202 pr_err("Could not look up %s\n", oh_name
);
207 pdev
= platform_device_alloc(pdev_name
, pdev_id
);
209 pr_err("Could not create pdev for %s\n", pdev_name
);
215 pdev
->dev
.parent
= &parent
->dev
;
218 dev_set_name(&pdev
->dev
, "%s.%d", pdev
->name
, pdev
->id
);
220 dev_set_name(&pdev
->dev
, "%s", pdev
->name
);
223 od
= omap_device_alloc(pdev
, ohs
, 1, NULL
, 0);
225 pr_err("Could not alloc omap_device for %s\n", pdev_name
);
230 r
= platform_device_add_data(pdev
, pdata
, pdata_len
);
232 pr_err("Could not set pdata for %s\n", pdev_name
);
236 r
= omap_device_register(pdev
);
238 pr_err("Could not register omap_device for %s\n", pdev_name
);
248 static struct platform_device
*create_simple_dss_pdev(const char *pdev_name
,
249 int pdev_id
, void *pdata
, int pdata_len
,
250 struct platform_device
*parent
)
252 struct platform_device
*pdev
;
255 pdev
= platform_device_alloc(pdev_name
, pdev_id
);
257 pr_err("Could not create pdev for %s\n", pdev_name
);
263 pdev
->dev
.parent
= &parent
->dev
;
266 dev_set_name(&pdev
->dev
, "%s.%d", pdev
->name
, pdev
->id
);
268 dev_set_name(&pdev
->dev
, "%s", pdev
->name
);
270 r
= platform_device_add_data(pdev
, pdata
, pdata_len
);
272 pr_err("Could not set pdata for %s\n", pdev_name
);
276 r
= platform_device_add(pdev
);
278 pr_err("Could not register platform_device for %s\n", pdev_name
);
288 static enum omapdss_version __init
omap_display_get_version(void)
290 if (cpu_is_omap24xx())
291 return OMAPDSS_VER_OMAP24xx
;
292 else if (cpu_is_omap3630())
293 return OMAPDSS_VER_OMAP3630
;
294 else if (cpu_is_omap34xx()) {
295 if (soc_is_am35xx()) {
296 return OMAPDSS_VER_AM35xx
;
298 if (omap_rev() < OMAP3430_REV_ES3_0
)
299 return OMAPDSS_VER_OMAP34xx_ES1
;
301 return OMAPDSS_VER_OMAP34xx_ES3
;
303 } else if (omap_rev() == OMAP4430_REV_ES1_0
)
304 return OMAPDSS_VER_OMAP4430_ES1
;
305 else if (omap_rev() == OMAP4430_REV_ES2_0
||
306 omap_rev() == OMAP4430_REV_ES2_1
||
307 omap_rev() == OMAP4430_REV_ES2_2
)
308 return OMAPDSS_VER_OMAP4430_ES2
;
309 else if (cpu_is_omap44xx())
310 return OMAPDSS_VER_OMAP4
;
311 else if (soc_is_omap54xx())
312 return OMAPDSS_VER_OMAP5
;
314 return OMAPDSS_VER_UNKNOWN
;
317 int __init
omap_display_init(struct omap_dss_board_info
*board_data
)
320 struct platform_device
*pdev
;
322 const struct omap_dss_hwmod_data
*curr_dss_hwmod
;
323 struct platform_device
*dss_pdev
;
324 enum omapdss_version ver
;
326 /* create omapdss device */
328 ver
= omap_display_get_version();
330 if (ver
== OMAPDSS_VER_UNKNOWN
) {
331 pr_err("DSS not supported on this SoC\n");
335 board_data
->version
= ver
;
336 board_data
->dsi_enable_pads
= omap_dsi_enable_pads
;
337 board_data
->dsi_disable_pads
= omap_dsi_disable_pads
;
338 board_data
->get_context_loss_count
= omap_pm_get_dev_context_loss_count
;
339 board_data
->set_min_bus_tput
= omap_dss_set_min_bus_tput
;
341 omap_display_device
.dev
.platform_data
= board_data
;
343 r
= platform_device_register(&omap_display_device
);
345 pr_err("Unable to register omapdss device\n");
349 /* create devices for dss hwmods */
351 if (cpu_is_omap24xx()) {
352 curr_dss_hwmod
= omap2_dss_hwmod_data
;
353 oh_count
= ARRAY_SIZE(omap2_dss_hwmod_data
);
354 } else if (cpu_is_omap34xx()) {
355 curr_dss_hwmod
= omap3_dss_hwmod_data
;
356 oh_count
= ARRAY_SIZE(omap3_dss_hwmod_data
);
358 curr_dss_hwmod
= omap4_dss_hwmod_data
;
359 oh_count
= ARRAY_SIZE(omap4_dss_hwmod_data
);
363 * First create the pdev for dss_core, which is used as a parent device
364 * by the other dss pdevs. Note: dss_core has to be the first item in
367 dss_pdev
= create_dss_pdev(curr_dss_hwmod
[0].dev_name
,
368 curr_dss_hwmod
[0].id
,
369 curr_dss_hwmod
[0].oh_name
,
370 board_data
, sizeof(*board_data
),
373 if (IS_ERR(dss_pdev
)) {
374 pr_err("Could not build omap_device for %s\n",
375 curr_dss_hwmod
[0].oh_name
);
377 return PTR_ERR(dss_pdev
);
380 for (i
= 1; i
< oh_count
; i
++) {
381 pdev
= create_dss_pdev(curr_dss_hwmod
[i
].dev_name
,
382 curr_dss_hwmod
[i
].id
,
383 curr_dss_hwmod
[i
].oh_name
,
384 board_data
, sizeof(*board_data
),
388 pr_err("Could not build omap_device for %s\n",
389 curr_dss_hwmod
[i
].oh_name
);
391 return PTR_ERR(pdev
);
395 /* Create devices for DPI and SDI */
397 pdev
= create_simple_dss_pdev("omapdss_dpi", -1,
398 board_data
, sizeof(*board_data
), dss_pdev
);
400 pr_err("Could not build platform_device for omapdss_dpi\n");
401 return PTR_ERR(pdev
);
404 if (cpu_is_omap34xx()) {
405 pdev
= create_simple_dss_pdev("omapdss_sdi", -1,
406 board_data
, sizeof(*board_data
), dss_pdev
);
408 pr_err("Could not build platform_device for omapdss_sdi\n");
409 return PTR_ERR(pdev
);
416 static void dispc_disable_outputs(void)
419 bool lcd_en
, digit_en
, lcd2_en
= false, lcd3_en
= false;
421 struct omap_dss_dispc_dev_attr
*da
;
422 struct omap_hwmod
*oh
;
424 oh
= omap_hwmod_lookup("dss_dispc");
426 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
431 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
435 da
= (struct omap_dss_dispc_dev_attr
*)oh
->dev_attr
;
437 /* store value of LCDENABLE and DIGITENABLE bits */
438 v
= omap_hwmod_read(oh
, DISPC_CONTROL
);
439 lcd_en
= v
& LCD_EN_MASK
;
440 digit_en
= v
& DIGIT_EN_MASK
;
442 /* store value of LCDENABLE for LCD2 */
443 if (da
->manager_count
> 2) {
444 v
= omap_hwmod_read(oh
, DISPC_CONTROL2
);
445 lcd2_en
= v
& LCD_EN_MASK
;
448 /* store value of LCDENABLE for LCD3 */
449 if (da
->manager_count
> 3) {
450 v
= omap_hwmod_read(oh
, DISPC_CONTROL3
);
451 lcd3_en
= v
& LCD_EN_MASK
;
454 if (!(lcd_en
| digit_en
| lcd2_en
| lcd3_en
))
455 return; /* no managers currently enabled */
458 * If any manager was enabled, we need to disable it before
459 * DSS clocks are disabled or DISPC module is reset
462 irq_mask
|= 1 << FRAMEDONE_IRQ_SHIFT
;
465 if (da
->has_framedonetv_irq
) {
466 irq_mask
|= 1 << FRAMEDONETV_IRQ_SHIFT
;
468 irq_mask
|= 1 << EVSYNC_EVEN_IRQ_SHIFT
|
469 1 << EVSYNC_ODD_IRQ_SHIFT
;
474 irq_mask
|= 1 << FRAMEDONE2_IRQ_SHIFT
;
476 irq_mask
|= 1 << FRAMEDONE3_IRQ_SHIFT
;
479 * clear any previous FRAMEDONE, FRAMEDONETV,
480 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
482 omap_hwmod_write(irq_mask
, oh
, DISPC_IRQSTATUS
);
484 /* disable LCD and TV managers */
485 v
= omap_hwmod_read(oh
, DISPC_CONTROL
);
486 v
&= ~(LCD_EN_MASK
| DIGIT_EN_MASK
);
487 omap_hwmod_write(v
, oh
, DISPC_CONTROL
);
489 /* disable LCD2 manager */
490 if (da
->manager_count
> 2) {
491 v
= omap_hwmod_read(oh
, DISPC_CONTROL2
);
493 omap_hwmod_write(v
, oh
, DISPC_CONTROL2
);
496 /* disable LCD3 manager */
497 if (da
->manager_count
> 3) {
498 v
= omap_hwmod_read(oh
, DISPC_CONTROL3
);
500 omap_hwmod_write(v
, oh
, DISPC_CONTROL3
);
504 while ((omap_hwmod_read(oh
, DISPC_IRQSTATUS
) & irq_mask
) !=
507 if (i
> FRAMEDONE_IRQ_TIMEOUT
) {
508 pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
515 #define MAX_MODULE_SOFTRESET_WAIT 10000
516 int omap_dss_reset(struct omap_hwmod
*oh
)
518 struct omap_hwmod_opt_clk
*oc
;
522 if (!(oh
->class->sysc
->sysc_flags
& SYSS_HAS_RESET_STATUS
)) {
523 pr_err("dss_core: hwmod data doesn't contain reset data\n");
527 for (i
= oh
->opt_clks_cnt
, oc
= oh
->opt_clks
; i
> 0; i
--, oc
++)
529 clk_prepare_enable(oc
->_clk
);
531 dispc_disable_outputs();
533 /* clear SDI registers */
534 if (cpu_is_omap3430()) {
535 omap_hwmod_write(0x0, oh
, DSS_SDI_CONTROL
);
536 omap_hwmod_write(0x0, oh
, DSS_PLL_CONTROL
);
540 * clear DSS_CONTROL register to switch DSS clock sources to
543 omap_hwmod_write(0x0, oh
, DSS_CONTROL
);
545 omap_test_timeout((omap_hwmod_read(oh
, oh
->class->sysc
->syss_offs
)
546 & SYSS_RESETDONE_MASK
),
547 MAX_MODULE_SOFTRESET_WAIT
, c
);
549 if (c
== MAX_MODULE_SOFTRESET_WAIT
)
550 pr_warning("dss_core: waiting for reset to finish failed\n");
552 pr_debug("dss_core: softreset done\n");
554 for (i
= oh
->opt_clks_cnt
, oc
= oh
->opt_clks
; i
> 0; i
--, oc
++)
556 clk_disable_unprepare(oc
->_clk
);
558 r
= (c
== MAX_MODULE_SOFTRESET_WAIT
) ? -ETIMEDOUT
: 0;