4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 * Copyright (C) 2009 Texas Instruments
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
16 * Converted DMA library into platform driver
17 * - G, Manjunath Kondaiah <manjugk@ti.com>
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
24 #include <linux/err.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/device.h>
31 #include <plat-omap/dma-omap.h>
33 #include "omap_hwmod.h"
34 #include "omap_device.h"
36 #define OMAP2_DMA_STRIDE 0x60
41 static struct omap_dma_dev_attr
*d
;
43 static enum omap_reg_offsets dma_common_ch_start
, dma_common_ch_end
;
45 static u16 reg_map
[] = {
48 [IRQSTATUS_L0
] = 0x08,
49 [IRQSTATUS_L1
] = 0x0c,
50 [IRQSTATUS_L2
] = 0x10,
51 [IRQSTATUS_L3
] = 0x14,
52 [IRQENABLE_L0
] = 0x18,
53 [IRQENABLE_L1
] = 0x1c,
54 [IRQENABLE_L2
] = 0x20,
55 [IRQENABLE_L3
] = 0x24,
57 [OCP_SYSCONFIG
] = 0x2c,
63 /* Common register offsets */
78 /* Channel specific register offsets */
85 /* OMAP4 specific registers */
91 static void __iomem
*dma_base
;
92 static inline void dma_write(u32 val
, int reg
, int lch
)
97 stride
= (reg
>= dma_common_ch_start
) ? dma_stride
: 0;
98 offset
= reg_map
[reg
] + (stride
* lch
);
99 __raw_writel(val
, dma_base
+ offset
);
102 static inline u32
dma_read(int reg
, int lch
)
107 stride
= (reg
>= dma_common_ch_start
) ? dma_stride
: 0;
108 offset
= reg_map
[reg
] + (stride
* lch
);
109 val
= __raw_readl(dma_base
+ offset
);
113 static inline void omap2_disable_irq_lch(int lch
)
117 val
= dma_read(IRQENABLE_L0
, lch
);
119 dma_write(val
, IRQENABLE_L0
, lch
);
122 static void omap2_clear_dma(int lch
)
124 int i
= dma_common_ch_start
;
126 for (; i
<= dma_common_ch_end
; i
+= 1)
127 dma_write(0, i
, lch
);
130 static void omap2_show_dma_caps(void)
132 u8 revision
= dma_read(REVISION
, 0) & 0xff;
133 printk(KERN_INFO
"OMAP DMA hardware revision %d.%d\n",
134 revision
>> 4, revision
& 0xf);
138 static u32
configure_dma_errata(void)
142 * Errata applicable for OMAP2430ES1.0 and all omap2420
145 * Erratum ID: Not Available
146 * Inter Frame DMA buffering issue DMA will wrongly
147 * buffer elements if packing and bursting is enabled. This might
148 * result in data gets stalled in FIFO at the end of the block.
149 * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
150 * guarantee no data will stay in the DMA FIFO in case inter frame
154 * Erratum ID: Not Available
155 * DMA may hang when several channels are used in parallel
156 * In the following configuration, DMA channel hanging can occur:
157 * a. Channel i, hardware synchronized, is enabled
158 * b. Another channel (Channel x), software synchronized, is enabled.
159 * c. Channel i is disabled before end of transfer
160 * d. Channel i is reenabled.
161 * e. Steps 1 to 4 are repeated a certain number of times.
162 * f. A third channel (Channel y), software synchronized, is enabled.
163 * Channel x and Channel y may hang immediately after step 'f'.
165 * For any channel used - make sure NextLCH_ID is set to the value j.
167 if (cpu_is_omap2420() || (cpu_is_omap2430() &&
168 (omap_type() == OMAP2430_REV_ES1_0
))) {
170 SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING
);
171 SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS
);
175 * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
176 * after a transaction error.
177 * Workaround: SW should explicitely disable the channel.
179 if (cpu_class_is_omap2())
180 SET_DMA_ERRATA(DMA_ERRATA_i378
);
183 * Erratum ID: i541: sDMA FIFO draining does not finish
184 * If sDMA channel is disabled on the fly, sDMA enters standby even
185 * through FIFO Drain is still in progress
186 * Workaround: Put sDMA in NoStandby more before a logical channel is
187 * disabled, then put it back to SmartStandby right after the channel
188 * finishes FIFO draining.
190 if (cpu_is_omap34xx())
191 SET_DMA_ERRATA(DMA_ERRATA_i541
);
194 * Erratum ID: i88 : Special programming model needed to disable DMA
195 * before end of block.
196 * Workaround: software must ensure that the DMA is configured in No
197 * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
199 if (omap_type() == OMAP3430_REV_ES1_0
)
200 SET_DMA_ERRATA(DMA_ERRATA_i88
);
203 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
204 * read before the DMA controller finished disabling the channel.
206 SET_DMA_ERRATA(DMA_ERRATA_3_3
);
209 * Erratum ID: Not Available
210 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
211 * after secure sram context save and restore.
212 * Work around: Hence we need to manually clear those IRQs to avoid
213 * spurious interrupts. This affects only secure devices.
215 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP
))
216 SET_DMA_ERRATA(DMA_ROMCODE_BUG
);
221 /* One time initializations */
222 static int __init
omap2_system_dma_init_dev(struct omap_hwmod
*oh
, void *unused
)
224 struct platform_device
*pdev
;
225 struct omap_system_dma_plat_info
*p
;
226 struct resource
*mem
;
227 char *name
= "omap_dma_system";
229 dma_stride
= OMAP2_DMA_STRIDE
;
230 dma_common_ch_start
= CSDP
;
232 p
= kzalloc(sizeof(struct omap_system_dma_plat_info
), GFP_KERNEL
);
234 pr_err("%s: Unable to allocate pdata for %s:%s\n",
235 __func__
, name
, oh
->name
);
239 p
->dma_attr
= (struct omap_dma_dev_attr
*)oh
->dev_attr
;
240 p
->disable_irq_lch
= omap2_disable_irq_lch
;
241 p
->show_dma_caps
= omap2_show_dma_caps
;
242 p
->clear_dma
= omap2_clear_dma
;
243 p
->dma_write
= dma_write
;
244 p
->dma_read
= dma_read
;
246 p
->clear_lch_regs
= NULL
;
248 p
->errata
= configure_dma_errata();
250 pdev
= omap_device_build(name
, 0, oh
, p
, sizeof(*p
), NULL
, 0, 0);
253 pr_err("%s: Can't build omap_device for %s:%s.\n",
254 __func__
, name
, oh
->name
);
255 return PTR_ERR(pdev
);
258 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
260 dev_err(&pdev
->dev
, "%s: no mem resource\n", __func__
);
263 dma_base
= ioremap(mem
->start
, resource_size(mem
));
265 dev_err(&pdev
->dev
, "%s: ioremap fail\n", __func__
);
270 d
->chan
= kzalloc(sizeof(struct omap_dma_lch
) *
271 (d
->lch_count
), GFP_KERNEL
);
274 dev_err(&pdev
->dev
, "%s: kzalloc fail\n", __func__
);
278 /* Check the capabilities register for descriptor loading feature */
279 if (dma_read(CAPS_0
, 0) & DMA_HAS_DESCRIPTOR_CAPS
)
280 dma_common_ch_end
= CCDN
;
282 dma_common_ch_end
= CCFN
;
287 static int __init
omap2_system_dma_init(void)
289 return omap_hwmod_for_each_by_class("dma",
290 omap2_system_dma_init_dev
, NULL
);
292 arch_initcall(omap2_system_dma_init
);