arch/arm/mach-omap2/dpll3xxx.c

   1 /*
   2  * OMAP3/4 - specific DPLL control functions
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * Testing and integration fixes by Jouni Högander
   9  *
  10  * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
  11  * Menon
  12  *
  13  * Parts of this code are based on code written by
  14  * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/device.h>
  23 #include <linux/list.h>
  24 #include <linux/errno.h>
  25 #include <linux/delay.h>
  26 #include <linux/clk.h>
  27 #include <linux/io.h>
  28 #include <linux/bitops.h>
  29 #include <linux/clkdev.h>
  30
  31 #include "soc.h"
  32 #include "clockdomain.h"
  33 #include "clock.h"
  34 #include "cm2xxx_3xxx.h"
  35 #include "cm-regbits-34xx.h"
  36
  37 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
  38 #define DPLL_AUTOIDLE_DISABLE                   0x0
  39 #define DPLL_AUTOIDLE_LOW_POWER_STOP            0x1
  40
  41 #define MAX_DPLL_WAIT_TRIES             1000000
  42
  43 /* Private functions */
  44
  45 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
  46 static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
  47 {
  48         const struct dpll_data *dd;
  49         u32 v;
  50
  51         dd = clk->dpll_data;
  52
  53         v = omap2_clk_readl(clk, dd->control_reg);
  54         v &= ~dd->enable_mask;
  55         v |= clken_bits << __ffs(dd->enable_mask);
  56         omap2_clk_writel(v, clk, dd->control_reg);
  57 }
  58
  59 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
  60 static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
  61 {
  62         const struct dpll_data *dd;
  63         int i = 0;
  64         int ret = -EINVAL;
  65         const char *clk_name;
  66
  67         dd = clk->dpll_data;
  68         clk_name = __clk_get_name(clk->hw.clk);
  69
  70         state <<= __ffs(dd->idlest_mask);
  71
  72         while (((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask)
  73                 != state) && i < MAX_DPLL_WAIT_TRIES) {
  74                 i++;
  75                 udelay(1);
  76         }
  77
  78         if (i == MAX_DPLL_WAIT_TRIES) {
  79                 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
  80                        clk_name, (state) ? "locked" : "bypassed");
  81         } else {
  82                 pr_debug("clock: %s transition to '%s' in %d loops\n",
  83                          clk_name, (state) ? "locked" : "bypassed", i);
  84
  85                 ret = 0;
  86         }
  87
  88         return ret;
  89 }
  90
  91 /* From 3430 TRM ES2 4.7.6.2 */
  92 static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
  93 {
  94         unsigned long fint;
  95         u16 f = 0;
  96
  97         fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;
  98
  99         pr_debug("clock: fint is %lu\n", fint);
 100
 101         if (fint >= 750000 && fint <= 1000000)
 102                 f = 0x3;
 103         else if (fint > 1000000 && fint <= 1250000)
 104                 f = 0x4;
 105         else if (fint > 1250000 && fint <= 1500000)
 106                 f = 0x5;
 107         else if (fint > 1500000 && fint <= 1750000)
 108                 f = 0x6;
 109         else if (fint > 1750000 && fint <= 2100000)
 110                 f = 0x7;
 111         else if (fint > 7500000 && fint <= 10000000)
 112                 f = 0xB;
 113         else if (fint > 10000000 && fint <= 12500000)
 114                 f = 0xC;
 115         else if (fint > 12500000 && fint <= 15000000)
 116                 f = 0xD;
 117         else if (fint > 15000000 && fint <= 17500000)
 118                 f = 0xE;
 119         else if (fint > 17500000 && fint <= 21000000)
 120                 f = 0xF;
 121         else
 122                 pr_debug("clock: unknown freqsel setting for %d\n", n);
 123
 124         return f;
 125 }
 126
 127 /*
 128  * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
 129  * @clk: pointer to a DPLL struct clk
 130  *
 131  * Instructs a non-CORE DPLL to lock.  Waits for the DPLL to report
 132  * readiness before returning.  Will save and restore the DPLL's
 133  * autoidle state across the enable, per the CDP code.  If the DPLL
 134  * locked successfully, return 0; if the DPLL did not lock in the time
 135  * allotted, or DPLL3 was passed in, return -EINVAL.
 136  */
 137 static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
 138 {
 139         const struct dpll_data *dd;
 140         u8 ai;
 141         u8 state = 1;
 142         int r = 0;
 143
 144         pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk));
 145
 146         dd = clk->dpll_data;
 147         state <<= __ffs(dd->idlest_mask);
 148
 149         /* Check if already locked */
 150         if ((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) == state)
 151                 goto done;
 152
 153         ai = omap3_dpll_autoidle_read(clk);
 154
 155         if (ai)
 156                 omap3_dpll_deny_idle(clk);
 157
 158         _omap3_dpll_write_clken(clk, DPLL_LOCKED);
 159
 160         r = _omap3_wait_dpll_status(clk, 1);
 161
 162         if (ai)
 163                 omap3_dpll_allow_idle(clk);
 164
 165 done:
 166         return r;
 167 }
 168
 169 /*
 170  * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
 171  * @clk: pointer to a DPLL struct clk
 172  *
 173  * Instructs a non-CORE DPLL to enter low-power bypass mode.  In
 174  * bypass mode, the DPLL's rate is set equal to its parent clock's
 175  * rate.  Waits for the DPLL to report readiness before returning.
 176  * Will save and restore the DPLL's autoidle state across the enable,
 177  * per the CDP code.  If the DPLL entered bypass mode successfully,
 178  * return 0; if the DPLL did not enter bypass in the time allotted, or
 179  * DPLL3 was passed in, or the DPLL does not support low-power bypass,
 180  * return -EINVAL.
 181  */
 182 static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
 183 {
 184         int r;
 185         u8 ai;
 186
 187         if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
 188                 return -EINVAL;
 189
 190         pr_debug("clock: configuring DPLL %s for low-power bypass\n",
 191                  __clk_get_name(clk->hw.clk));
 192
 193         ai = omap3_dpll_autoidle_read(clk);
 194
 195         _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
 196
 197         r = _omap3_wait_dpll_status(clk, 0);
 198
 199         if (ai)
 200                 omap3_dpll_allow_idle(clk);
 201
 202         return r;
 203 }
 204
 205 /*
 206  * _omap3_noncore_dpll_stop - instruct a DPLL to stop
 207  * @clk: pointer to a DPLL struct clk
 208  *
 209  * Instructs a non-CORE DPLL to enter low-power stop. Will save and
 210  * restore the DPLL's autoidle state across the stop, per the CDP
 211  * code.  If DPLL3 was passed in, or the DPLL does not support
 212  * low-power stop, return -EINVAL; otherwise, return 0.
 213  */
 214 static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)
 215 {
 216         u8 ai;
 217
 218         if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
 219                 return -EINVAL;
 220
 221         pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk));
 222
 223         ai = omap3_dpll_autoidle_read(clk);
 224
 225         _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
 226
 227         if (ai)
 228                 omap3_dpll_allow_idle(clk);
 229
 230         return 0;
 231 }
 232
 233 /**
 234  * _lookup_dco - Lookup DCO used by j-type DPLL
 235  * @clk: pointer to a DPLL struct clk
 236  * @dco: digital control oscillator selector
 237  * @m: DPLL multiplier to set
 238  * @n: DPLL divider to set
 239  *
 240  * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
 241  *
 242  * XXX This code is not needed for 3430/AM35xx; can it be optimized
 243  * out in non-multi-OMAP builds for those chips?
 244  */
 245 static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n)
 246 {
 247         unsigned long fint, clkinp; /* watch out for overflow */
 248
 249         clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));
 250         fint = (clkinp / n) * m;
 251
 252         if (fint < 1000000000)
 253                 *dco = 2;
 254         else
 255                 *dco = 4;
 256 }
 257
 258 /**
 259  * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
 260  * @clk: pointer to a DPLL struct clk
 261  * @sd_div: target sigma-delta divider
 262  * @m: DPLL multiplier to set
 263  * @n: DPLL divider to set
 264  *
 265  * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
 266  *
 267  * XXX This code is not needed for 3430/AM35xx; can it be optimized
 268  * out in non-multi-OMAP builds for those chips?
 269  */
 270 static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
 271 {
 272         unsigned long clkinp, sd; /* watch out for overflow */
 273         int mod1, mod2;
 274
 275         clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));
 276
 277         /*
 278          * target sigma-delta to near 250MHz
 279          * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
 280          */
 281         clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
 282         mod1 = (clkinp * m) % (250 * n);
 283         sd = (clkinp * m) / (250 * n);
 284         mod2 = sd % 10;
 285         sd /= 10;
 286
 287         if (mod1 || mod2)
 288                 sd++;
 289         *sd_div = sd;
 290 }
 291
 292 /*
 293  * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
 294  * @clk:        struct clk * of DPLL to set
 295  * @freqsel:    FREQSEL value to set
 296  *
 297  * Program the DPLL with the last M, N values calculated, and wait for
 298  * the DPLL to lock. Returns -EINVAL upon error, or 0 upon success.
 299  */
 300 static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
 301 {
 302         struct dpll_data *dd = clk->dpll_data;
 303         u8 dco, sd_div;
 304         u32 v;
 305
 306         /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
 307         _omap3_noncore_dpll_bypass(clk);
 308
 309         /*
 310          * Set jitter correction. Jitter correction applicable for OMAP343X
 311          * only since freqsel field is no longer present on other devices.
 312          */
 313         if (cpu_is_omap343x()) {
 314                 v = omap2_clk_readl(clk, dd->control_reg);
 315                 v &= ~dd->freqsel_mask;
 316                 v |= freqsel << __ffs(dd->freqsel_mask);
 317                 omap2_clk_writel(v, clk, dd->control_reg);
 318         }
 319
 320         /* Set DPLL multiplier, divider */
 321         v = omap2_clk_readl(clk, dd->mult_div1_reg);
 322
 323         /* Handle Duty Cycle Correction */
 324         if (dd->dcc_mask) {
 325                 if (dd->last_rounded_rate >= dd->dcc_rate)
 326                         v |= dd->dcc_mask; /* Enable DCC */
 327                 else
 328                         v &= ~dd->dcc_mask; /* Disable DCC */
 329         }
 330
 331         v &= ~(dd->mult_mask | dd->div1_mask);
 332         v |= dd->last_rounded_m << __ffs(dd->mult_mask);
 333         v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
 334
 335         /* Configure dco and sd_div for dplls that have these fields */
 336         if (dd->dco_mask) {
 337                 _lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n);
 338                 v &= ~(dd->dco_mask);
 339                 v |= dco << __ffs(dd->dco_mask);
 340         }
 341         if (dd->sddiv_mask) {
 342                 _lookup_sddiv(clk, &sd_div, dd->last_rounded_m,
 343                               dd->last_rounded_n);
 344                 v &= ~(dd->sddiv_mask);
 345                 v |= sd_div << __ffs(dd->sddiv_mask);
 346         }
 347
 348         omap2_clk_writel(v, clk, dd->mult_div1_reg);
 349
 350         /* Set 4X multiplier and low-power mode */
 351         if (dd->m4xen_mask || dd->lpmode_mask) {
 352                 v = omap2_clk_readl(clk, dd->control_reg);
 353
 354                 if (dd->m4xen_mask) {
 355                         if (dd->last_rounded_m4xen)
 356                                 v |= dd->m4xen_mask;
 357                         else
 358                                 v &= ~dd->m4xen_mask;
 359                 }
 360
 361                 if (dd->lpmode_mask) {
 362                         if (dd->last_rounded_lpmode)
 363                                 v |= dd->lpmode_mask;
 364                         else
 365                                 v &= ~dd->lpmode_mask;
 366                 }
 367
 368                 omap2_clk_writel(v, clk, dd->control_reg);
 369         }
 370
 371         /* We let the clock framework set the other output dividers later */
 372
 373         /* REVISIT: Set ramp-up delay? */
 374
 375         _omap3_noncore_dpll_lock(clk);
 376
 377         return 0;
 378 }
 379
 380 /* Public functions */
 381
 382 /**
 383  * omap3_dpll_recalc - recalculate DPLL rate
 384  * @clk: DPLL struct clk
 385  *
 386  * Recalculate and propagate the DPLL rate.
 387  */
 388 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)
 389 {
 390         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
 391
 392         return omap2_get_dpll_rate(clk);
 393 }
 394
 395 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
 396
 397 /**
 398  * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
 399  * @clk: pointer to a DPLL struct clk
 400  *
 401  * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
 402  * The choice of modes depends on the DPLL's programmed rate: if it is
 403  * the same as the DPLL's parent clock, it will enter bypass;
 404  * otherwise, it will enter lock.  This code will wait for the DPLL to
 405  * indicate readiness before returning, unless the DPLL takes too long
 406  * to enter the target state.  Intended to be used as the struct clk's
 407  * enable function.  If DPLL3 was passed in, or the DPLL does not
 408  * support low-power stop, or if the DPLL took too long to enter
 409  * bypass or lock, return -EINVAL; otherwise, return 0.
 410  */
 411 int omap3_noncore_dpll_enable(struct clk_hw *hw)
 412 {
 413         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
 414         int r;
 415         struct dpll_data *dd;
 416         struct clk *parent;
 417
 418         dd = clk->dpll_data;
 419         if (!dd)
 420                 return -EINVAL;
 421
 422         if (clk->clkdm) {
 423                 r = clkdm_clk_enable(clk->clkdm, hw->clk);
 424                 if (r) {
 425                         WARN(1,
 426                              "%s: could not enable %s's clockdomain %s: %d\n",
 427                              __func__, __clk_get_name(hw->clk),
 428                              clk->clkdm->name, r);
 429                         return r;
 430                 }
 431         }
 432
 433         parent = __clk_get_parent(hw->clk);
 434
 435         if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) {
 436                 WARN_ON(parent != dd->clk_bypass);
 437                 r = _omap3_noncore_dpll_bypass(clk);
 438         } else {
 439                 WARN_ON(parent != dd->clk_ref);
 440                 r = _omap3_noncore_dpll_lock(clk);
 441         }
 442
 443         return r;
 444 }
 445
 446 /**
 447  * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
 448  * @clk: pointer to a DPLL struct clk
 449  *
 450  * Instructs a non-CORE DPLL to enter low-power stop.  This function is
 451  * intended for use in struct clkops.  No return value.
 452  */
 453 void omap3_noncore_dpll_disable(struct clk_hw *hw)
 454 {
 455         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
 456
 457         _omap3_noncore_dpll_stop(clk);
 458         if (clk->clkdm)
 459                 clkdm_clk_disable(clk->clkdm, hw->clk);
 460 }
 461
 462
 463 /* Non-CORE DPLL rate set code */
 464
 465 /**
 466  * omap3_noncore_dpll_set_rate - set non-core DPLL rate
 467  * @clk: struct clk * of DPLL to set
 468  * @rate: rounded target rate
 469  *
 470  * Set the DPLL CLKOUT to the target rate.  If the DPLL can enter
 471  * low-power bypass, and the target rate is the bypass source clock
 472  * rate, then configure the DPLL for bypass.  Otherwise, round the
 473  * target rate if it hasn't been done already, then program and lock
 474  * the DPLL.  Returns -EINVAL upon error, or 0 upon success.
 475  */
 476 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
 477                                         unsigned long parent_rate)
 478 {
 479         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
 480         struct clk *new_parent = NULL;
 481         u16 freqsel = 0;
 482         struct dpll_data *dd;
 483         int ret;
 484
 485         if (!hw || !rate)
 486                 return -EINVAL;
 487
 488         dd = clk->dpll_data;
 489         if (!dd)
 490                 return -EINVAL;
 491
 492         if (__clk_get_rate(dd->clk_bypass) == rate &&
 493             (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
 494                 pr_debug("%s: %s: set rate: entering bypass.\n",
 495                          __func__, __clk_get_name(hw->clk));
 496
 497                 __clk_prepare(dd->clk_bypass);
 498                 clk_enable(dd->clk_bypass);
 499                 ret = _omap3_noncore_dpll_bypass(clk);
 500                 if (!ret)
 501                         new_parent = dd->clk_bypass;
 502                 clk_disable(dd->clk_bypass);
 503                 __clk_unprepare(dd->clk_bypass);
 504         } else {
 505                 __clk_prepare(dd->clk_ref);
 506                 clk_enable(dd->clk_ref);
 507
 508                 if (dd->last_rounded_rate != rate)
 509                         rate = __clk_round_rate(hw->clk, rate);
 510
 511                 if (dd->last_rounded_rate == 0)
 512                         return -EINVAL;
 513
 514                 /* Freqsel is available only on OMAP343X devices */
 515                 if (cpu_is_omap343x()) {
 516                         freqsel = _omap3_dpll_compute_freqsel(clk,
 517                                                 dd->last_rounded_n);
 518                         WARN_ON(!freqsel);
 519                 }
 520
 521                 pr_debug("%s: %s: set rate: locking rate to %lu.\n",
 522                          __func__, __clk_get_name(hw->clk), rate);
 523
 524                 ret = omap3_noncore_dpll_program(clk, freqsel);
 525                 if (!ret)
 526                         new_parent = dd->clk_ref;
 527                 clk_disable(dd->clk_ref);
 528                 __clk_unprepare(dd->clk_ref);
 529         }
 530         /*
 531         * FIXME - this is all wrong.  common code handles reparenting and
 532         * migrating prepare/enable counts.  dplls should be a multiplexer
 533         * clock and this should be a set_parent operation so that all of that
 534         * stuff is inherited for free
 535         */
 536
 537         if (!ret && clk_get_parent(hw->clk) != new_parent)
 538                 __clk_reparent(hw->clk, new_parent);
 539
 540         return 0;
 541 }
 542
 543 /* DPLL autoidle read/set code */
 544
 545 /**
 546  * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
 547  * @clk: struct clk * of the DPLL to read
 548  *
 549  * Return the DPLL's autoidle bits, shifted down to bit 0.  Returns
 550  * -EINVAL if passed a null pointer or if the struct clk does not
 551  * appear to refer to a DPLL.
 552  */
 553 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
 554 {
 555         const struct dpll_data *dd;
 556         u32 v;
 557
 558         if (!clk || !clk->dpll_data)
 559                 return -EINVAL;
 560
 561         dd = clk->dpll_data;
 562
 563         if (!dd->autoidle_reg)
 564                 return -EINVAL;
 565
 566         v = omap2_clk_readl(clk, dd->autoidle_reg);
 567         v &= dd->autoidle_mask;
 568         v >>= __ffs(dd->autoidle_mask);
 569
 570         return v;
 571 }
 572
 573 /**
 574  * omap3_dpll_allow_idle - enable DPLL autoidle bits
 575  * @clk: struct clk * of the DPLL to operate on
 576  *
 577  * Enable DPLL automatic idle control.  This automatic idle mode
 578  * switching takes effect only when the DPLL is locked, at least on
 579  * OMAP3430.  The DPLL will enter low-power stop when its downstream
 580  * clocks are gated.  No return value.
 581  */
 582 void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
 583 {
 584         const struct dpll_data *dd;
 585         u32 v;
 586
 587         if (!clk || !clk->dpll_data)
 588                 return;
 589
 590         dd = clk->dpll_data;
 591
 592         if (!dd->autoidle_reg)
 593                 return;
 594
 595         /*
 596          * REVISIT: CORE DPLL can optionally enter low-power bypass
 597          * by writing 0x5 instead of 0x1.  Add some mechanism to
 598          * optionally enter this mode.
 599          */
 600         v = omap2_clk_readl(clk, dd->autoidle_reg);
 601         v &= ~dd->autoidle_mask;
 602         v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
 603         omap2_clk_writel(v, clk, dd->autoidle_reg);
 604
 605 }
 606
 607 /**
 608  * omap3_dpll_deny_idle - prevent DPLL from automatically idling
 609  * @clk: struct clk * of the DPLL to operate on
 610  *
 611  * Disable DPLL automatic idle control.  No return value.
 612  */
 613 void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
 614 {
 615         const struct dpll_data *dd;
 616         u32 v;
 617
 618         if (!clk || !clk->dpll_data)
 619                 return;
 620
 621         dd = clk->dpll_data;
 622
 623         if (!dd->autoidle_reg)
 624                 return;
 625
 626         v = omap2_clk_readl(clk, dd->autoidle_reg);
 627         v &= ~dd->autoidle_mask;
 628         v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
 629         omap2_clk_writel(v, clk, dd->autoidle_reg);
 630
 631 }
 632
 633 /* Clock control for DPLL outputs */
 634
 635 /* Find the parent DPLL for the given clkoutx2 clock */
 636 static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw)
 637 {
 638         struct clk_hw_omap *pclk = NULL;
 639         struct clk *parent;
 640
 641         /* Walk up the parents of clk, looking for a DPLL */
 642         do {
 643                 do {
 644                         parent = __clk_get_parent(hw->clk);
 645                         hw = __clk_get_hw(parent);
 646                 } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC));
 647                 if (!hw)
 648                         break;
 649                 pclk = to_clk_hw_omap(hw);
 650         } while (pclk && !pclk->dpll_data);
 651
 652         /* clk does not have a DPLL as a parent?  error in the clock data */
 653         if (!pclk) {
 654                 WARN_ON(1);
 655                 return NULL;
 656         }
 657
 658         return pclk;
 659 }
 660
 661 /**
 662  * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
 663  * @clk: DPLL output struct clk
 664  *
 665  * Using parent clock DPLL data, look up DPLL state.  If locked, set our
 666  * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
 667  */
 668 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 669                                     unsigned long parent_rate)
 670 {
 671         const struct dpll_data *dd;
 672         unsigned long rate;
 673         u32 v;
 674         struct clk_hw_omap *pclk = NULL;
 675
 676         if (!parent_rate)
 677                 return 0;
 678
 679         pclk = omap3_find_clkoutx2_dpll(hw);
 680
 681         if (!pclk)
 682                 return 0;
 683
 684         dd = pclk->dpll_data;
 685
 686         WARN_ON(!dd->enable_mask);
 687
 688         v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask;
 689         v >>= __ffs(dd->enable_mask);
 690         if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
 691                 rate = parent_rate;
 692         else
 693                 rate = parent_rate * 2;
 694         return rate;
 695 }
 696
 697 int omap3_clkoutx2_set_rate(struct clk_hw *hw, unsigned long rate,
 698                                         unsigned long parent_rate)
 699 {
 700         return 0;
 701 }
 702
 703 long omap3_clkoutx2_round_rate(struct clk_hw *hw, unsigned long rate,
 704                 unsigned long *prate)
 705 {
 706         const struct dpll_data *dd;
 707         u32 v;
 708         struct clk_hw_omap *pclk = NULL;
 709
 710         if (!*prate)
 711                 return 0;
 712
 713         pclk = omap3_find_clkoutx2_dpll(hw);
 714
 715         if (!pclk)
 716                 return 0;
 717
 718         dd = pclk->dpll_data;
 719
 720         /* TYPE J does not have a clkoutx2 */
 721         if (dd->flags & DPLL_J_TYPE) {
 722                 *prate = __clk_round_rate(__clk_get_parent(pclk->hw.clk), rate);
 723                 return *prate;
 724         }
 725
 726         WARN_ON(!dd->enable_mask);
 727
 728         v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask;
 729         v >>= __ffs(dd->enable_mask);
 730
 731         /* If in bypass, the rate is fixed to the bypass rate*/
 732         if (v != OMAP3XXX_EN_DPLL_LOCKED)
 733                 return *prate;
 734
 735         if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
 736                 unsigned long best_parent;
 737
 738                 best_parent = (rate / 2);
 739                 *prate = __clk_round_rate(__clk_get_parent(hw->clk),
 740                                 best_parent);
 741         }
 742
 743         return *prate * 2;
 744 }
 745
 746 /* OMAP3/4 non-CORE DPLL clkops */
 747 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
 748         .allow_idle     = omap3_dpll_allow_idle,
 749         .deny_idle      = omap3_dpll_deny_idle,
 750 };