arch/arm/mach-omap2/dpll3xxx.c

   1 /*
   2  * OMAP3/4 - specific DPLL control functions
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * Testing and integration fixes by Jouni Högander
   9  *
  10  * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
  11  * Menon
  12  *
  13  * Parts of this code are based on code written by
  14  * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/device.h>
  23 #include <linux/list.h>
  24 #include <linux/errno.h>
  25 #include <linux/delay.h>
  26 #include <linux/clk.h>
  27 #include <linux/io.h>
  28 #include <linux/bitops.h>
  29 #include <linux/clkdev.h>
  30
  31 #include "soc.h"
  32 #include "clockdomain.h"
  33 #include "clock.h"
  34 #include "cm2xxx_3xxx.h"
  35 #include "cm-regbits-34xx.h"
  36
  37 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
  38 #define DPLL_AUTOIDLE_DISABLE                   0x0
  39 #define DPLL_AUTOIDLE_LOW_POWER_STOP            0x1
  40
  41 #define MAX_DPLL_WAIT_TRIES             1000000
  42
  43 /* Private functions */
  44
  45 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
  46 static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
  47 {
  48         const struct dpll_data *dd;
  49         u32 v;
  50
  51         dd = clk->dpll_data;
  52
  53         v = __raw_readl(dd->control_reg);
  54         v &= ~dd->enable_mask;
  55         v |= clken_bits << __ffs(dd->enable_mask);
  56         __raw_writel(v, dd->control_reg);
  57 }
  58
  59 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
  60 static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
  61 {
  62         const struct dpll_data *dd;
  63         int i = 0;
  64         int ret = -EINVAL;
  65         const char *clk_name;
  66
  67         dd = clk->dpll_data;
  68         clk_name = __clk_get_name(clk->hw.clk);
  69
  70         state <<= __ffs(dd->idlest_mask);
  71
  72         while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
  73                i < MAX_DPLL_WAIT_TRIES) {
  74                 i++;
  75                 udelay(1);
  76         }
  77
  78         if (i == MAX_DPLL_WAIT_TRIES) {
  79                 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
  80                        clk_name, (state) ? "locked" : "bypassed");
  81         } else {
  82                 pr_debug("clock: %s transition to '%s' in %d loops\n",
  83                          clk_name, (state) ? "locked" : "bypassed", i);
  84
  85                 ret = 0;
  86         }
  87
  88         return ret;
  89 }
  90
  91 /* From 3430 TRM ES2 4.7.6.2 */
  92 static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
  93 {
  94         unsigned long fint;
  95         u16 f = 0;
  96
  97         fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;
  98
  99         pr_debug("clock: fint is %lu\n", fint);
 100
 101         if (fint >= 750000 && fint <= 1000000)
 102                 f = 0x3;
 103         else if (fint > 1000000 && fint <= 1250000)
 104                 f = 0x4;
 105         else if (fint > 1250000 && fint <= 1500000)
 106                 f = 0x5;
 107         else if (fint > 1500000 && fint <= 1750000)
 108                 f = 0x6;
 109         else if (fint > 1750000 && fint <= 2100000)
 110                 f = 0x7;
 111         else if (fint > 7500000 && fint <= 10000000)
 112                 f = 0xB;
 113         else if (fint > 10000000 && fint <= 12500000)
 114                 f = 0xC;
 115         else if (fint > 12500000 && fint <= 15000000)
 116                 f = 0xD;
 117         else if (fint > 15000000 && fint <= 17500000)
 118                 f = 0xE;
 119         else if (fint > 17500000 && fint <= 21000000)
 120                 f = 0xF;
 121         else
 122                 pr_debug("clock: unknown freqsel setting for %d\n", n);
 123
 124         return f;
 125 }
 126
 127 /*
 128  * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
 129  * @clk: pointer to a DPLL struct clk
 130  *
 131  * Instructs a non-CORE DPLL to lock.  Waits for the DPLL to report
 132  * readiness before returning.  Will save and restore the DPLL's
 133  * autoidle state across the enable, per the CDP code.  If the DPLL
 134  * locked successfully, return 0; if the DPLL did not lock in the time
 135  * allotted, or DPLL3 was passed in, return -EINVAL.
 136  */
 137 static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
 138 {
 139         const struct dpll_data *dd;
 140         u8 ai;
 141         u8 state = 1;
 142         int r = 0;
 143
 144         pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk));
 145
 146         dd = clk->dpll_data;
 147         state <<= __ffs(dd->idlest_mask);
 148
 149         /* Check if already locked */
 150         if ((__raw_readl(dd->idlest_reg) & dd->idlest_mask) == state)
 151                 goto done;
 152
 153         ai = omap3_dpll_autoidle_read(clk);
 154
 155         if (ai)
 156                 omap3_dpll_deny_idle(clk);
 157
 158         _omap3_dpll_write_clken(clk, DPLL_LOCKED);
 159
 160         r = _omap3_wait_dpll_status(clk, 1);
 161
 162         if (ai)
 163                 omap3_dpll_allow_idle(clk);
 164
 165 done:
 166         return r;
 167 }
 168
 169 /*
 170  * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
 171  * @clk: pointer to a DPLL struct clk
 172  *
 173  * Instructs a non-CORE DPLL to enter low-power bypass mode.  In
 174  * bypass mode, the DPLL's rate is set equal to its parent clock's
 175  * rate.  Waits for the DPLL to report readiness before returning.
 176  * Will save and restore the DPLL's autoidle state across the enable,
 177  * per the CDP code.  If the DPLL entered bypass mode successfully,
 178  * return 0; if the DPLL did not enter bypass in the time allotted, or
 179  * DPLL3 was passed in, or the DPLL does not support low-power bypass,
 180  * return -EINVAL.
 181  */
 182 static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
 183 {
 184         int r;
 185         u8 ai;
 186
 187         if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
 188                 return -EINVAL;
 189
 190         pr_debug("clock: configuring DPLL %s for low-power bypass\n",
 191                  __clk_get_name(clk->hw.clk));
 192
 193         ai = omap3_dpll_autoidle_read(clk);
 194
 195         _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
 196
 197         r = _omap3_wait_dpll_status(clk, 0);
 198
 199         if (ai)
 200                 omap3_dpll_allow_idle(clk);
 201
 202         return r;
 203 }
 204
 205 /*
 206  * _omap3_noncore_dpll_stop - instruct a DPLL to stop
 207  * @clk: pointer to a DPLL struct clk
 208  *
 209  * Instructs a non-CORE DPLL to enter low-power stop. Will save and
 210  * restore the DPLL's autoidle state across the stop, per the CDP
 211  * code.  If DPLL3 was passed in, or the DPLL does not support
 212  * low-power stop, return -EINVAL; otherwise, return 0.
 213  */
 214 static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)
 215 {
 216         u8 ai;
 217
 218         if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
 219                 return -EINVAL;
 220
 221         pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk));
 222
 223         ai = omap3_dpll_autoidle_read(clk);
 224
 225         _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
 226
 227         if (ai)
 228                 omap3_dpll_allow_idle(clk);
 229
 230         return 0;
 231 }
 232
 233 /**
 234  * _lookup_dco - Lookup DCO used by j-type DPLL
 235  * @clk: pointer to a DPLL struct clk
 236  * @dco: digital control oscillator selector
 237  * @m: DPLL multiplier to set
 238  * @n: DPLL divider to set
 239  *
 240  * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
 241  *
 242  * XXX This code is not needed for 3430/AM35xx; can it be optimized
 243  * out in non-multi-OMAP builds for those chips?
 244  */
 245 static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n)
 246 {
 247         unsigned long fint, clkinp; /* watch out for overflow */
 248
 249         clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));
 250         fint = (clkinp / n) * m;
 251
 252         if (fint < 1000000000)
 253                 *dco = 2;
 254         else
 255                 *dco = 4;
 256 }
 257
 258 /**
 259  * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
 260  * @clk: pointer to a DPLL struct clk
 261  * @sd_div: target sigma-delta divider
 262  * @m: DPLL multiplier to set
 263  * @n: DPLL divider to set
 264  *
 265  * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
 266  *
 267  * XXX This code is not needed for 3430/AM35xx; can it be optimized
 268  * out in non-multi-OMAP builds for those chips?
 269  */
 270 static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
 271 {
 272         unsigned long clkinp, sd; /* watch out for overflow */
 273         int mod1, mod2;
 274
 275         clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));
 276
 277         /*
 278          * target sigma-delta to near 250MHz
 279          * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
 280          */
 281         clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
 282         mod1 = (clkinp * m) % (250 * n);
 283         sd = (clkinp * m) / (250 * n);
 284         mod2 = sd % 10;
 285         sd /= 10;
 286
 287         if (mod1 || mod2)
 288                 sd++;
 289         *sd_div = sd;
 290 }
 291
 292 /*
 293  * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
 294  * @clk: struct clk * of DPLL to set
 295  * @m: DPLL multiplier to set
 296  * @n: DPLL divider to set
 297  * @freqsel: FREQSEL value to set
 298  *
 299  * Program the DPLL with the supplied M, N values, and wait for the DPLL to
 300  * lock..  Returns -EINVAL upon error, or 0 upon success.
 301  */
 302 static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 m, u8 n,
 303                                       u16 freqsel)
 304 {
 305         struct dpll_data *dd = clk->dpll_data;
 306         u8 dco, sd_div;
 307         u32 v;
 308
 309         /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
 310         _omap3_noncore_dpll_bypass(clk);
 311
 312         /*
 313          * Set jitter correction. No jitter correction for OMAP4 and 3630
 314          * since freqsel field is no longer present
 315          */
 316         if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
 317                 v = __raw_readl(dd->control_reg);
 318                 v &= ~dd->freqsel_mask;
 319                 v |= freqsel << __ffs(dd->freqsel_mask);
 320                 __raw_writel(v, dd->control_reg);
 321         }
 322
 323         /* Set DPLL multiplier, divider */
 324         v = __raw_readl(dd->mult_div1_reg);
 325         v &= ~(dd->mult_mask | dd->div1_mask);
 326         v |= m << __ffs(dd->mult_mask);
 327         v |= (n - 1) << __ffs(dd->div1_mask);
 328
 329         /* Configure dco and sd_div for dplls that have these fields */
 330         if (dd->dco_mask) {
 331                 _lookup_dco(clk, &dco, m, n);
 332                 v &= ~(dd->dco_mask);
 333                 v |= dco << __ffs(dd->dco_mask);
 334         }
 335         if (dd->sddiv_mask) {
 336                 _lookup_sddiv(clk, &sd_div, m, n);
 337                 v &= ~(dd->sddiv_mask);
 338                 v |= sd_div << __ffs(dd->sddiv_mask);
 339         }
 340
 341         __raw_writel(v, dd->mult_div1_reg);
 342
 343         /* We let the clock framework set the other output dividers later */
 344
 345         /* REVISIT: Set ramp-up delay? */
 346
 347         _omap3_noncore_dpll_lock(clk);
 348
 349         return 0;
 350 }
 351
 352 /* Public functions */
 353
 354 /**
 355  * omap3_dpll_recalc - recalculate DPLL rate
 356  * @clk: DPLL struct clk
 357  *
 358  * Recalculate and propagate the DPLL rate.
 359  */
 360 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)
 361 {
 362         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
 363
 364         return omap2_get_dpll_rate(clk);
 365 }
 366
 367 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
 368
 369 /**
 370  * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
 371  * @clk: pointer to a DPLL struct clk
 372  *
 373  * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
 374  * The choice of modes depends on the DPLL's programmed rate: if it is
 375  * the same as the DPLL's parent clock, it will enter bypass;
 376  * otherwise, it will enter lock.  This code will wait for the DPLL to
 377  * indicate readiness before returning, unless the DPLL takes too long
 378  * to enter the target state.  Intended to be used as the struct clk's
 379  * enable function.  If DPLL3 was passed in, or the DPLL does not
 380  * support low-power stop, or if the DPLL took too long to enter
 381  * bypass or lock, return -EINVAL; otherwise, return 0.
 382  */
 383 int omap3_noncore_dpll_enable(struct clk_hw *hw)
 384 {
 385         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
 386         int r;
 387         struct dpll_data *dd;
 388         struct clk *parent;
 389
 390         dd = clk->dpll_data;
 391         if (!dd)
 392                 return -EINVAL;
 393
 394         if (clk->clkdm) {
 395                 r = clkdm_clk_enable(clk->clkdm, hw->clk);
 396                 if (r) {
 397                         WARN(1,
 398                              "%s: could not enable %s's clockdomain %s: %d\n",
 399                              __func__, __clk_get_name(hw->clk),
 400                              clk->clkdm->name, r);
 401                         return r;
 402                 }
 403         }
 404
 405         parent = __clk_get_parent(hw->clk);
 406
 407         if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) {
 408                 WARN_ON(parent != dd->clk_bypass);
 409                 r = _omap3_noncore_dpll_bypass(clk);
 410         } else {
 411                 WARN_ON(parent != dd->clk_ref);
 412                 r = _omap3_noncore_dpll_lock(clk);
 413         }
 414
 415         return r;
 416 }
 417
 418 /**
 419  * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
 420  * @clk: pointer to a DPLL struct clk
 421  *
 422  * Instructs a non-CORE DPLL to enter low-power stop.  This function is
 423  * intended for use in struct clkops.  No return value.
 424  */
 425 void omap3_noncore_dpll_disable(struct clk_hw *hw)
 426 {
 427         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
 428
 429         _omap3_noncore_dpll_stop(clk);
 430         if (clk->clkdm)
 431                 clkdm_clk_disable(clk->clkdm, hw->clk);
 432 }
 433
 434
 435 /* Non-CORE DPLL rate set code */
 436
 437 /**
 438  * omap3_noncore_dpll_set_rate - set non-core DPLL rate
 439  * @clk: struct clk * of DPLL to set
 440  * @rate: rounded target rate
 441  *
 442  * Set the DPLL CLKOUT to the target rate.  If the DPLL can enter
 443  * low-power bypass, and the target rate is the bypass source clock
 444  * rate, then configure the DPLL for bypass.  Otherwise, round the
 445  * target rate if it hasn't been done already, then program and lock
 446  * the DPLL.  Returns -EINVAL upon error, or 0 upon success.
 447  */
 448 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
 449                                         unsigned long parent_rate)
 450 {
 451         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
 452         struct clk *new_parent = NULL;
 453         u16 freqsel = 0;
 454         struct dpll_data *dd;
 455         int ret;
 456
 457         if (!hw || !rate)
 458                 return -EINVAL;
 459
 460         dd = clk->dpll_data;
 461         if (!dd)
 462                 return -EINVAL;
 463
 464         __clk_prepare(dd->clk_bypass);
 465         clk_enable(dd->clk_bypass);
 466         __clk_prepare(dd->clk_ref);
 467         clk_enable(dd->clk_ref);
 468
 469         if (__clk_get_rate(dd->clk_bypass) == rate &&
 470             (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
 471                 pr_debug("%s: %s: set rate: entering bypass.\n",
 472                          __func__, __clk_get_name(hw->clk));
 473
 474                 ret = _omap3_noncore_dpll_bypass(clk);
 475                 if (!ret)
 476                         new_parent = dd->clk_bypass;
 477         } else {
 478                 if (dd->last_rounded_rate != rate)
 479                         rate = __clk_round_rate(hw->clk, rate);
 480
 481                 if (dd->last_rounded_rate == 0)
 482                         return -EINVAL;
 483
 484                 /* No freqsel on OMAP4 and OMAP3630 */
 485                 if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
 486                         freqsel = _omap3_dpll_compute_freqsel(clk,
 487                                                 dd->last_rounded_n);
 488                         if (!freqsel)
 489                                 WARN_ON(1);
 490                 }
 491
 492                 pr_debug("%s: %s: set rate: locking rate to %lu.\n",
 493                          __func__, __clk_get_name(hw->clk), rate);
 494
 495                 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
 496                                                 dd->last_rounded_n, freqsel);
 497                 if (!ret)
 498                         new_parent = dd->clk_ref;
 499         }
 500         /*
 501         * FIXME - this is all wrong.  common code handles reparenting and
 502         * migrating prepare/enable counts.  dplls should be a multiplexer
 503         * clock and this should be a set_parent operation so that all of that
 504         * stuff is inherited for free
 505         */
 506
 507         if (!ret)
 508                 __clk_reparent(hw->clk, new_parent);
 509
 510         clk_disable(dd->clk_ref);
 511         __clk_unprepare(dd->clk_ref);
 512         clk_disable(dd->clk_bypass);
 513         __clk_unprepare(dd->clk_bypass);
 514
 515         return 0;
 516 }
 517
 518 /* DPLL autoidle read/set code */
 519
 520 /**
 521  * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
 522  * @clk: struct clk * of the DPLL to read
 523  *
 524  * Return the DPLL's autoidle bits, shifted down to bit 0.  Returns
 525  * -EINVAL if passed a null pointer or if the struct clk does not
 526  * appear to refer to a DPLL.
 527  */
 528 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
 529 {
 530         const struct dpll_data *dd;
 531         u32 v;
 532
 533         if (!clk || !clk->dpll_data)
 534                 return -EINVAL;
 535
 536         dd = clk->dpll_data;
 537
 538         if (!dd->autoidle_reg)
 539                 return -EINVAL;
 540
 541         v = __raw_readl(dd->autoidle_reg);
 542         v &= dd->autoidle_mask;
 543         v >>= __ffs(dd->autoidle_mask);
 544
 545         return v;
 546 }
 547
 548 /**
 549  * omap3_dpll_allow_idle - enable DPLL autoidle bits
 550  * @clk: struct clk * of the DPLL to operate on
 551  *
 552  * Enable DPLL automatic idle control.  This automatic idle mode
 553  * switching takes effect only when the DPLL is locked, at least on
 554  * OMAP3430.  The DPLL will enter low-power stop when its downstream
 555  * clocks are gated.  No return value.
 556  */
 557 void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
 558 {
 559         const struct dpll_data *dd;
 560         u32 v;
 561
 562         if (!clk || !clk->dpll_data)
 563                 return;
 564
 565         dd = clk->dpll_data;
 566
 567         if (!dd->autoidle_reg)
 568                 return;
 569
 570         /*
 571          * REVISIT: CORE DPLL can optionally enter low-power bypass
 572          * by writing 0x5 instead of 0x1.  Add some mechanism to
 573          * optionally enter this mode.
 574          */
 575         v = __raw_readl(dd->autoidle_reg);
 576         v &= ~dd->autoidle_mask;
 577         v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
 578         __raw_writel(v, dd->autoidle_reg);
 579
 580 }
 581
 582 /**
 583  * omap3_dpll_deny_idle - prevent DPLL from automatically idling
 584  * @clk: struct clk * of the DPLL to operate on
 585  *
 586  * Disable DPLL automatic idle control.  No return value.
 587  */
 588 void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
 589 {
 590         const struct dpll_data *dd;
 591         u32 v;
 592
 593         if (!clk || !clk->dpll_data)
 594                 return;
 595
 596         dd = clk->dpll_data;
 597
 598         if (!dd->autoidle_reg)
 599                 return;
 600
 601         v = __raw_readl(dd->autoidle_reg);
 602         v &= ~dd->autoidle_mask;
 603         v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
 604         __raw_writel(v, dd->autoidle_reg);
 605
 606 }
 607
 608 /* Clock control for DPLL outputs */
 609
 610 /**
 611  * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
 612  * @clk: DPLL output struct clk
 613  *
 614  * Using parent clock DPLL data, look up DPLL state.  If locked, set our
 615  * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
 616  */
 617 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 618                                     unsigned long parent_rate)
 619 {
 620         const struct dpll_data *dd;
 621         unsigned long rate;
 622         u32 v;
 623         struct clk_hw_omap *pclk = NULL;
 624         struct clk *parent;
 625
 626         /* Walk up the parents of clk, looking for a DPLL */
 627         do {
 628                 do {
 629                         parent = __clk_get_parent(hw->clk);
 630                         hw = __clk_get_hw(parent);
 631                 } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC));
 632                 if (!hw)
 633                         break;
 634                 pclk = to_clk_hw_omap(hw);
 635         } while (pclk && !pclk->dpll_data);
 636
 637         /* clk does not have a DPLL as a parent?  error in the clock data */
 638         if (!pclk) {
 639                 WARN_ON(1);
 640                 return 0;
 641         }
 642
 643         dd = pclk->dpll_data;
 644
 645         WARN_ON(!dd->enable_mask);
 646
 647         v = __raw_readl(dd->control_reg) & dd->enable_mask;
 648         v >>= __ffs(dd->enable_mask);
 649         if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
 650                 rate = parent_rate;
 651         else
 652                 rate = parent_rate * 2;
 653         return rate;
 654 }
 655
 656 /* OMAP3/4 non-CORE DPLL clkops */
 657 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
 658         .allow_idle     = omap3_dpll_allow_idle,
 659         .deny_idle      = omap3_dpll_deny_idle,
 660 };