2 * OMAP3/4 - specific DPLL control functions
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
10 * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
13 * Parts of this code are based on code written by
14 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/kernel.h>
22 #include <linux/device.h>
23 #include <linux/list.h>
24 #include <linux/errno.h>
25 #include <linux/delay.h>
26 #include <linux/clk.h>
28 #include <linux/bitops.h>
29 #include <linux/clkdev.h>
33 #include "cm2xxx_3xxx.h"
34 #include "cm-regbits-34xx.h"
36 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
37 #define DPLL_AUTOIDLE_DISABLE 0x0
38 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
40 #define MAX_DPLL_WAIT_TRIES 1000000
42 /* Private functions */
44 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
45 static void _omap3_dpll_write_clken(struct clk
*clk
, u8 clken_bits
)
47 const struct dpll_data
*dd
;
52 v
= __raw_readl(dd
->control_reg
);
53 v
&= ~dd
->enable_mask
;
54 v
|= clken_bits
<< __ffs(dd
->enable_mask
);
55 __raw_writel(v
, dd
->control_reg
);
58 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
59 static int _omap3_wait_dpll_status(struct clk
*clk
, u8 state
)
61 const struct dpll_data
*dd
;
67 clk_name
= __clk_get_name(clk
);
69 state
<<= __ffs(dd
->idlest_mask
);
71 while (((__raw_readl(dd
->idlest_reg
) & dd
->idlest_mask
) != state
) &&
72 i
< MAX_DPLL_WAIT_TRIES
) {
77 if (i
== MAX_DPLL_WAIT_TRIES
) {
78 printk(KERN_ERR
"clock: %s failed transition to '%s'\n",
79 clk_name
, (state
) ? "locked" : "bypassed");
81 pr_debug("clock: %s transition to '%s' in %d loops\n",
82 clk_name
, (state
) ? "locked" : "bypassed", i
);
90 /* From 3430 TRM ES2 4.7.6.2 */
91 static u16
_omap3_dpll_compute_freqsel(struct clk
*clk
, u8 n
)
96 fint
= __clk_get_rate(clk
->dpll_data
->clk_ref
) / n
;
98 pr_debug("clock: fint is %lu\n", fint
);
100 if (fint
>= 750000 && fint
<= 1000000)
102 else if (fint
> 1000000 && fint
<= 1250000)
104 else if (fint
> 1250000 && fint
<= 1500000)
106 else if (fint
> 1500000 && fint
<= 1750000)
108 else if (fint
> 1750000 && fint
<= 2100000)
110 else if (fint
> 7500000 && fint
<= 10000000)
112 else if (fint
> 10000000 && fint
<= 12500000)
114 else if (fint
> 12500000 && fint
<= 15000000)
116 else if (fint
> 15000000 && fint
<= 17500000)
118 else if (fint
> 17500000 && fint
<= 21000000)
121 pr_debug("clock: unknown freqsel setting for %d\n", n
);
127 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
128 * @clk: pointer to a DPLL struct clk
130 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
131 * readiness before returning. Will save and restore the DPLL's
132 * autoidle state across the enable, per the CDP code. If the DPLL
133 * locked successfully, return 0; if the DPLL did not lock in the time
134 * allotted, or DPLL3 was passed in, return -EINVAL.
136 static int _omap3_noncore_dpll_lock(struct clk
*clk
)
138 const struct dpll_data
*dd
;
143 pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk
));
146 state
<<= __ffs(dd
->idlest_mask
);
148 /* Check if already locked */
149 if ((__raw_readl(dd
->idlest_reg
) & dd
->idlest_mask
) == state
)
152 ai
= omap3_dpll_autoidle_read(clk
);
155 omap3_dpll_deny_idle(clk
);
157 _omap3_dpll_write_clken(clk
, DPLL_LOCKED
);
159 r
= _omap3_wait_dpll_status(clk
, 1);
162 omap3_dpll_allow_idle(clk
);
169 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
170 * @clk: pointer to a DPLL struct clk
172 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
173 * bypass mode, the DPLL's rate is set equal to its parent clock's
174 * rate. Waits for the DPLL to report readiness before returning.
175 * Will save and restore the DPLL's autoidle state across the enable,
176 * per the CDP code. If the DPLL entered bypass mode successfully,
177 * return 0; if the DPLL did not enter bypass in the time allotted, or
178 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
181 static int _omap3_noncore_dpll_bypass(struct clk
*clk
)
186 if (!(clk
->dpll_data
->modes
& (1 << DPLL_LOW_POWER_BYPASS
)))
189 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
190 __clk_get_name(clk
));
192 ai
= omap3_dpll_autoidle_read(clk
);
194 _omap3_dpll_write_clken(clk
, DPLL_LOW_POWER_BYPASS
);
196 r
= _omap3_wait_dpll_status(clk
, 0);
199 omap3_dpll_allow_idle(clk
);
205 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
206 * @clk: pointer to a DPLL struct clk
208 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
209 * restore the DPLL's autoidle state across the stop, per the CDP
210 * code. If DPLL3 was passed in, or the DPLL does not support
211 * low-power stop, return -EINVAL; otherwise, return 0.
213 static int _omap3_noncore_dpll_stop(struct clk
*clk
)
217 if (!(clk
->dpll_data
->modes
& (1 << DPLL_LOW_POWER_STOP
)))
220 pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk
));
222 ai
= omap3_dpll_autoidle_read(clk
);
224 _omap3_dpll_write_clken(clk
, DPLL_LOW_POWER_STOP
);
227 omap3_dpll_allow_idle(clk
);
233 * _lookup_dco - Lookup DCO used by j-type DPLL
234 * @clk: pointer to a DPLL struct clk
235 * @dco: digital control oscillator selector
236 * @m: DPLL multiplier to set
237 * @n: DPLL divider to set
239 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
241 * XXX This code is not needed for 3430/AM35xx; can it be optimized
242 * out in non-multi-OMAP builds for those chips?
244 static void _lookup_dco(struct clk
*clk
, u8
*dco
, u16 m
, u8 n
)
246 unsigned long fint
, clkinp
; /* watch out for overflow */
248 clkinp
= __clk_get_rate(__clk_get_parent(clk
));
249 fint
= (clkinp
/ n
) * m
;
251 if (fint
< 1000000000)
258 * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
259 * @clk: pointer to a DPLL struct clk
260 * @sd_div: target sigma-delta divider
261 * @m: DPLL multiplier to set
262 * @n: DPLL divider to set
264 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
266 * XXX This code is not needed for 3430/AM35xx; can it be optimized
267 * out in non-multi-OMAP builds for those chips?
269 static void _lookup_sddiv(struct clk
*clk
, u8
*sd_div
, u16 m
, u8 n
)
271 unsigned long clkinp
, sd
; /* watch out for overflow */
274 clkinp
= __clk_get_rate(__clk_get_parent(clk
));
277 * target sigma-delta to near 250MHz
278 * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
280 clkinp
/= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
281 mod1
= (clkinp
* m
) % (250 * n
);
282 sd
= (clkinp
* m
) / (250 * n
);
292 * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
293 * @clk: struct clk * of DPLL to set
294 * @m: DPLL multiplier to set
295 * @n: DPLL divider to set
296 * @freqsel: FREQSEL value to set
298 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
299 * lock.. Returns -EINVAL upon error, or 0 upon success.
301 static int omap3_noncore_dpll_program(struct clk
*clk
, u16 m
, u8 n
, u16 freqsel
)
303 struct dpll_data
*dd
= clk
->dpll_data
;
307 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
308 _omap3_noncore_dpll_bypass(clk
);
311 * Set jitter correction. No jitter correction for OMAP4 and 3630
312 * since freqsel field is no longer present
314 if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
315 v
= __raw_readl(dd
->control_reg
);
316 v
&= ~dd
->freqsel_mask
;
317 v
|= freqsel
<< __ffs(dd
->freqsel_mask
);
318 __raw_writel(v
, dd
->control_reg
);
321 /* Set DPLL multiplier, divider */
322 v
= __raw_readl(dd
->mult_div1_reg
);
323 v
&= ~(dd
->mult_mask
| dd
->div1_mask
);
324 v
|= m
<< __ffs(dd
->mult_mask
);
325 v
|= (n
- 1) << __ffs(dd
->div1_mask
);
327 /* Configure dco and sd_div for dplls that have these fields */
329 _lookup_dco(clk
, &dco
, m
, n
);
330 v
&= ~(dd
->dco_mask
);
331 v
|= dco
<< __ffs(dd
->dco_mask
);
333 if (dd
->sddiv_mask
) {
334 _lookup_sddiv(clk
, &sd_div
, m
, n
);
335 v
&= ~(dd
->sddiv_mask
);
336 v
|= sd_div
<< __ffs(dd
->sddiv_mask
);
339 __raw_writel(v
, dd
->mult_div1_reg
);
341 /* We let the clock framework set the other output dividers later */
343 /* REVISIT: Set ramp-up delay? */
345 _omap3_noncore_dpll_lock(clk
);
350 /* Public functions */
353 * omap3_dpll_recalc - recalculate DPLL rate
354 * @clk: DPLL struct clk
356 * Recalculate and propagate the DPLL rate.
358 unsigned long omap3_dpll_recalc(struct clk
*clk
)
360 return omap2_get_dpll_rate(clk
);
363 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
366 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
367 * @clk: pointer to a DPLL struct clk
369 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
370 * The choice of modes depends on the DPLL's programmed rate: if it is
371 * the same as the DPLL's parent clock, it will enter bypass;
372 * otherwise, it will enter lock. This code will wait for the DPLL to
373 * indicate readiness before returning, unless the DPLL takes too long
374 * to enter the target state. Intended to be used as the struct clk's
375 * enable function. If DPLL3 was passed in, or the DPLL does not
376 * support low-power stop, or if the DPLL took too long to enter
377 * bypass or lock, return -EINVAL; otherwise, return 0.
379 int omap3_noncore_dpll_enable(struct clk
*clk
)
382 struct dpll_data
*dd
;
389 parent
= __clk_get_parent(clk
);
391 if (__clk_get_rate(clk
) == __clk_get_rate(dd
->clk_bypass
)) {
392 WARN_ON(parent
!= dd
->clk_bypass
);
393 r
= _omap3_noncore_dpll_bypass(clk
);
395 WARN_ON(parent
!= dd
->clk_ref
);
396 r
= _omap3_noncore_dpll_lock(clk
);
399 *FIXME: this is dubious - if clk->rate has changed, what about
403 clk
->rate
= (clk
->recalc
) ? clk
->recalc(clk
) :
404 omap2_get_dpll_rate(clk
);
410 * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
411 * @clk: pointer to a DPLL struct clk
413 * Instructs a non-CORE DPLL to enter low-power stop. This function is
414 * intended for use in struct clkops. No return value.
416 void omap3_noncore_dpll_disable(struct clk
*clk
)
418 _omap3_noncore_dpll_stop(clk
);
422 /* Non-CORE DPLL rate set code */
425 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
426 * @clk: struct clk * of DPLL to set
427 * @rate: rounded target rate
429 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
430 * low-power bypass, and the target rate is the bypass source clock
431 * rate, then configure the DPLL for bypass. Otherwise, round the
432 * target rate if it hasn't been done already, then program and lock
433 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
435 int omap3_noncore_dpll_set_rate(struct clk
*clk
, unsigned long rate
)
437 struct clk
*new_parent
= NULL
;
438 unsigned long hw_rate
, bypass_rate
;
440 struct dpll_data
*dd
;
450 hw_rate
= (clk
->recalc
) ? clk
->recalc(clk
) : omap2_get_dpll_rate(clk
);
455 * Ensure both the bypass and ref clocks are enabled prior to
456 * doing anything; we need the bypass clock running to reprogram
459 omap2_clk_enable(dd
->clk_bypass
);
460 omap2_clk_enable(dd
->clk_ref
);
462 bypass_rate
= __clk_get_rate(dd
->clk_bypass
);
463 if (bypass_rate
== rate
&&
464 (clk
->dpll_data
->modes
& (1 << DPLL_LOW_POWER_BYPASS
))) {
465 pr_debug("clock: %s: set rate: entering bypass.\n", clk
->name
);
467 ret
= _omap3_noncore_dpll_bypass(clk
);
469 new_parent
= dd
->clk_bypass
;
471 if (dd
->last_rounded_rate
!= rate
)
472 rate
= clk
->round_rate(clk
, rate
);
474 if (dd
->last_rounded_rate
== 0)
477 /* No freqsel on OMAP4 and OMAP3630 */
478 if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
479 freqsel
= _omap3_dpll_compute_freqsel(clk
,
485 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
486 __clk_get_name(clk
), rate
);
488 ret
= omap3_noncore_dpll_program(clk
, dd
->last_rounded_m
,
489 dd
->last_rounded_n
, freqsel
);
491 new_parent
= dd
->clk_ref
;
495 * Switch the parent clock in the hierarchy, and make sure
496 * that the new parent's usecount is correct. Note: we
497 * enable the new parent before disabling the old to avoid
498 * any unnecessary hardware disable->enable transitions.
501 omap2_clk_enable(new_parent
);
502 omap2_clk_disable(clk
->parent
);
504 clk_reparent(clk
, new_parent
);
507 omap2_clk_disable(dd
->clk_ref
);
508 omap2_clk_disable(dd
->clk_bypass
);
513 /* DPLL autoidle read/set code */
516 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
517 * @clk: struct clk * of the DPLL to read
519 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
520 * -EINVAL if passed a null pointer or if the struct clk does not
521 * appear to refer to a DPLL.
523 u32
omap3_dpll_autoidle_read(struct clk
*clk
)
525 const struct dpll_data
*dd
;
528 if (!clk
|| !clk
->dpll_data
)
533 if (!dd
->autoidle_reg
)
536 v
= __raw_readl(dd
->autoidle_reg
);
537 v
&= dd
->autoidle_mask
;
538 v
>>= __ffs(dd
->autoidle_mask
);
544 * omap3_dpll_allow_idle - enable DPLL autoidle bits
545 * @clk: struct clk * of the DPLL to operate on
547 * Enable DPLL automatic idle control. This automatic idle mode
548 * switching takes effect only when the DPLL is locked, at least on
549 * OMAP3430. The DPLL will enter low-power stop when its downstream
550 * clocks are gated. No return value.
552 void omap3_dpll_allow_idle(struct clk
*clk
)
554 const struct dpll_data
*dd
;
557 if (!clk
|| !clk
->dpll_data
)
562 if (!dd
->autoidle_reg
) {
563 pr_debug("clock: DPLL %s: autoidle not supported\n",
564 __clk_get_name(clk
));
569 * REVISIT: CORE DPLL can optionally enter low-power bypass
570 * by writing 0x5 instead of 0x1. Add some mechanism to
571 * optionally enter this mode.
573 v
= __raw_readl(dd
->autoidle_reg
);
574 v
&= ~dd
->autoidle_mask
;
575 v
|= DPLL_AUTOIDLE_LOW_POWER_STOP
<< __ffs(dd
->autoidle_mask
);
576 __raw_writel(v
, dd
->autoidle_reg
);
581 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
582 * @clk: struct clk * of the DPLL to operate on
584 * Disable DPLL automatic idle control. No return value.
586 void omap3_dpll_deny_idle(struct clk
*clk
)
588 const struct dpll_data
*dd
;
591 if (!clk
|| !clk
->dpll_data
)
596 if (!dd
->autoidle_reg
) {
597 pr_debug("clock: DPLL %s: autoidle not supported\n",
598 __clk_get_name(clk
));
602 v
= __raw_readl(dd
->autoidle_reg
);
603 v
&= ~dd
->autoidle_mask
;
604 v
|= DPLL_AUTOIDLE_DISABLE
<< __ffs(dd
->autoidle_mask
);
605 __raw_writel(v
, dd
->autoidle_reg
);
609 /* Clock control for DPLL outputs */
612 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
613 * @clk: DPLL output struct clk
615 * Using parent clock DPLL data, look up DPLL state. If locked, set our
616 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
618 unsigned long omap3_clkoutx2_recalc(struct clk
*clk
)
620 const struct dpll_data
*dd
;
624 unsigned long parent_rate
;
626 /* Walk up the parents of clk, looking for a DPLL */
627 pclk
= __clk_get_parent(clk
);
628 while (pclk
&& !pclk
->dpll_data
)
629 pclk
= __clk_get_parent(pclk
);
631 /* clk does not have a DPLL as a parent? error in the clock data */
637 dd
= pclk
->dpll_data
;
639 WARN_ON(!dd
->enable_mask
);
641 parent_rate
= __clk_get_rate(__clk_get_parent(clk
));
642 v
= __raw_readl(dd
->control_reg
) & dd
->enable_mask
;
643 v
>>= __ffs(dd
->enable_mask
);
644 if ((v
!= OMAP3XXX_EN_DPLL_LOCKED
) || (dd
->flags
& DPLL_J_TYPE
))
647 rate
= parent_rate
* 2;
651 /* OMAP3/4 non-CORE DPLL clkops */
653 const struct clkops clkops_omap3_noncore_dpll_ops
= {
654 .enable
= omap3_noncore_dpll_enable
,
655 .disable
= omap3_noncore_dpll_disable
,
656 .allow_idle
= omap3_dpll_allow_idle
,
657 .deny_idle
= omap3_dpll_deny_idle
,
660 const struct clkops clkops_omap3_core_dpll_ops
= {
661 .allow_idle
= omap3_dpll_allow_idle
,
662 .deny_idle
= omap3_dpll_deny_idle
,