4 * Copyright (C) 2009 Texas Instruments
5 * Vimal Singh <vimalsingh@ti.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/platform_device.h>
15 #include <linux/mtd/nand.h>
16 #include <linux/platform_data/mtd-nand-omap2.h>
18 #include <asm/mach/flash.h>
22 #include "gpmc-nand.h"
24 /* minimum size for IO mapping */
25 #define NAND_IO_SIZE 4
27 static struct resource gpmc_nand_resource
[] = {
29 .flags
= IORESOURCE_MEM
,
32 .flags
= IORESOURCE_IRQ
,
35 .flags
= IORESOURCE_IRQ
,
39 static struct platform_device gpmc_nand_device
= {
42 .num_resources
= ARRAY_SIZE(gpmc_nand_resource
),
43 .resource
= gpmc_nand_resource
,
46 static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt
)
48 /* platforms which support all ECC schemes */
49 if (soc_is_am33xx() || soc_is_am43xx() || cpu_is_omap44xx() ||
50 soc_is_omap54xx() || soc_is_dra7xx())
53 if (ecc_opt
== OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
||
54 ecc_opt
== OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
) {
55 if (cpu_is_omap24xx())
57 else if (cpu_is_omap3630() && (GET_OMAP_REVISION() == 0))
63 /* OMAP3xxx do not have ELM engine, so cannot support ECC schemes
64 * which require H/W based ECC error detection */
65 if ((cpu_is_omap34xx() || cpu_is_omap3630()) &&
66 ((ecc_opt
== OMAP_ECC_BCH4_CODE_HW
) ||
67 (ecc_opt
== OMAP_ECC_BCH8_CODE_HW
)))
70 /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
71 if (ecc_opt
== OMAP_ECC_HAM1_CODE_HW
)
77 /* This function will go away once the device-tree convertion is complete */
78 static void gpmc_set_legacy(struct omap_nand_platform_data
*gpmc_nand_data
,
79 struct gpmc_settings
*s
)
81 /* Enable RD PIN Monitoring Reg */
82 if (gpmc_nand_data
->dev_ready
) {
83 s
->wait_on_read
= true;
84 s
->wait_on_write
= true;
87 if (gpmc_nand_data
->devsize
== NAND_BUSWIDTH_16
)
88 s
->device_width
= GPMC_DEVWIDTH_16BIT
;
90 s
->device_width
= GPMC_DEVWIDTH_8BIT
;
93 int gpmc_nand_init(struct omap_nand_platform_data
*gpmc_nand_data
,
94 struct gpmc_timings
*gpmc_t
)
97 struct gpmc_settings s
;
98 struct device
*dev
= &gpmc_nand_device
.dev
;
100 memset(&s
, 0, sizeof(struct gpmc_settings
));
102 gpmc_nand_device
.dev
.platform_data
= gpmc_nand_data
;
104 err
= gpmc_cs_request(gpmc_nand_data
->cs
, NAND_IO_SIZE
,
105 (unsigned long *)&gpmc_nand_resource
[0].start
);
107 dev_err(dev
, "Cannot request GPMC CS %d, error %d\n",
108 gpmc_nand_data
->cs
, err
);
112 gpmc_nand_resource
[0].end
= gpmc_nand_resource
[0].start
+
115 gpmc_nand_resource
[1].start
=
116 gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE
);
117 gpmc_nand_resource
[2].start
=
118 gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT
);
121 err
= gpmc_cs_set_timings(gpmc_nand_data
->cs
, gpmc_t
);
123 dev_err(dev
, "Unable to set gpmc timings: %d\n", err
);
128 if (gpmc_nand_data
->of_node
)
129 gpmc_read_settings_dt(gpmc_nand_data
->of_node
, &s
);
131 gpmc_set_legacy(gpmc_nand_data
, &s
);
133 s
.device_nand
= true;
135 err
= gpmc_cs_program_settings(gpmc_nand_data
->cs
, &s
);
139 err
= gpmc_configure(GPMC_CONFIG_WP
, 0);
143 gpmc_update_nand_reg(&gpmc_nand_data
->reg
, gpmc_nand_data
->cs
);
145 if (!gpmc_hwecc_bch_capable(gpmc_nand_data
->ecc_opt
)) {
146 dev_err(dev
, "Unsupported NAND ECC scheme selected\n");
150 err
= platform_device_register(&gpmc_nand_device
);
152 dev_err(dev
, "Unable to register NAND device\n");
159 gpmc_cs_free(gpmc_nand_data
->cs
);