4 * Copyright (C) 2009 Texas Instruments
5 * Vimal Singh <vimalsingh@ti.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/platform_device.h>
15 #include <linux/mtd/nand.h>
16 #include <linux/platform_data/mtd-nand-omap2.h>
18 #include <asm/mach/flash.h>
22 #include "gpmc-nand.h"
24 /* minimum size for IO mapping */
25 #define NAND_IO_SIZE 4
27 static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt
)
29 /* platforms which support all ECC schemes */
30 if (soc_is_am33xx() || soc_is_am43xx() || cpu_is_omap44xx() ||
31 soc_is_omap54xx() || soc_is_dra7xx())
34 if (ecc_opt
== OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
||
35 ecc_opt
== OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
) {
36 if (cpu_is_omap24xx())
38 else if (cpu_is_omap3630() && (GET_OMAP_REVISION() == 0))
44 /* OMAP3xxx do not have ELM engine, so cannot support ECC schemes
45 * which require H/W based ECC error detection */
46 if ((cpu_is_omap34xx() || cpu_is_omap3630()) &&
47 ((ecc_opt
== OMAP_ECC_BCH4_CODE_HW
) ||
48 (ecc_opt
== OMAP_ECC_BCH8_CODE_HW
)))
51 /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
52 if (ecc_opt
== OMAP_ECC_HAM1_CODE_HW
||
53 ecc_opt
== OMAP_ECC_HAM1_CODE_SW
)
59 /* This function will go away once the device-tree convertion is complete */
60 static void gpmc_set_legacy(struct omap_nand_platform_data
*gpmc_nand_data
,
61 struct gpmc_settings
*s
)
63 /* Enable RD PIN Monitoring Reg */
64 if (gpmc_nand_data
->dev_ready
) {
65 s
->wait_on_read
= true;
66 s
->wait_on_write
= true;
69 if (gpmc_nand_data
->devsize
== NAND_BUSWIDTH_16
)
70 s
->device_width
= GPMC_DEVWIDTH_16BIT
;
72 s
->device_width
= GPMC_DEVWIDTH_8BIT
;
75 int gpmc_nand_init(struct omap_nand_platform_data
*gpmc_nand_data
,
76 struct gpmc_timings
*gpmc_t
)
79 struct gpmc_settings s
;
80 struct platform_device
*pdev
;
81 struct resource gpmc_nand_res
[] = {
82 { .flags
= IORESOURCE_MEM
, },
83 { .flags
= IORESOURCE_IRQ
, },
84 { .flags
= IORESOURCE_IRQ
, },
87 BUG_ON(gpmc_nand_data
->cs
>= GPMC_CS_NUM
);
89 err
= gpmc_cs_request(gpmc_nand_data
->cs
, NAND_IO_SIZE
,
90 (unsigned long *)&gpmc_nand_res
[0].start
);
92 pr_err("omap2-gpmc: Cannot request GPMC CS %d, error %d\n",
93 gpmc_nand_data
->cs
, err
);
96 gpmc_nand_res
[0].end
= gpmc_nand_res
[0].start
+ NAND_IO_SIZE
- 1;
97 gpmc_nand_res
[1].start
= gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE
);
98 gpmc_nand_res
[2].start
= gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT
);
101 err
= gpmc_cs_set_timings(gpmc_nand_data
->cs
, gpmc_t
);
103 pr_err("omap2-gpmc: Unable to set gpmc timings: %d\n", err
);
108 memset(&s
, 0, sizeof(struct gpmc_settings
));
109 if (gpmc_nand_data
->of_node
)
110 gpmc_read_settings_dt(gpmc_nand_data
->of_node
, &s
);
112 gpmc_set_legacy(gpmc_nand_data
, &s
);
114 s
.device_nand
= true;
115 err
= gpmc_cs_program_settings(gpmc_nand_data
->cs
, &s
);
119 err
= gpmc_configure(GPMC_CONFIG_WP
, 0);
123 gpmc_update_nand_reg(&gpmc_nand_data
->reg
, gpmc_nand_data
->cs
);
125 if (!gpmc_hwecc_bch_capable(gpmc_nand_data
->ecc_opt
)) {
126 pr_err("omap2-nand: Unsupported NAND ECC scheme selected\n");
132 pdev
= platform_device_alloc("omap2-nand", gpmc_nand_data
->cs
);
134 err
= platform_device_add_resources(pdev
, gpmc_nand_res
,
135 ARRAY_SIZE(gpmc_nand_res
));
137 pdev
->dev
.platform_data
= gpmc_nand_data
;
144 err
= platform_device_add(pdev
);
146 dev_err(&pdev
->dev
, "Unable to register NAND device\n");
153 platform_device_put(pdev
);
155 gpmc_cs_free(gpmc_nand_data
->cs
);