2 * linux/arch/arm/mach-omap2/gpmc-onenand.c
4 * Copyright (C) 2006 - 2009 Nokia Corporation
5 * Contacts: Juha Yrjola
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/string.h>
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/mtd/onenand_regs.h>
19 #include <asm/mach/flash.h>
22 #include <plat/onenand.h>
23 #include <plat/board.h>
24 #include <plat/gpmc.h>
26 static struct omap_onenand_platform_data
*gpmc_onenand_data
;
28 static struct platform_device gpmc_onenand_device
= {
29 .name
= "omap2-onenand",
33 static int omap2_onenand_set_async_mode(int cs
, void __iomem
*onenand_base
)
35 struct gpmc_timings t
;
40 const int t_avdp
= 12;
41 const int t_aavdh
= 7;
45 const int t_cez
= 20; /* max of t_cez, t_oez */
50 /* Ensure sync read and sync write are disabled */
51 reg
= readw(onenand_base
+ ONENAND_REG_SYS_CFG1
);
52 reg
&= ~ONENAND_SYS_CFG1_SYNC_READ
& ~ONENAND_SYS_CFG1_SYNC_WRITE
;
53 writew(reg
, onenand_base
+ ONENAND_REG_SYS_CFG1
);
55 memset(&t
, 0, sizeof(t
));
61 t
.adv_rd_off
= gpmc_round_ns_to_ticks(max_t(int, t_avdp
, t_cer
));
62 t
.oe_on
= t
.adv_rd_off
+ gpmc_round_ns_to_ticks(t_aavdh
);
63 t
.access
= t
.adv_on
+ gpmc_round_ns_to_ticks(t_aa
);
64 t
.access
= max_t(int, t
.access
, t
.cs_on
+ gpmc_round_ns_to_ticks(t_ce
));
65 t
.access
= max_t(int, t
.access
, t
.oe_on
+ gpmc_round_ns_to_ticks(t_oe
));
66 t
.oe_off
= t
.access
+ gpmc_round_ns_to_ticks(1);
67 t
.cs_rd_off
= t
.oe_off
;
68 t
.rd_cycle
= t
.cs_rd_off
+ gpmc_round_ns_to_ticks(t_cez
);
71 t
.adv_wr_off
= t
.adv_rd_off
;
73 if (cpu_is_omap34xx()) {
74 t
.wr_data_mux_bus
= t
.we_on
;
75 t
.wr_access
= t
.we_on
+ gpmc_round_ns_to_ticks(t_ds
);
77 t
.we_off
= t
.we_on
+ gpmc_round_ns_to_ticks(t_wpl
);
78 t
.cs_wr_off
= t
.we_off
+ gpmc_round_ns_to_ticks(t_wph
);
79 t
.wr_cycle
= t
.cs_wr_off
+ gpmc_round_ns_to_ticks(t_cez
);
81 /* Configure GPMC for asynchronous read */
82 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
,
83 GPMC_CONFIG1_DEVICESIZE_16
|
84 GPMC_CONFIG1_MUXADDDATA
);
86 err
= gpmc_cs_set_timings(cs
, &t
);
90 /* Ensure sync read and sync write are disabled */
91 reg
= readw(onenand_base
+ ONENAND_REG_SYS_CFG1
);
92 reg
&= ~ONENAND_SYS_CFG1_SYNC_READ
& ~ONENAND_SYS_CFG1_SYNC_WRITE
;
93 writew(reg
, onenand_base
+ ONENAND_REG_SYS_CFG1
);
98 static void set_onenand_cfg(void __iomem
*onenand_base
, int latency
,
99 int sync_read
, int sync_write
, int hf
, int vhf
)
103 reg
= readw(onenand_base
+ ONENAND_REG_SYS_CFG1
);
104 reg
&= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT
) | (0x7 << 9));
105 reg
|= (latency
<< ONENAND_SYS_CFG1_BRL_SHIFT
) |
106 ONENAND_SYS_CFG1_BL_16
;
108 reg
|= ONENAND_SYS_CFG1_SYNC_READ
;
110 reg
&= ~ONENAND_SYS_CFG1_SYNC_READ
;
112 reg
|= ONENAND_SYS_CFG1_SYNC_WRITE
;
114 reg
&= ~ONENAND_SYS_CFG1_SYNC_WRITE
;
116 reg
|= ONENAND_SYS_CFG1_HF
;
118 reg
&= ~ONENAND_SYS_CFG1_HF
;
120 reg
|= ONENAND_SYS_CFG1_VHF
;
122 reg
&= ~ONENAND_SYS_CFG1_VHF
;
123 writew(reg
, onenand_base
+ ONENAND_REG_SYS_CFG1
);
126 static int omap2_onenand_get_freq(struct omap_onenand_platform_data
*cfg
,
127 void __iomem
*onenand_base
, bool *clk_dep
)
129 u16 ver
= readw(onenand_base
+ ONENAND_REG_VERSION_ID
);
133 struct onenand_freq_info fi
;
135 fi
.maf_id
= readw(onenand_base
+ ONENAND_REG_MANUFACTURER_ID
);
136 fi
.dev_id
= readw(onenand_base
+ ONENAND_REG_DEVICE_ID
);
138 freq
= cfg
->get_freq(&fi
, clk_dep
);
143 switch ((ver
>> 4) & 0xf) {
167 static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data
*cfg
,
168 void __iomem
*onenand_base
,
171 struct gpmc_timings t
;
172 const int t_cer
= 15;
173 const int t_avdp
= 12;
174 const int t_cez
= 20; /* max of t_cez, t_oez */
176 const int t_wpl
= 40;
177 const int t_wph
= 30;
178 int min_gpmc_clk_period
, t_ces
, t_avds
, t_avdh
, t_ach
, t_aavdh
, t_rdyo
;
179 int div
, fclk_offset_ns
, fclk_offset
, gpmc_clk_ns
, latency
;
180 int first_time
= 0, hf
= 0, vhf
= 0, sync_read
= 0, sync_write
= 0;
182 int cs
= cfg
->cs
, freq
= *freq_ptr
;
184 bool clk_dep
= false;
186 if (cfg
->flags
& ONENAND_SYNC_READ
) {
188 } else if (cfg
->flags
& ONENAND_SYNC_READWRITE
) {
192 return omap2_onenand_set_async_mode(cs
, onenand_base
);
195 /* Very first call freq is not known */
196 err
= omap2_onenand_set_async_mode(cs
, onenand_base
);
199 freq
= omap2_onenand_get_freq(cfg
, onenand_base
, &clk_dep
);
205 min_gpmc_clk_period
= 9600; /* 104 MHz */
214 min_gpmc_clk_period
= 12000; /* 83 MHz */
223 min_gpmc_clk_period
= 15000; /* 66 MHz */
232 min_gpmc_clk_period
= 18500; /* 54 MHz */
243 div
= gpmc_cs_calc_divider(cs
, min_gpmc_clk_period
);
244 gpmc_clk_ns
= gpmc_ticks_to_ns(div
);
245 if (gpmc_clk_ns
< 15) /* >66Mhz */
247 if (gpmc_clk_ns
< 12) /* >83Mhz */
253 else if (gpmc_clk_ns
>= 25) /* 40 MHz*/
259 if (gpmc_clk_ns
< 12) { /* >83Mhz */
262 } else if (gpmc_clk_ns
< 15) { /* >66Mhz */
265 } else if (gpmc_clk_ns
< 25) { /* >40Mhz */
275 set_onenand_cfg(onenand_base
, latency
,
276 sync_read
, sync_write
, hf
, vhf
);
279 reg
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG2
);
281 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG2
, reg
);
282 reg
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG3
);
284 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG3
, reg
);
285 reg
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG4
);
288 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG4
, reg
);
290 reg
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG2
);
292 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG2
, reg
);
293 reg
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG3
);
295 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG3
, reg
);
296 reg
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG4
);
299 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG4
, reg
);
302 /* Set synchronous read timings */
303 memset(&t
, 0, sizeof(t
));
304 t
.sync_clk
= min_gpmc_clk_period
;
307 fclk_offset_ns
= gpmc_round_ns_to_ticks(max_t(int, t_ces
, t_avds
));
308 fclk_offset
= gpmc_ns_to_ticks(fclk_offset_ns
);
309 t
.page_burst_access
= gpmc_clk_ns
;
312 t
.adv_rd_off
= gpmc_ticks_to_ns(fclk_offset
+ gpmc_ns_to_ticks(t_avdh
));
313 t
.oe_on
= gpmc_ticks_to_ns(fclk_offset
+ gpmc_ns_to_ticks(t_ach
));
314 /* Force at least 1 clk between AVD High to OE Low */
315 if (t
.oe_on
<= t
.adv_rd_off
)
316 t
.oe_on
= t
.adv_rd_off
+ gpmc_round_ns_to_ticks(1);
317 t
.access
= gpmc_ticks_to_ns(fclk_offset
+ (latency
+ 1) * div
);
318 t
.oe_off
= t
.access
+ gpmc_round_ns_to_ticks(1);
319 t
.cs_rd_off
= t
.oe_off
;
320 ticks_cez
= ((gpmc_ns_to_ticks(t_cez
) + div
- 1) / div
) * div
;
321 t
.rd_cycle
= gpmc_ticks_to_ns(fclk_offset
+ (latency
+ 1) * div
+
326 t
.adv_wr_off
= t
.adv_rd_off
;
328 t
.we_off
= t
.cs_rd_off
;
329 t
.cs_wr_off
= t
.cs_rd_off
;
330 t
.wr_cycle
= t
.rd_cycle
;
331 if (cpu_is_omap34xx()) {
332 t
.wr_data_mux_bus
= gpmc_ticks_to_ns(fclk_offset
+
333 gpmc_ps_to_ticks(min_gpmc_clk_period
+
335 t
.wr_access
= t
.access
;
338 t
.adv_wr_off
= gpmc_round_ns_to_ticks(max_t(int,
340 t
.we_on
= t
.adv_wr_off
+ gpmc_round_ns_to_ticks(t_aavdh
);
341 t
.we_off
= t
.we_on
+ gpmc_round_ns_to_ticks(t_wpl
);
342 t
.cs_wr_off
= t
.we_off
+ gpmc_round_ns_to_ticks(t_wph
);
343 t
.wr_cycle
= t
.cs_wr_off
+ gpmc_round_ns_to_ticks(t_cez
);
344 if (cpu_is_omap34xx()) {
345 t
.wr_data_mux_bus
= t
.we_on
;
346 t
.wr_access
= t
.we_on
+ gpmc_round_ns_to_ticks(t_ds
);
350 /* Configure GPMC for synchronous read */
351 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
,
352 GPMC_CONFIG1_WRAPBURST_SUPP
|
353 GPMC_CONFIG1_READMULTIPLE_SUPP
|
354 (sync_read
? GPMC_CONFIG1_READTYPE_SYNC
: 0) |
355 (sync_write
? GPMC_CONFIG1_WRITEMULTIPLE_SUPP
: 0) |
356 (sync_write
? GPMC_CONFIG1_WRITETYPE_SYNC
: 0) |
357 GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset
) |
358 GPMC_CONFIG1_PAGE_LEN(2) |
359 (cpu_is_omap34xx() ? 0 :
360 (GPMC_CONFIG1_WAIT_READ_MON
|
361 GPMC_CONFIG1_WAIT_PIN_SEL(0))) |
362 GPMC_CONFIG1_DEVICESIZE_16
|
363 GPMC_CONFIG1_DEVICETYPE_NOR
|
364 GPMC_CONFIG1_MUXADDDATA
);
366 err
= gpmc_cs_set_timings(cs
, &t
);
370 set_onenand_cfg(onenand_base
, latency
, sync_read
, sync_write
, hf
, vhf
);
377 static int gpmc_onenand_setup(void __iomem
*onenand_base
, int *freq_ptr
)
379 struct device
*dev
= &gpmc_onenand_device
.dev
;
381 /* Set sync timings in GPMC */
382 if (omap2_onenand_set_sync_mode(gpmc_onenand_data
, onenand_base
,
384 dev_err(dev
, "Unable to set synchronous mode\n");
391 void __init
gpmc_onenand_init(struct omap_onenand_platform_data
*_onenand_data
)
393 gpmc_onenand_data
= _onenand_data
;
394 gpmc_onenand_data
->onenand_setup
= gpmc_onenand_setup
;
395 gpmc_onenand_device
.dev
.platform_data
= gpmc_onenand_data
;
397 if (cpu_is_omap24xx() &&
398 (gpmc_onenand_data
->flags
& ONENAND_SYNC_READWRITE
)) {
399 printk(KERN_ERR
"Onenand using only SYNC_READ on 24xx\n");
400 gpmc_onenand_data
->flags
&= ~ONENAND_SYNC_READWRITE
;
401 gpmc_onenand_data
->flags
|= ONENAND_SYNC_READ
;
404 if (platform_device_register(&gpmc_onenand_device
) < 0) {
405 printk(KERN_ERR
"Unable to register OneNAND device\n");