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20747fbc686af7cdd12a3ab448e2537191696729
[deliverable/linux.git] / arch / arm / mach-omap2 / gpmc.c
1 /*
2 * GPMC support functions
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * Author: Juha Yrjola
7 *
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15 #undef DEBUG
16
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/ioport.h>
23 #include <linux/spinlock.h>
24 #include <linux/io.h>
25 #include <linux/module.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/of.h>
29 #include <linux/of_mtd.h>
30 #include <linux/of_device.h>
31 #include <linux/mtd/nand.h>
32
33 #include <linux/platform_data/mtd-nand-omap2.h>
34
35 #include <asm/mach-types.h>
36
37 #include "soc.h"
38 #include "common.h"
39 #include "omap_device.h"
40 #include "gpmc.h"
41 #include "gpmc-nand.h"
42 #include "gpmc-onenand.h"
43
44 #define DEVICE_NAME "omap-gpmc"
45
46 /* GPMC register offsets */
47 #define GPMC_REVISION 0x00
48 #define GPMC_SYSCONFIG 0x10
49 #define GPMC_SYSSTATUS 0x14
50 #define GPMC_IRQSTATUS 0x18
51 #define GPMC_IRQENABLE 0x1c
52 #define GPMC_TIMEOUT_CONTROL 0x40
53 #define GPMC_ERR_ADDRESS 0x44
54 #define GPMC_ERR_TYPE 0x48
55 #define GPMC_CONFIG 0x50
56 #define GPMC_STATUS 0x54
57 #define GPMC_PREFETCH_CONFIG1 0x1e0
58 #define GPMC_PREFETCH_CONFIG2 0x1e4
59 #define GPMC_PREFETCH_CONTROL 0x1ec
60 #define GPMC_PREFETCH_STATUS 0x1f0
61 #define GPMC_ECC_CONFIG 0x1f4
62 #define GPMC_ECC_CONTROL 0x1f8
63 #define GPMC_ECC_SIZE_CONFIG 0x1fc
64 #define GPMC_ECC1_RESULT 0x200
65 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
66 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
67 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
68 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
69
70 /* GPMC ECC control settings */
71 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
72 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
73 #define GPMC_ECC_CTRL_ECCREG1 0x001
74 #define GPMC_ECC_CTRL_ECCREG2 0x002
75 #define GPMC_ECC_CTRL_ECCREG3 0x003
76 #define GPMC_ECC_CTRL_ECCREG4 0x004
77 #define GPMC_ECC_CTRL_ECCREG5 0x005
78 #define GPMC_ECC_CTRL_ECCREG6 0x006
79 #define GPMC_ECC_CTRL_ECCREG7 0x007
80 #define GPMC_ECC_CTRL_ECCREG8 0x008
81 #define GPMC_ECC_CTRL_ECCREG9 0x009
82
83 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
84 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
85 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
86 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
87 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
88 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
89
90 #define GPMC_CS0_OFFSET 0x60
91 #define GPMC_CS_SIZE 0x30
92 #define GPMC_BCH_SIZE 0x10
93
94 #define GPMC_MEM_START 0x00000000
95 #define GPMC_MEM_END 0x3FFFFFFF
96 #define BOOT_ROM_SPACE 0x100000 /* 1MB */
97
98 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
99 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
100
101 #define CS_NUM_SHIFT 24
102 #define ENABLE_PREFETCH (0x1 << 7)
103 #define DMA_MPU_MODE 2
104
105 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
106 #define GPMC_REVISION_MINOR(l) (l & 0xf)
107
108 #define GPMC_HAS_WR_ACCESS 0x1
109 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
110
111 #define GPMC_NR_WAITPINS 4
112
113 /* XXX: Only NAND irq has been considered,currently these are the only ones used
114 */
115 #define GPMC_NR_IRQ 2
116
117 struct gpmc_client_irq {
118 unsigned irq;
119 u32 bitmask;
120 };
121
122 /* Structure to save gpmc cs context */
123 struct gpmc_cs_config {
124 u32 config1;
125 u32 config2;
126 u32 config3;
127 u32 config4;
128 u32 config5;
129 u32 config6;
130 u32 config7;
131 int is_valid;
132 };
133
134 /*
135 * Structure to save/restore gpmc context
136 * to support core off on OMAP3
137 */
138 struct omap3_gpmc_regs {
139 u32 sysconfig;
140 u32 irqenable;
141 u32 timeout_ctrl;
142 u32 config;
143 u32 prefetch_config1;
144 u32 prefetch_config2;
145 u32 prefetch_control;
146 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
147 };
148
149 static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
150 static struct irq_chip gpmc_irq_chip;
151 static unsigned gpmc_irq_start;
152
153 static struct resource gpmc_mem_root;
154 static struct resource gpmc_cs_mem[GPMC_CS_NUM];
155 static DEFINE_SPINLOCK(gpmc_mem_lock);
156 /* Define chip-selects as reserved by default until probe completes */
157 static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
158 static unsigned int gpmc_nr_waitpins;
159 static struct device *gpmc_dev;
160 static int gpmc_irq;
161 static resource_size_t phys_base, mem_size;
162 static unsigned gpmc_capability;
163 static void __iomem *gpmc_base;
164
165 static struct clk *gpmc_l3_clk;
166
167 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
168
169 static void gpmc_write_reg(int idx, u32 val)
170 {
171 __raw_writel(val, gpmc_base + idx);
172 }
173
174 static u32 gpmc_read_reg(int idx)
175 {
176 return __raw_readl(gpmc_base + idx);
177 }
178
179 void gpmc_cs_write_reg(int cs, int idx, u32 val)
180 {
181 void __iomem *reg_addr;
182
183 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
184 __raw_writel(val, reg_addr);
185 }
186
187 static u32 gpmc_cs_read_reg(int cs, int idx)
188 {
189 void __iomem *reg_addr;
190
191 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
192 return __raw_readl(reg_addr);
193 }
194
195 /* TODO: Add support for gpmc_fck to clock framework and use it */
196 static unsigned long gpmc_get_fclk_period(void)
197 {
198 unsigned long rate = clk_get_rate(gpmc_l3_clk);
199
200 if (rate == 0) {
201 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
202 return 0;
203 }
204
205 rate /= 1000;
206 rate = 1000000000 / rate; /* In picoseconds */
207
208 return rate;
209 }
210
211 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
212 {
213 unsigned long tick_ps;
214
215 /* Calculate in picosecs to yield more exact results */
216 tick_ps = gpmc_get_fclk_period();
217
218 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
219 }
220
221 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
222 {
223 unsigned long tick_ps;
224
225 /* Calculate in picosecs to yield more exact results */
226 tick_ps = gpmc_get_fclk_period();
227
228 return (time_ps + tick_ps - 1) / tick_ps;
229 }
230
231 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
232 {
233 return ticks * gpmc_get_fclk_period() / 1000;
234 }
235
236 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
237 {
238 return ticks * gpmc_get_fclk_period();
239 }
240
241 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
242 {
243 unsigned long ticks = gpmc_ps_to_ticks(time_ps);
244
245 return ticks * gpmc_get_fclk_period();
246 }
247
248 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
249 {
250 u32 l;
251
252 l = gpmc_cs_read_reg(cs, reg);
253 if (value)
254 l |= mask;
255 else
256 l &= ~mask;
257 gpmc_cs_write_reg(cs, reg, l);
258 }
259
260 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
261 {
262 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
263 GPMC_CONFIG1_TIME_PARA_GRAN,
264 p->time_para_granularity);
265 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
266 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
267 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
268 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
269 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
270 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
271 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
272 GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
273 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
274 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
275 p->cycle2cyclesamecsen);
276 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
277 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
278 p->cycle2cyclediffcsen);
279 }
280
281 #ifdef DEBUG
282 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
283 int time, const char *name)
284 #else
285 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
286 int time)
287 #endif
288 {
289 u32 l;
290 int ticks, mask, nr_bits;
291
292 if (time == 0)
293 ticks = 0;
294 else
295 ticks = gpmc_ns_to_ticks(time);
296 nr_bits = end_bit - st_bit + 1;
297 if (ticks >= 1 << nr_bits) {
298 #ifdef DEBUG
299 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
300 cs, name, time, ticks, 1 << nr_bits);
301 #endif
302 return -1;
303 }
304
305 mask = (1 << nr_bits) - 1;
306 l = gpmc_cs_read_reg(cs, reg);
307 #ifdef DEBUG
308 printk(KERN_INFO
309 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
310 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
311 (l >> st_bit) & mask, time);
312 #endif
313 l &= ~(mask << st_bit);
314 l |= ticks << st_bit;
315 gpmc_cs_write_reg(cs, reg, l);
316
317 return 0;
318 }
319
320 #ifdef DEBUG
321 #define GPMC_SET_ONE(reg, st, end, field) \
322 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
323 t->field, #field) < 0) \
324 return -1
325 #else
326 #define GPMC_SET_ONE(reg, st, end, field) \
327 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
328 return -1
329 #endif
330
331 int gpmc_calc_divider(unsigned int sync_clk)
332 {
333 int div;
334 u32 l;
335
336 l = sync_clk + (gpmc_get_fclk_period() - 1);
337 div = l / gpmc_get_fclk_period();
338 if (div > 4)
339 return -1;
340 if (div <= 0)
341 div = 1;
342
343 return div;
344 }
345
346 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
347 {
348 int div;
349 u32 l;
350
351 div = gpmc_calc_divider(t->sync_clk);
352 if (div < 0)
353 return div;
354
355 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
356 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
357 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
358
359 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
360 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
361 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
362
363 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
364 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
365 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
366 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
367
368 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
369 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
370 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
371
372 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
373
374 GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
375 GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
376
377 GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
378 GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
379
380 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
381 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
382 if (gpmc_capability & GPMC_HAS_WR_ACCESS)
383 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
384
385 /* caller is expected to have initialized CONFIG1 to cover
386 * at least sync vs async
387 */
388 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
389 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
390 #ifdef DEBUG
391 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
392 cs, (div * gpmc_get_fclk_period()) / 1000, div);
393 #endif
394 l &= ~0x03;
395 l |= (div - 1);
396 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
397 }
398
399 gpmc_cs_bool_timings(cs, &t->bool_timings);
400
401 return 0;
402 }
403
404 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
405 {
406 u32 l;
407 u32 mask;
408
409 mask = (1 << GPMC_SECTION_SHIFT) - size;
410 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
411 l &= ~0x3f;
412 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
413 l &= ~(0x0f << 8);
414 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
415 l |= GPMC_CONFIG7_CSVALID;
416 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
417 }
418
419 static void gpmc_cs_disable_mem(int cs)
420 {
421 u32 l;
422
423 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
424 l &= ~GPMC_CONFIG7_CSVALID;
425 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
426 }
427
428 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
429 {
430 u32 l;
431 u32 mask;
432
433 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
434 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
435 mask = (l >> 8) & 0x0f;
436 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
437 }
438
439 static int gpmc_cs_mem_enabled(int cs)
440 {
441 u32 l;
442
443 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
444 return l & GPMC_CONFIG7_CSVALID;
445 }
446
447 static void gpmc_cs_set_reserved(int cs, int reserved)
448 {
449 gpmc_cs_map &= ~(1 << cs);
450 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
451 }
452
453 static bool gpmc_cs_reserved(int cs)
454 {
455 return gpmc_cs_map & (1 << cs);
456 }
457
458 static unsigned long gpmc_mem_align(unsigned long size)
459 {
460 int order;
461
462 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
463 order = GPMC_CHUNK_SHIFT - 1;
464 do {
465 size >>= 1;
466 order++;
467 } while (size);
468 size = 1 << order;
469 return size;
470 }
471
472 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
473 {
474 struct resource *res = &gpmc_cs_mem[cs];
475 int r;
476
477 size = gpmc_mem_align(size);
478 spin_lock(&gpmc_mem_lock);
479 res->start = base;
480 res->end = base + size - 1;
481 r = request_resource(&gpmc_mem_root, res);
482 spin_unlock(&gpmc_mem_lock);
483
484 return r;
485 }
486
487 static int gpmc_cs_delete_mem(int cs)
488 {
489 struct resource *res = &gpmc_cs_mem[cs];
490 int r;
491
492 spin_lock(&gpmc_mem_lock);
493 r = release_resource(&gpmc_cs_mem[cs]);
494 res->start = 0;
495 res->end = 0;
496 spin_unlock(&gpmc_mem_lock);
497
498 return r;
499 }
500
501 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
502 {
503 struct resource *res = &gpmc_cs_mem[cs];
504 int r = -1;
505
506 if (cs > GPMC_CS_NUM)
507 return -ENODEV;
508
509 size = gpmc_mem_align(size);
510 if (size > (1 << GPMC_SECTION_SHIFT))
511 return -ENOMEM;
512
513 spin_lock(&gpmc_mem_lock);
514 if (gpmc_cs_reserved(cs)) {
515 r = -EBUSY;
516 goto out;
517 }
518 if (gpmc_cs_mem_enabled(cs))
519 r = adjust_resource(res, res->start & ~(size - 1), size);
520 if (r < 0)
521 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
522 size, NULL, NULL);
523 if (r < 0)
524 goto out;
525
526 gpmc_cs_enable_mem(cs, res->start, resource_size(res));
527 *base = res->start;
528 gpmc_cs_set_reserved(cs, 1);
529 out:
530 spin_unlock(&gpmc_mem_lock);
531 return r;
532 }
533 EXPORT_SYMBOL(gpmc_cs_request);
534
535 void gpmc_cs_free(int cs)
536 {
537 spin_lock(&gpmc_mem_lock);
538 if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
539 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
540 BUG();
541 spin_unlock(&gpmc_mem_lock);
542 return;
543 }
544 gpmc_cs_disable_mem(cs);
545 release_resource(&gpmc_cs_mem[cs]);
546 gpmc_cs_set_reserved(cs, 0);
547 spin_unlock(&gpmc_mem_lock);
548 }
549 EXPORT_SYMBOL(gpmc_cs_free);
550
551 /**
552 * gpmc_cs_configure - write request to configure gpmc
553 * @cs: chip select number
554 * @cmd: command type
555 * @wval: value to write
556 * @return status of the operation
557 */
558 int gpmc_cs_configure(int cs, int cmd, int wval)
559 {
560 int err = 0;
561 u32 regval = 0;
562
563 switch (cmd) {
564 case GPMC_ENABLE_IRQ:
565 gpmc_write_reg(GPMC_IRQENABLE, wval);
566 break;
567
568 case GPMC_SET_IRQ_STATUS:
569 gpmc_write_reg(GPMC_IRQSTATUS, wval);
570 break;
571
572 case GPMC_CONFIG_WP:
573 regval = gpmc_read_reg(GPMC_CONFIG);
574 if (wval)
575 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
576 else
577 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
578 gpmc_write_reg(GPMC_CONFIG, regval);
579 break;
580
581 case GPMC_CONFIG_RDY_BSY:
582 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
583 if (wval)
584 regval |= WR_RD_PIN_MONITORING;
585 else
586 regval &= ~WR_RD_PIN_MONITORING;
587 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
588 break;
589
590 case GPMC_CONFIG_DEV_SIZE:
591 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
592
593 /* clear 2 target bits */
594 regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
595
596 /* set the proper value */
597 regval |= GPMC_CONFIG1_DEVICESIZE(wval);
598
599 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
600 break;
601
602 case GPMC_CONFIG_DEV_TYPE:
603 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
604 /* clear 4 target bits */
605 regval &= ~(GPMC_CONFIG1_DEVICETYPE(3) |
606 GPMC_CONFIG1_MUXTYPE(3));
607 /* set the proper value */
608 regval |= GPMC_CONFIG1_DEVICETYPE(wval);
609 if (wval == GPMC_DEVICETYPE_NOR)
610 regval |= GPMC_CONFIG1_MUXADDDATA;
611 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
612 break;
613
614 default:
615 printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
616 err = -EINVAL;
617 }
618
619 return err;
620 }
621 EXPORT_SYMBOL(gpmc_cs_configure);
622
623 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
624 {
625 int i;
626
627 reg->gpmc_status = gpmc_base + GPMC_STATUS;
628 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
629 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
630 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
631 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
632 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
633 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
634 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
635 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
636 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
637 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
638 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
639 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
640 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
641 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
642
643 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
644 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
645 GPMC_BCH_SIZE * i;
646 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
647 GPMC_BCH_SIZE * i;
648 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
649 GPMC_BCH_SIZE * i;
650 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
651 GPMC_BCH_SIZE * i;
652 }
653 }
654
655 int gpmc_get_client_irq(unsigned irq_config)
656 {
657 int i;
658
659 if (hweight32(irq_config) > 1)
660 return 0;
661
662 for (i = 0; i < GPMC_NR_IRQ; i++)
663 if (gpmc_client_irq[i].bitmask & irq_config)
664 return gpmc_client_irq[i].irq;
665
666 return 0;
667 }
668
669 static int gpmc_irq_endis(unsigned irq, bool endis)
670 {
671 int i;
672 u32 regval;
673
674 for (i = 0; i < GPMC_NR_IRQ; i++)
675 if (irq == gpmc_client_irq[i].irq) {
676 regval = gpmc_read_reg(GPMC_IRQENABLE);
677 if (endis)
678 regval |= gpmc_client_irq[i].bitmask;
679 else
680 regval &= ~gpmc_client_irq[i].bitmask;
681 gpmc_write_reg(GPMC_IRQENABLE, regval);
682 break;
683 }
684
685 return 0;
686 }
687
688 static void gpmc_irq_disable(struct irq_data *p)
689 {
690 gpmc_irq_endis(p->irq, false);
691 }
692
693 static void gpmc_irq_enable(struct irq_data *p)
694 {
695 gpmc_irq_endis(p->irq, true);
696 }
697
698 static void gpmc_irq_noop(struct irq_data *data) { }
699
700 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
701
702 static int gpmc_setup_irq(void)
703 {
704 int i;
705 u32 regval;
706
707 if (!gpmc_irq)
708 return -EINVAL;
709
710 gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
711 if (gpmc_irq_start < 0) {
712 pr_err("irq_alloc_descs failed\n");
713 return gpmc_irq_start;
714 }
715
716 gpmc_irq_chip.name = "gpmc";
717 gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
718 gpmc_irq_chip.irq_enable = gpmc_irq_enable;
719 gpmc_irq_chip.irq_disable = gpmc_irq_disable;
720 gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
721 gpmc_irq_chip.irq_ack = gpmc_irq_noop;
722 gpmc_irq_chip.irq_mask = gpmc_irq_noop;
723 gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
724
725 gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
726 gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
727
728 for (i = 0; i < GPMC_NR_IRQ; i++) {
729 gpmc_client_irq[i].irq = gpmc_irq_start + i;
730 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
731 &gpmc_irq_chip, handle_simple_irq);
732 set_irq_flags(gpmc_client_irq[i].irq,
733 IRQF_VALID | IRQF_NOAUTOEN);
734 }
735
736 /* Disable interrupts */
737 gpmc_write_reg(GPMC_IRQENABLE, 0);
738
739 /* clear interrupts */
740 regval = gpmc_read_reg(GPMC_IRQSTATUS);
741 gpmc_write_reg(GPMC_IRQSTATUS, regval);
742
743 return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
744 }
745
746 static int gpmc_free_irq(void)
747 {
748 int i;
749
750 if (gpmc_irq)
751 free_irq(gpmc_irq, NULL);
752
753 for (i = 0; i < GPMC_NR_IRQ; i++) {
754 irq_set_handler(gpmc_client_irq[i].irq, NULL);
755 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
756 irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
757 }
758
759 irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
760
761 return 0;
762 }
763
764 static void gpmc_mem_exit(void)
765 {
766 int cs;
767
768 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
769 if (!gpmc_cs_mem_enabled(cs))
770 continue;
771 gpmc_cs_delete_mem(cs);
772 }
773
774 }
775
776 static int gpmc_mem_init(void)
777 {
778 int cs, rc;
779 unsigned long boot_rom_space = 0;
780
781 /* never allocate the first page, to facilitate bug detection;
782 * even if we didn't boot from ROM.
783 */
784 boot_rom_space = BOOT_ROM_SPACE;
785 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
786 gpmc_mem_root.end = GPMC_MEM_END;
787
788 /* Reserve all regions that has been set up by bootloader */
789 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
790 u32 base, size;
791
792 if (!gpmc_cs_mem_enabled(cs))
793 continue;
794 gpmc_cs_get_memconf(cs, &base, &size);
795 rc = gpmc_cs_insert_mem(cs, base, size);
796 if (rc < 0) {
797 while (--cs >= 0)
798 if (gpmc_cs_mem_enabled(cs))
799 gpmc_cs_delete_mem(cs);
800 return rc;
801 }
802 }
803
804 return 0;
805 }
806
807 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
808 {
809 u32 temp;
810 int div;
811
812 div = gpmc_calc_divider(sync_clk);
813 temp = gpmc_ps_to_ticks(time_ps);
814 temp = (temp + div - 1) / div;
815 return gpmc_ticks_to_ps(temp * div);
816 }
817
818 /* XXX: can the cycles be avoided ? */
819 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
820 struct gpmc_device_timings *dev_t,
821 bool mux)
822 {
823 u32 temp;
824
825 /* adv_rd_off */
826 temp = dev_t->t_avdp_r;
827 /* XXX: mux check required ? */
828 if (mux) {
829 /* XXX: t_avdp not to be required for sync, only added for tusb
830 * this indirectly necessitates requirement of t_avdp_r and
831 * t_avdp_w instead of having a single t_avdp
832 */
833 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
834 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
835 }
836 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
837
838 /* oe_on */
839 temp = dev_t->t_oeasu; /* XXX: remove this ? */
840 if (mux) {
841 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
842 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
843 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
844 }
845 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
846
847 /* access */
848 /* XXX: any scope for improvement ?, by combining oe_on
849 * and clk_activation, need to check whether
850 * access = clk_activation + round to sync clk ?
851 */
852 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
853 temp += gpmc_t->clk_activation;
854 if (dev_t->cyc_oe)
855 temp = max_t(u32, temp, gpmc_t->oe_on +
856 gpmc_ticks_to_ps(dev_t->cyc_oe));
857 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
858
859 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
860 gpmc_t->cs_rd_off = gpmc_t->oe_off;
861
862 /* rd_cycle */
863 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
864 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
865 gpmc_t->access;
866 /* XXX: barter t_ce_rdyz with t_cez_r ? */
867 if (dev_t->t_ce_rdyz)
868 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
869 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
870
871 return 0;
872 }
873
874 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
875 struct gpmc_device_timings *dev_t,
876 bool mux)
877 {
878 u32 temp;
879
880 /* adv_wr_off */
881 temp = dev_t->t_avdp_w;
882 if (mux) {
883 temp = max_t(u32, temp,
884 gpmc_t->clk_activation + dev_t->t_avdh);
885 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
886 }
887 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
888
889 /* wr_data_mux_bus */
890 temp = max_t(u32, dev_t->t_weasu,
891 gpmc_t->clk_activation + dev_t->t_rdyo);
892 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
893 * and in that case remember to handle we_on properly
894 */
895 if (mux) {
896 temp = max_t(u32, temp,
897 gpmc_t->adv_wr_off + dev_t->t_aavdh);
898 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
899 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
900 }
901 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
902
903 /* we_on */
904 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
905 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
906 else
907 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
908
909 /* wr_access */
910 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
911 gpmc_t->wr_access = gpmc_t->access;
912
913 /* we_off */
914 temp = gpmc_t->we_on + dev_t->t_wpl;
915 temp = max_t(u32, temp,
916 gpmc_t->wr_access + gpmc_ticks_to_ps(1));
917 temp = max_t(u32, temp,
918 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
919 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
920
921 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
922 dev_t->t_wph);
923
924 /* wr_cycle */
925 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
926 temp += gpmc_t->wr_access;
927 /* XXX: barter t_ce_rdyz with t_cez_w ? */
928 if (dev_t->t_ce_rdyz)
929 temp = max_t(u32, temp,
930 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
931 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
932
933 return 0;
934 }
935
936 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
937 struct gpmc_device_timings *dev_t,
938 bool mux)
939 {
940 u32 temp;
941
942 /* adv_rd_off */
943 temp = dev_t->t_avdp_r;
944 if (mux)
945 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
946 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
947
948 /* oe_on */
949 temp = dev_t->t_oeasu;
950 if (mux)
951 temp = max_t(u32, temp,
952 gpmc_t->adv_rd_off + dev_t->t_aavdh);
953 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
954
955 /* access */
956 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
957 gpmc_t->oe_on + dev_t->t_oe);
958 temp = max_t(u32, temp,
959 gpmc_t->cs_on + dev_t->t_ce);
960 temp = max_t(u32, temp,
961 gpmc_t->adv_on + dev_t->t_aa);
962 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
963
964 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
965 gpmc_t->cs_rd_off = gpmc_t->oe_off;
966
967 /* rd_cycle */
968 temp = max_t(u32, dev_t->t_rd_cycle,
969 gpmc_t->cs_rd_off + dev_t->t_cez_r);
970 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
971 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
972
973 return 0;
974 }
975
976 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
977 struct gpmc_device_timings *dev_t,
978 bool mux)
979 {
980 u32 temp;
981
982 /* adv_wr_off */
983 temp = dev_t->t_avdp_w;
984 if (mux)
985 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
986 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
987
988 /* wr_data_mux_bus */
989 temp = dev_t->t_weasu;
990 if (mux) {
991 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
992 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
993 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
994 }
995 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
996
997 /* we_on */
998 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
999 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1000 else
1001 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1002
1003 /* we_off */
1004 temp = gpmc_t->we_on + dev_t->t_wpl;
1005 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1006
1007 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1008 dev_t->t_wph);
1009
1010 /* wr_cycle */
1011 temp = max_t(u32, dev_t->t_wr_cycle,
1012 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1013 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1014
1015 return 0;
1016 }
1017
1018 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1019 struct gpmc_device_timings *dev_t)
1020 {
1021 u32 temp;
1022
1023 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1024 gpmc_get_fclk_period();
1025
1026 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1027 dev_t->t_bacc,
1028 gpmc_t->sync_clk);
1029
1030 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1031 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1032
1033 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1034 return 0;
1035
1036 if (dev_t->ce_xdelay)
1037 gpmc_t->bool_timings.cs_extra_delay = true;
1038 if (dev_t->avd_xdelay)
1039 gpmc_t->bool_timings.adv_extra_delay = true;
1040 if (dev_t->oe_xdelay)
1041 gpmc_t->bool_timings.oe_extra_delay = true;
1042 if (dev_t->we_xdelay)
1043 gpmc_t->bool_timings.we_extra_delay = true;
1044
1045 return 0;
1046 }
1047
1048 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1049 struct gpmc_device_timings *dev_t,
1050 bool sync)
1051 {
1052 u32 temp;
1053
1054 /* cs_on */
1055 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1056
1057 /* adv_on */
1058 temp = dev_t->t_avdasu;
1059 if (dev_t->t_ce_avd)
1060 temp = max_t(u32, temp,
1061 gpmc_t->cs_on + dev_t->t_ce_avd);
1062 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1063
1064 if (sync)
1065 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1066
1067 return 0;
1068 }
1069
1070 /* TODO: remove this function once all peripherals are confirmed to
1071 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1072 * has to be modified to handle timings in ps instead of ns
1073 */
1074 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1075 {
1076 t->cs_on /= 1000;
1077 t->cs_rd_off /= 1000;
1078 t->cs_wr_off /= 1000;
1079 t->adv_on /= 1000;
1080 t->adv_rd_off /= 1000;
1081 t->adv_wr_off /= 1000;
1082 t->we_on /= 1000;
1083 t->we_off /= 1000;
1084 t->oe_on /= 1000;
1085 t->oe_off /= 1000;
1086 t->page_burst_access /= 1000;
1087 t->access /= 1000;
1088 t->rd_cycle /= 1000;
1089 t->wr_cycle /= 1000;
1090 t->bus_turnaround /= 1000;
1091 t->cycle2cycle_delay /= 1000;
1092 t->wait_monitoring /= 1000;
1093 t->clk_activation /= 1000;
1094 t->wr_access /= 1000;
1095 t->wr_data_mux_bus /= 1000;
1096 }
1097
1098 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1099 struct gpmc_settings *gpmc_s,
1100 struct gpmc_device_timings *dev_t)
1101 {
1102 bool mux = false, sync = false;
1103
1104 if (gpmc_s) {
1105 mux = gpmc_s->mux_add_data ? true : false;
1106 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1107 }
1108
1109 memset(gpmc_t, 0, sizeof(*gpmc_t));
1110
1111 gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1112
1113 if (gpmc_s && gpmc_s->sync_read)
1114 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1115 else
1116 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1117
1118 if (gpmc_s && gpmc_s->sync_write)
1119 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1120 else
1121 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1122
1123 /* TODO: remove, see function definition */
1124 gpmc_convert_ps_to_ns(gpmc_t);
1125
1126 return 0;
1127 }
1128
1129 #ifdef CONFIG_OF
1130 static struct of_device_id gpmc_dt_ids[] = {
1131 { .compatible = "ti,omap2420-gpmc" },
1132 { .compatible = "ti,omap2430-gpmc" },
1133 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1134 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1135 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
1136 { }
1137 };
1138 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1139
1140 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1141 struct gpmc_timings *gpmc_t)
1142 {
1143 u32 val;
1144
1145 memset(gpmc_t, 0, sizeof(*gpmc_t));
1146
1147 /* minimum clock period for syncronous mode */
1148 if (!of_property_read_u32(np, "gpmc,sync-clk", &val))
1149 gpmc_t->sync_clk = val;
1150
1151 /* chip select timtings */
1152 if (!of_property_read_u32(np, "gpmc,cs-on", &val))
1153 gpmc_t->cs_on = val;
1154
1155 if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val))
1156 gpmc_t->cs_rd_off = val;
1157
1158 if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val))
1159 gpmc_t->cs_wr_off = val;
1160
1161 /* ADV signal timings */
1162 if (!of_property_read_u32(np, "gpmc,adv-on", &val))
1163 gpmc_t->adv_on = val;
1164
1165 if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val))
1166 gpmc_t->adv_rd_off = val;
1167
1168 if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val))
1169 gpmc_t->adv_wr_off = val;
1170
1171 /* WE signal timings */
1172 if (!of_property_read_u32(np, "gpmc,we-on", &val))
1173 gpmc_t->we_on = val;
1174
1175 if (!of_property_read_u32(np, "gpmc,we-off", &val))
1176 gpmc_t->we_off = val;
1177
1178 /* OE signal timings */
1179 if (!of_property_read_u32(np, "gpmc,oe-on", &val))
1180 gpmc_t->oe_on = val;
1181
1182 if (!of_property_read_u32(np, "gpmc,oe-off", &val))
1183 gpmc_t->oe_off = val;
1184
1185 /* access and cycle timings */
1186 if (!of_property_read_u32(np, "gpmc,page-burst-access", &val))
1187 gpmc_t->page_burst_access = val;
1188
1189 if (!of_property_read_u32(np, "gpmc,access", &val))
1190 gpmc_t->access = val;
1191
1192 if (!of_property_read_u32(np, "gpmc,rd-cycle", &val))
1193 gpmc_t->rd_cycle = val;
1194
1195 if (!of_property_read_u32(np, "gpmc,wr-cycle", &val))
1196 gpmc_t->wr_cycle = val;
1197
1198 /* only for OMAP3430 */
1199 if (!of_property_read_u32(np, "gpmc,wr-access", &val))
1200 gpmc_t->wr_access = val;
1201
1202 if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val))
1203 gpmc_t->wr_data_mux_bus = val;
1204 }
1205
1206 #ifdef CONFIG_MTD_NAND
1207
1208 static const char * const nand_ecc_opts[] = {
1209 [OMAP_ECC_HAMMING_CODE_DEFAULT] = "sw",
1210 [OMAP_ECC_HAMMING_CODE_HW] = "hw",
1211 [OMAP_ECC_HAMMING_CODE_HW_ROMCODE] = "hw-romcode",
1212 [OMAP_ECC_BCH4_CODE_HW] = "bch4",
1213 [OMAP_ECC_BCH8_CODE_HW] = "bch8",
1214 };
1215
1216 static int gpmc_probe_nand_child(struct platform_device *pdev,
1217 struct device_node *child)
1218 {
1219 u32 val;
1220 const char *s;
1221 struct gpmc_timings gpmc_t;
1222 struct omap_nand_platform_data *gpmc_nand_data;
1223
1224 if (of_property_read_u32(child, "reg", &val) < 0) {
1225 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1226 child->full_name);
1227 return -ENODEV;
1228 }
1229
1230 gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1231 GFP_KERNEL);
1232 if (!gpmc_nand_data)
1233 return -ENOMEM;
1234
1235 gpmc_nand_data->cs = val;
1236 gpmc_nand_data->of_node = child;
1237
1238 if (!of_property_read_string(child, "ti,nand-ecc-opt", &s))
1239 for (val = 0; val < ARRAY_SIZE(nand_ecc_opts); val++)
1240 if (!strcasecmp(s, nand_ecc_opts[val])) {
1241 gpmc_nand_data->ecc_opt = val;
1242 break;
1243 }
1244
1245 val = of_get_nand_bus_width(child);
1246 if (val == 16)
1247 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1248
1249 gpmc_read_timings_dt(child, &gpmc_t);
1250 gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1251
1252 return 0;
1253 }
1254 #else
1255 static int gpmc_probe_nand_child(struct platform_device *pdev,
1256 struct device_node *child)
1257 {
1258 return 0;
1259 }
1260 #endif
1261
1262 #ifdef CONFIG_MTD_ONENAND
1263 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1264 struct device_node *child)
1265 {
1266 u32 val;
1267 struct omap_onenand_platform_data *gpmc_onenand_data;
1268
1269 if (of_property_read_u32(child, "reg", &val) < 0) {
1270 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1271 child->full_name);
1272 return -ENODEV;
1273 }
1274
1275 gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1276 GFP_KERNEL);
1277 if (!gpmc_onenand_data)
1278 return -ENOMEM;
1279
1280 gpmc_onenand_data->cs = val;
1281 gpmc_onenand_data->of_node = child;
1282 gpmc_onenand_data->dma_channel = -1;
1283
1284 if (!of_property_read_u32(child, "dma-channel", &val))
1285 gpmc_onenand_data->dma_channel = val;
1286
1287 gpmc_onenand_init(gpmc_onenand_data);
1288
1289 return 0;
1290 }
1291 #else
1292 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1293 struct device_node *child)
1294 {
1295 return 0;
1296 }
1297 #endif
1298
1299 static int gpmc_probe_dt(struct platform_device *pdev)
1300 {
1301 int ret;
1302 struct device_node *child;
1303 const struct of_device_id *of_id =
1304 of_match_device(gpmc_dt_ids, &pdev->dev);
1305
1306 if (!of_id)
1307 return 0;
1308
1309 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
1310 &gpmc_nr_waitpins);
1311 if (ret < 0) {
1312 pr_err("%s: number of wait pins not found!\n", __func__);
1313 return ret;
1314 }
1315
1316 for_each_node_by_name(child, "nand") {
1317 ret = gpmc_probe_nand_child(pdev, child);
1318 if (ret < 0) {
1319 of_node_put(child);
1320 return ret;
1321 }
1322 }
1323
1324 for_each_node_by_name(child, "onenand") {
1325 ret = gpmc_probe_onenand_child(pdev, child);
1326 if (ret < 0) {
1327 of_node_put(child);
1328 return ret;
1329 }
1330 }
1331 return 0;
1332 }
1333 #else
1334 static int gpmc_probe_dt(struct platform_device *pdev)
1335 {
1336 return 0;
1337 }
1338 #endif
1339
1340 static int gpmc_probe(struct platform_device *pdev)
1341 {
1342 int rc;
1343 u32 l;
1344 struct resource *res;
1345
1346 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1347 if (res == NULL)
1348 return -ENOENT;
1349
1350 phys_base = res->start;
1351 mem_size = resource_size(res);
1352
1353 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
1354 if (IS_ERR(gpmc_base))
1355 return PTR_ERR(gpmc_base);
1356
1357 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1358 if (res == NULL)
1359 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
1360 else
1361 gpmc_irq = res->start;
1362
1363 gpmc_l3_clk = clk_get(&pdev->dev, "fck");
1364 if (IS_ERR(gpmc_l3_clk)) {
1365 dev_err(&pdev->dev, "error: clk_get\n");
1366 gpmc_irq = 0;
1367 return PTR_ERR(gpmc_l3_clk);
1368 }
1369
1370 clk_prepare_enable(gpmc_l3_clk);
1371
1372 gpmc_dev = &pdev->dev;
1373
1374 l = gpmc_read_reg(GPMC_REVISION);
1375 if (GPMC_REVISION_MAJOR(l) > 0x4)
1376 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
1377 dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
1378 GPMC_REVISION_MINOR(l));
1379
1380 rc = gpmc_mem_init();
1381 if (rc < 0) {
1382 clk_disable_unprepare(gpmc_l3_clk);
1383 clk_put(gpmc_l3_clk);
1384 dev_err(gpmc_dev, "failed to reserve memory\n");
1385 return rc;
1386 }
1387
1388 if (gpmc_setup_irq() < 0)
1389 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
1390
1391 /* Now the GPMC is initialised, unreserve the chip-selects */
1392 gpmc_cs_map = 0;
1393
1394 if (!pdev->dev.of_node)
1395 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
1396
1397 rc = gpmc_probe_dt(pdev);
1398 if (rc < 0) {
1399 clk_disable_unprepare(gpmc_l3_clk);
1400 clk_put(gpmc_l3_clk);
1401 dev_err(gpmc_dev, "failed to probe DT parameters\n");
1402 return rc;
1403 }
1404
1405 return 0;
1406 }
1407
1408 static int gpmc_remove(struct platform_device *pdev)
1409 {
1410 gpmc_free_irq();
1411 gpmc_mem_exit();
1412 gpmc_dev = NULL;
1413 return 0;
1414 }
1415
1416 static struct platform_driver gpmc_driver = {
1417 .probe = gpmc_probe,
1418 .remove = gpmc_remove,
1419 .driver = {
1420 .name = DEVICE_NAME,
1421 .owner = THIS_MODULE,
1422 .of_match_table = of_match_ptr(gpmc_dt_ids),
1423 },
1424 };
1425
1426 static __init int gpmc_init(void)
1427 {
1428 return platform_driver_register(&gpmc_driver);
1429 }
1430
1431 static __exit void gpmc_exit(void)
1432 {
1433 platform_driver_unregister(&gpmc_driver);
1434
1435 }
1436
1437 omap_postcore_initcall(gpmc_init);
1438 module_exit(gpmc_exit);
1439
1440 static int __init omap_gpmc_init(void)
1441 {
1442 struct omap_hwmod *oh;
1443 struct platform_device *pdev;
1444 char *oh_name = "gpmc";
1445
1446 /*
1447 * if the board boots up with a populated DT, do not
1448 * manually add the device from this initcall
1449 */
1450 if (of_have_populated_dt())
1451 return -ENODEV;
1452
1453 oh = omap_hwmod_lookup(oh_name);
1454 if (!oh) {
1455 pr_err("Could not look up %s\n", oh_name);
1456 return -ENODEV;
1457 }
1458
1459 pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0);
1460 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
1461
1462 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
1463 }
1464 omap_postcore_initcall(omap_gpmc_init);
1465
1466 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
1467 {
1468 int i;
1469 u32 regval;
1470
1471 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1472
1473 if (!regval)
1474 return IRQ_NONE;
1475
1476 for (i = 0; i < GPMC_NR_IRQ; i++)
1477 if (regval & gpmc_client_irq[i].bitmask)
1478 generic_handle_irq(gpmc_client_irq[i].irq);
1479
1480 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1481
1482 return IRQ_HANDLED;
1483 }
1484
1485 #ifdef CONFIG_ARCH_OMAP3
1486 static struct omap3_gpmc_regs gpmc_context;
1487
1488 void omap3_gpmc_save_context(void)
1489 {
1490 int i;
1491
1492 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
1493 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
1494 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
1495 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
1496 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
1497 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
1498 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
1499 for (i = 0; i < GPMC_CS_NUM; i++) {
1500 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
1501 if (gpmc_context.cs_context[i].is_valid) {
1502 gpmc_context.cs_context[i].config1 =
1503 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
1504 gpmc_context.cs_context[i].config2 =
1505 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
1506 gpmc_context.cs_context[i].config3 =
1507 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
1508 gpmc_context.cs_context[i].config4 =
1509 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
1510 gpmc_context.cs_context[i].config5 =
1511 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
1512 gpmc_context.cs_context[i].config6 =
1513 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
1514 gpmc_context.cs_context[i].config7 =
1515 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
1516 }
1517 }
1518 }
1519
1520 void omap3_gpmc_restore_context(void)
1521 {
1522 int i;
1523
1524 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
1525 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
1526 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
1527 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
1528 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
1529 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
1530 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
1531 for (i = 0; i < GPMC_CS_NUM; i++) {
1532 if (gpmc_context.cs_context[i].is_valid) {
1533 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
1534 gpmc_context.cs_context[i].config1);
1535 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
1536 gpmc_context.cs_context[i].config2);
1537 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
1538 gpmc_context.cs_context[i].config3);
1539 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
1540 gpmc_context.cs_context[i].config4);
1541 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
1542 gpmc_context.cs_context[i].config5);
1543 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
1544 gpmc_context.cs_context[i].config6);
1545 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
1546 gpmc_context.cs_context[i].config7);
1547 }
1548 }
1549 }
1550 #endif /* CONFIG_ARCH_OMAP3 */
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