2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/ioport.h>
23 #include <linux/spinlock.h>
25 #include <linux/module.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
29 #include <linux/of_address.h>
30 #include <linux/of_mtd.h>
31 #include <linux/of_device.h>
32 #include <linux/mtd/nand.h>
34 #include <linux/platform_data/mtd-nand-omap2.h>
36 #include <asm/mach-types.h>
40 #include "omap_device.h"
42 #include "gpmc-nand.h"
43 #include "gpmc-onenand.h"
45 #define DEVICE_NAME "omap-gpmc"
47 /* GPMC register offsets */
48 #define GPMC_REVISION 0x00
49 #define GPMC_SYSCONFIG 0x10
50 #define GPMC_SYSSTATUS 0x14
51 #define GPMC_IRQSTATUS 0x18
52 #define GPMC_IRQENABLE 0x1c
53 #define GPMC_TIMEOUT_CONTROL 0x40
54 #define GPMC_ERR_ADDRESS 0x44
55 #define GPMC_ERR_TYPE 0x48
56 #define GPMC_CONFIG 0x50
57 #define GPMC_STATUS 0x54
58 #define GPMC_PREFETCH_CONFIG1 0x1e0
59 #define GPMC_PREFETCH_CONFIG2 0x1e4
60 #define GPMC_PREFETCH_CONTROL 0x1ec
61 #define GPMC_PREFETCH_STATUS 0x1f0
62 #define GPMC_ECC_CONFIG 0x1f4
63 #define GPMC_ECC_CONTROL 0x1f8
64 #define GPMC_ECC_SIZE_CONFIG 0x1fc
65 #define GPMC_ECC1_RESULT 0x200
66 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
67 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
68 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
69 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
71 /* GPMC ECC control settings */
72 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
73 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
74 #define GPMC_ECC_CTRL_ECCREG1 0x001
75 #define GPMC_ECC_CTRL_ECCREG2 0x002
76 #define GPMC_ECC_CTRL_ECCREG3 0x003
77 #define GPMC_ECC_CTRL_ECCREG4 0x004
78 #define GPMC_ECC_CTRL_ECCREG5 0x005
79 #define GPMC_ECC_CTRL_ECCREG6 0x006
80 #define GPMC_ECC_CTRL_ECCREG7 0x007
81 #define GPMC_ECC_CTRL_ECCREG8 0x008
82 #define GPMC_ECC_CTRL_ECCREG9 0x009
84 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
85 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
86 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
87 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
88 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
89 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
91 #define GPMC_CS0_OFFSET 0x60
92 #define GPMC_CS_SIZE 0x30
93 #define GPMC_BCH_SIZE 0x10
95 #define GPMC_MEM_END 0x3FFFFFFF
97 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
98 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
100 #define CS_NUM_SHIFT 24
101 #define ENABLE_PREFETCH (0x1 << 7)
102 #define DMA_MPU_MODE 2
104 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
105 #define GPMC_REVISION_MINOR(l) (l & 0xf)
107 #define GPMC_HAS_WR_ACCESS 0x1
108 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
109 #define GPMC_HAS_MUX_AAD 0x4
111 #define GPMC_NR_WAITPINS 4
113 /* XXX: Only NAND irq has been considered,currently these are the only ones used
115 #define GPMC_NR_IRQ 2
117 struct gpmc_client_irq
{
122 /* Structure to save gpmc cs context */
123 struct gpmc_cs_config
{
135 * Structure to save/restore gpmc context
136 * to support core off on OMAP3
138 struct omap3_gpmc_regs
{
143 u32 prefetch_config1
;
144 u32 prefetch_config2
;
145 u32 prefetch_control
;
146 struct gpmc_cs_config cs_context
[GPMC_CS_NUM
];
149 static struct gpmc_client_irq gpmc_client_irq
[GPMC_NR_IRQ
];
150 static struct irq_chip gpmc_irq_chip
;
151 static unsigned gpmc_irq_start
;
153 static struct resource gpmc_mem_root
;
154 static struct resource gpmc_cs_mem
[GPMC_CS_NUM
];
155 static DEFINE_SPINLOCK(gpmc_mem_lock
);
156 /* Define chip-selects as reserved by default until probe completes */
157 static unsigned int gpmc_cs_map
= ((1 << GPMC_CS_NUM
) - 1);
158 static unsigned int gpmc_cs_num
= GPMC_CS_NUM
;
159 static unsigned int gpmc_nr_waitpins
;
160 static struct device
*gpmc_dev
;
162 static resource_size_t phys_base
, mem_size
;
163 static unsigned gpmc_capability
;
164 static void __iomem
*gpmc_base
;
166 static struct clk
*gpmc_l3_clk
;
168 static irqreturn_t
gpmc_handle_irq(int irq
, void *dev
);
170 static void gpmc_write_reg(int idx
, u32 val
)
172 __raw_writel(val
, gpmc_base
+ idx
);
175 static u32
gpmc_read_reg(int idx
)
177 return __raw_readl(gpmc_base
+ idx
);
180 void gpmc_cs_write_reg(int cs
, int idx
, u32 val
)
182 void __iomem
*reg_addr
;
184 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
185 __raw_writel(val
, reg_addr
);
188 static u32
gpmc_cs_read_reg(int cs
, int idx
)
190 void __iomem
*reg_addr
;
192 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
193 return __raw_readl(reg_addr
);
196 /* TODO: Add support for gpmc_fck to clock framework and use it */
197 static unsigned long gpmc_get_fclk_period(void)
199 unsigned long rate
= clk_get_rate(gpmc_l3_clk
);
202 printk(KERN_WARNING
"gpmc_l3_clk not enabled\n");
207 rate
= 1000000000 / rate
; /* In picoseconds */
212 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns
)
214 unsigned long tick_ps
;
216 /* Calculate in picosecs to yield more exact results */
217 tick_ps
= gpmc_get_fclk_period();
219 return (time_ns
* 1000 + tick_ps
- 1) / tick_ps
;
222 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps
)
224 unsigned long tick_ps
;
226 /* Calculate in picosecs to yield more exact results */
227 tick_ps
= gpmc_get_fclk_period();
229 return (time_ps
+ tick_ps
- 1) / tick_ps
;
232 unsigned int gpmc_ticks_to_ns(unsigned int ticks
)
234 return ticks
* gpmc_get_fclk_period() / 1000;
237 static unsigned int gpmc_ticks_to_ps(unsigned int ticks
)
239 return ticks
* gpmc_get_fclk_period();
242 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps
)
244 unsigned long ticks
= gpmc_ps_to_ticks(time_ps
);
246 return ticks
* gpmc_get_fclk_period();
249 static inline void gpmc_cs_modify_reg(int cs
, int reg
, u32 mask
, bool value
)
253 l
= gpmc_cs_read_reg(cs
, reg
);
258 gpmc_cs_write_reg(cs
, reg
, l
);
261 static void gpmc_cs_bool_timings(int cs
, const struct gpmc_bool_timings
*p
)
263 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG1
,
264 GPMC_CONFIG1_TIME_PARA_GRAN
,
265 p
->time_para_granularity
);
266 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG2
,
267 GPMC_CONFIG2_CSEXTRADELAY
, p
->cs_extra_delay
);
268 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG3
,
269 GPMC_CONFIG3_ADVEXTRADELAY
, p
->adv_extra_delay
);
270 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG4
,
271 GPMC_CONFIG4_OEEXTRADELAY
, p
->oe_extra_delay
);
272 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG4
,
273 GPMC_CONFIG4_OEEXTRADELAY
, p
->we_extra_delay
);
274 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG6
,
275 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN
,
276 p
->cycle2cyclesamecsen
);
277 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG6
,
278 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN
,
279 p
->cycle2cyclediffcsen
);
283 static int set_gpmc_timing_reg(int cs
, int reg
, int st_bit
, int end_bit
,
284 int time
, const char *name
)
286 static int set_gpmc_timing_reg(int cs
, int reg
, int st_bit
, int end_bit
,
291 int ticks
, mask
, nr_bits
;
296 ticks
= gpmc_ns_to_ticks(time
);
297 nr_bits
= end_bit
- st_bit
+ 1;
298 if (ticks
>= 1 << nr_bits
) {
300 printk(KERN_INFO
"GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
301 cs
, name
, time
, ticks
, 1 << nr_bits
);
306 mask
= (1 << nr_bits
) - 1;
307 l
= gpmc_cs_read_reg(cs
, reg
);
310 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
311 cs
, name
, ticks
, gpmc_get_fclk_period() * ticks
/ 1000,
312 (l
>> st_bit
) & mask
, time
);
314 l
&= ~(mask
<< st_bit
);
315 l
|= ticks
<< st_bit
;
316 gpmc_cs_write_reg(cs
, reg
, l
);
322 #define GPMC_SET_ONE(reg, st, end, field) \
323 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
324 t->field, #field) < 0) \
327 #define GPMC_SET_ONE(reg, st, end, field) \
328 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
332 int gpmc_calc_divider(unsigned int sync_clk
)
337 l
= sync_clk
+ (gpmc_get_fclk_period() - 1);
338 div
= l
/ gpmc_get_fclk_period();
347 int gpmc_cs_set_timings(int cs
, const struct gpmc_timings
*t
)
352 div
= gpmc_calc_divider(t
->sync_clk
);
356 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 0, 3, cs_on
);
357 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 8, 12, cs_rd_off
);
358 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 16, 20, cs_wr_off
);
360 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 0, 3, adv_on
);
361 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 8, 12, adv_rd_off
);
362 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 16, 20, adv_wr_off
);
364 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 0, 3, oe_on
);
365 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 8, 12, oe_off
);
366 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 16, 19, we_on
);
367 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 24, 28, we_off
);
369 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 0, 4, rd_cycle
);
370 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 8, 12, wr_cycle
);
371 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 16, 20, access
);
373 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 24, 27, page_burst_access
);
375 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 0, 3, bus_turnaround
);
376 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 8, 11, cycle2cycle_delay
);
378 GPMC_SET_ONE(GPMC_CS_CONFIG1
, 18, 19, wait_monitoring
);
379 GPMC_SET_ONE(GPMC_CS_CONFIG1
, 25, 26, clk_activation
);
381 if (gpmc_capability
& GPMC_HAS_WR_DATA_MUX_BUS
)
382 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 16, 19, wr_data_mux_bus
);
383 if (gpmc_capability
& GPMC_HAS_WR_ACCESS
)
384 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 24, 28, wr_access
);
386 /* caller is expected to have initialized CONFIG1 to cover
387 * at least sync vs async
389 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG1
);
390 if (l
& (GPMC_CONFIG1_READTYPE_SYNC
| GPMC_CONFIG1_WRITETYPE_SYNC
)) {
392 printk(KERN_INFO
"GPMC CS%d CLK period is %lu ns (div %d)\n",
393 cs
, (div
* gpmc_get_fclk_period()) / 1000, div
);
397 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, l
);
400 gpmc_cs_bool_timings(cs
, &t
->bool_timings
);
405 static int gpmc_cs_enable_mem(int cs
, u32 base
, u32 size
)
411 * Ensure that base address is aligned on a
412 * boundary equal to or greater than size.
414 if (base
& (size
- 1))
417 mask
= (1 << GPMC_SECTION_SHIFT
) - size
;
418 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
420 l
= (base
>> GPMC_CHUNK_SHIFT
) & 0x3f;
422 l
|= ((mask
>> GPMC_CHUNK_SHIFT
) & 0x0f) << 8;
423 l
|= GPMC_CONFIG7_CSVALID
;
424 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
429 static void gpmc_cs_disable_mem(int cs
)
433 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
434 l
&= ~GPMC_CONFIG7_CSVALID
;
435 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
438 static void gpmc_cs_get_memconf(int cs
, u32
*base
, u32
*size
)
443 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
444 *base
= (l
& 0x3f) << GPMC_CHUNK_SHIFT
;
445 mask
= (l
>> 8) & 0x0f;
446 *size
= (1 << GPMC_SECTION_SHIFT
) - (mask
<< GPMC_CHUNK_SHIFT
);
449 static int gpmc_cs_mem_enabled(int cs
)
453 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
454 return l
& GPMC_CONFIG7_CSVALID
;
457 static void gpmc_cs_set_reserved(int cs
, int reserved
)
459 gpmc_cs_map
&= ~(1 << cs
);
460 gpmc_cs_map
|= (reserved
? 1 : 0) << cs
;
463 static bool gpmc_cs_reserved(int cs
)
465 return gpmc_cs_map
& (1 << cs
);
468 static unsigned long gpmc_mem_align(unsigned long size
)
472 size
= (size
- 1) >> (GPMC_CHUNK_SHIFT
- 1);
473 order
= GPMC_CHUNK_SHIFT
- 1;
482 static int gpmc_cs_insert_mem(int cs
, unsigned long base
, unsigned long size
)
484 struct resource
*res
= &gpmc_cs_mem
[cs
];
487 size
= gpmc_mem_align(size
);
488 spin_lock(&gpmc_mem_lock
);
490 res
->end
= base
+ size
- 1;
491 r
= request_resource(&gpmc_mem_root
, res
);
492 spin_unlock(&gpmc_mem_lock
);
497 static int gpmc_cs_delete_mem(int cs
)
499 struct resource
*res
= &gpmc_cs_mem
[cs
];
502 spin_lock(&gpmc_mem_lock
);
503 r
= release_resource(&gpmc_cs_mem
[cs
]);
506 spin_unlock(&gpmc_mem_lock
);
512 * gpmc_cs_remap - remaps a chip-select physical base address
513 * @cs: chip-select to remap
514 * @base: physical base address to re-map chip-select to
516 * Re-maps a chip-select to a new physical base address specified by
517 * "base". Returns 0 on success and appropriate negative error code
520 static int gpmc_cs_remap(int cs
, u32 base
)
525 if (cs
> gpmc_cs_num
) {
526 pr_err("%s: requested chip-select is disabled\n", __func__
);
529 gpmc_cs_get_memconf(cs
, &old_base
, &size
);
530 if (base
== old_base
)
532 gpmc_cs_disable_mem(cs
);
533 ret
= gpmc_cs_delete_mem(cs
);
536 ret
= gpmc_cs_insert_mem(cs
, base
, size
);
539 ret
= gpmc_cs_enable_mem(cs
, base
, size
);
546 int gpmc_cs_request(int cs
, unsigned long size
, unsigned long *base
)
548 struct resource
*res
= &gpmc_cs_mem
[cs
];
551 if (cs
> gpmc_cs_num
) {
552 pr_err("%s: requested chip-select is disabled\n", __func__
);
555 size
= gpmc_mem_align(size
);
556 if (size
> (1 << GPMC_SECTION_SHIFT
))
559 spin_lock(&gpmc_mem_lock
);
560 if (gpmc_cs_reserved(cs
)) {
564 if (gpmc_cs_mem_enabled(cs
))
565 r
= adjust_resource(res
, res
->start
& ~(size
- 1), size
);
567 r
= allocate_resource(&gpmc_mem_root
, res
, size
, 0, ~0,
572 r
= gpmc_cs_enable_mem(cs
, res
->start
, resource_size(res
));
574 release_resource(res
);
579 gpmc_cs_set_reserved(cs
, 1);
581 spin_unlock(&gpmc_mem_lock
);
584 EXPORT_SYMBOL(gpmc_cs_request
);
586 void gpmc_cs_free(int cs
)
588 spin_lock(&gpmc_mem_lock
);
589 if (cs
>= gpmc_cs_num
|| cs
< 0 || !gpmc_cs_reserved(cs
)) {
590 printk(KERN_ERR
"Trying to free non-reserved GPMC CS%d\n", cs
);
592 spin_unlock(&gpmc_mem_lock
);
595 gpmc_cs_disable_mem(cs
);
596 release_resource(&gpmc_cs_mem
[cs
]);
597 gpmc_cs_set_reserved(cs
, 0);
598 spin_unlock(&gpmc_mem_lock
);
600 EXPORT_SYMBOL(gpmc_cs_free
);
603 * gpmc_configure - write request to configure gpmc
605 * @wval: value to write
606 * @return status of the operation
608 int gpmc_configure(int cmd
, int wval
)
613 case GPMC_ENABLE_IRQ
:
614 gpmc_write_reg(GPMC_IRQENABLE
, wval
);
617 case GPMC_SET_IRQ_STATUS
:
618 gpmc_write_reg(GPMC_IRQSTATUS
, wval
);
622 regval
= gpmc_read_reg(GPMC_CONFIG
);
624 regval
&= ~GPMC_CONFIG_WRITEPROTECT
; /* WP is ON */
626 regval
|= GPMC_CONFIG_WRITEPROTECT
; /* WP is OFF */
627 gpmc_write_reg(GPMC_CONFIG
, regval
);
631 pr_err("%s: command not supported\n", __func__
);
637 EXPORT_SYMBOL(gpmc_configure
);
639 void gpmc_update_nand_reg(struct gpmc_nand_regs
*reg
, int cs
)
643 reg
->gpmc_status
= gpmc_base
+ GPMC_STATUS
;
644 reg
->gpmc_nand_command
= gpmc_base
+ GPMC_CS0_OFFSET
+
645 GPMC_CS_NAND_COMMAND
+ GPMC_CS_SIZE
* cs
;
646 reg
->gpmc_nand_address
= gpmc_base
+ GPMC_CS0_OFFSET
+
647 GPMC_CS_NAND_ADDRESS
+ GPMC_CS_SIZE
* cs
;
648 reg
->gpmc_nand_data
= gpmc_base
+ GPMC_CS0_OFFSET
+
649 GPMC_CS_NAND_DATA
+ GPMC_CS_SIZE
* cs
;
650 reg
->gpmc_prefetch_config1
= gpmc_base
+ GPMC_PREFETCH_CONFIG1
;
651 reg
->gpmc_prefetch_config2
= gpmc_base
+ GPMC_PREFETCH_CONFIG2
;
652 reg
->gpmc_prefetch_control
= gpmc_base
+ GPMC_PREFETCH_CONTROL
;
653 reg
->gpmc_prefetch_status
= gpmc_base
+ GPMC_PREFETCH_STATUS
;
654 reg
->gpmc_ecc_config
= gpmc_base
+ GPMC_ECC_CONFIG
;
655 reg
->gpmc_ecc_control
= gpmc_base
+ GPMC_ECC_CONTROL
;
656 reg
->gpmc_ecc_size_config
= gpmc_base
+ GPMC_ECC_SIZE_CONFIG
;
657 reg
->gpmc_ecc1_result
= gpmc_base
+ GPMC_ECC1_RESULT
;
659 for (i
= 0; i
< GPMC_BCH_NUM_REMAINDER
; i
++) {
660 reg
->gpmc_bch_result0
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_0
+
662 reg
->gpmc_bch_result1
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_1
+
664 reg
->gpmc_bch_result2
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_2
+
666 reg
->gpmc_bch_result3
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_3
+
671 int gpmc_get_client_irq(unsigned irq_config
)
675 if (hweight32(irq_config
) > 1)
678 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
679 if (gpmc_client_irq
[i
].bitmask
& irq_config
)
680 return gpmc_client_irq
[i
].irq
;
685 static int gpmc_irq_endis(unsigned irq
, bool endis
)
690 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
691 if (irq
== gpmc_client_irq
[i
].irq
) {
692 regval
= gpmc_read_reg(GPMC_IRQENABLE
);
694 regval
|= gpmc_client_irq
[i
].bitmask
;
696 regval
&= ~gpmc_client_irq
[i
].bitmask
;
697 gpmc_write_reg(GPMC_IRQENABLE
, regval
);
704 static void gpmc_irq_disable(struct irq_data
*p
)
706 gpmc_irq_endis(p
->irq
, false);
709 static void gpmc_irq_enable(struct irq_data
*p
)
711 gpmc_irq_endis(p
->irq
, true);
714 static void gpmc_irq_noop(struct irq_data
*data
) { }
716 static unsigned int gpmc_irq_noop_ret(struct irq_data
*data
) { return 0; }
718 static int gpmc_setup_irq(void)
726 gpmc_irq_start
= irq_alloc_descs(-1, 0, GPMC_NR_IRQ
, 0);
727 if (gpmc_irq_start
< 0) {
728 pr_err("irq_alloc_descs failed\n");
729 return gpmc_irq_start
;
732 gpmc_irq_chip
.name
= "gpmc";
733 gpmc_irq_chip
.irq_startup
= gpmc_irq_noop_ret
;
734 gpmc_irq_chip
.irq_enable
= gpmc_irq_enable
;
735 gpmc_irq_chip
.irq_disable
= gpmc_irq_disable
;
736 gpmc_irq_chip
.irq_shutdown
= gpmc_irq_noop
;
737 gpmc_irq_chip
.irq_ack
= gpmc_irq_noop
;
738 gpmc_irq_chip
.irq_mask
= gpmc_irq_noop
;
739 gpmc_irq_chip
.irq_unmask
= gpmc_irq_noop
;
741 gpmc_client_irq
[0].bitmask
= GPMC_IRQ_FIFOEVENTENABLE
;
742 gpmc_client_irq
[1].bitmask
= GPMC_IRQ_COUNT_EVENT
;
744 for (i
= 0; i
< GPMC_NR_IRQ
; i
++) {
745 gpmc_client_irq
[i
].irq
= gpmc_irq_start
+ i
;
746 irq_set_chip_and_handler(gpmc_client_irq
[i
].irq
,
747 &gpmc_irq_chip
, handle_simple_irq
);
748 set_irq_flags(gpmc_client_irq
[i
].irq
,
749 IRQF_VALID
| IRQF_NOAUTOEN
);
752 /* Disable interrupts */
753 gpmc_write_reg(GPMC_IRQENABLE
, 0);
755 /* clear interrupts */
756 regval
= gpmc_read_reg(GPMC_IRQSTATUS
);
757 gpmc_write_reg(GPMC_IRQSTATUS
, regval
);
759 return request_irq(gpmc_irq
, gpmc_handle_irq
, 0, "gpmc", NULL
);
762 static int gpmc_free_irq(void)
767 free_irq(gpmc_irq
, NULL
);
769 for (i
= 0; i
< GPMC_NR_IRQ
; i
++) {
770 irq_set_handler(gpmc_client_irq
[i
].irq
, NULL
);
771 irq_set_chip(gpmc_client_irq
[i
].irq
, &no_irq_chip
);
772 irq_modify_status(gpmc_client_irq
[i
].irq
, 0, 0);
775 irq_free_descs(gpmc_irq_start
, GPMC_NR_IRQ
);
780 static void gpmc_mem_exit(void)
784 for (cs
= 0; cs
< gpmc_cs_num
; cs
++) {
785 if (!gpmc_cs_mem_enabled(cs
))
787 gpmc_cs_delete_mem(cs
);
792 static void gpmc_mem_init(void)
797 * The first 1MB of GPMC address space is typically mapped to
798 * the internal ROM. Never allocate the first page, to
799 * facilitate bug detection; even if we didn't boot from ROM.
801 gpmc_mem_root
.start
= SZ_1M
;
802 gpmc_mem_root
.end
= GPMC_MEM_END
;
804 /* Reserve all regions that has been set up by bootloader */
805 for (cs
= 0; cs
< gpmc_cs_num
; cs
++) {
808 if (!gpmc_cs_mem_enabled(cs
))
810 gpmc_cs_get_memconf(cs
, &base
, &size
);
811 if (gpmc_cs_insert_mem(cs
, base
, size
)) {
812 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
813 __func__
, cs
, base
, base
+ size
);
814 gpmc_cs_disable_mem(cs
);
819 static u32
gpmc_round_ps_to_sync_clk(u32 time_ps
, u32 sync_clk
)
824 div
= gpmc_calc_divider(sync_clk
);
825 temp
= gpmc_ps_to_ticks(time_ps
);
826 temp
= (temp
+ div
- 1) / div
;
827 return gpmc_ticks_to_ps(temp
* div
);
830 /* XXX: can the cycles be avoided ? */
831 static int gpmc_calc_sync_read_timings(struct gpmc_timings
*gpmc_t
,
832 struct gpmc_device_timings
*dev_t
,
838 temp
= dev_t
->t_avdp_r
;
839 /* XXX: mux check required ? */
841 /* XXX: t_avdp not to be required for sync, only added for tusb
842 * this indirectly necessitates requirement of t_avdp_r and
843 * t_avdp_w instead of having a single t_avdp
845 temp
= max_t(u32
, temp
, gpmc_t
->clk_activation
+ dev_t
->t_avdh
);
846 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
848 gpmc_t
->adv_rd_off
= gpmc_round_ps_to_ticks(temp
);
851 temp
= dev_t
->t_oeasu
; /* XXX: remove this ? */
853 temp
= max_t(u32
, temp
, gpmc_t
->clk_activation
+ dev_t
->t_ach
);
854 temp
= max_t(u32
, temp
, gpmc_t
->adv_rd_off
+
855 gpmc_ticks_to_ps(dev_t
->cyc_aavdh_oe
));
857 gpmc_t
->oe_on
= gpmc_round_ps_to_ticks(temp
);
860 /* XXX: any scope for improvement ?, by combining oe_on
861 * and clk_activation, need to check whether
862 * access = clk_activation + round to sync clk ?
864 temp
= max_t(u32
, dev_t
->t_iaa
, dev_t
->cyc_iaa
* gpmc_t
->sync_clk
);
865 temp
+= gpmc_t
->clk_activation
;
867 temp
= max_t(u32
, temp
, gpmc_t
->oe_on
+
868 gpmc_ticks_to_ps(dev_t
->cyc_oe
));
869 gpmc_t
->access
= gpmc_round_ps_to_ticks(temp
);
871 gpmc_t
->oe_off
= gpmc_t
->access
+ gpmc_ticks_to_ps(1);
872 gpmc_t
->cs_rd_off
= gpmc_t
->oe_off
;
875 temp
= max_t(u32
, dev_t
->t_cez_r
, dev_t
->t_oez
);
876 temp
= gpmc_round_ps_to_sync_clk(temp
, gpmc_t
->sync_clk
) +
878 /* XXX: barter t_ce_rdyz with t_cez_r ? */
879 if (dev_t
->t_ce_rdyz
)
880 temp
= max_t(u32
, temp
, gpmc_t
->cs_rd_off
+ dev_t
->t_ce_rdyz
);
881 gpmc_t
->rd_cycle
= gpmc_round_ps_to_ticks(temp
);
886 static int gpmc_calc_sync_write_timings(struct gpmc_timings
*gpmc_t
,
887 struct gpmc_device_timings
*dev_t
,
893 temp
= dev_t
->t_avdp_w
;
895 temp
= max_t(u32
, temp
,
896 gpmc_t
->clk_activation
+ dev_t
->t_avdh
);
897 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
899 gpmc_t
->adv_wr_off
= gpmc_round_ps_to_ticks(temp
);
901 /* wr_data_mux_bus */
902 temp
= max_t(u32
, dev_t
->t_weasu
,
903 gpmc_t
->clk_activation
+ dev_t
->t_rdyo
);
904 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
905 * and in that case remember to handle we_on properly
908 temp
= max_t(u32
, temp
,
909 gpmc_t
->adv_wr_off
+ dev_t
->t_aavdh
);
910 temp
= max_t(u32
, temp
, gpmc_t
->adv_wr_off
+
911 gpmc_ticks_to_ps(dev_t
->cyc_aavdh_we
));
913 gpmc_t
->wr_data_mux_bus
= gpmc_round_ps_to_ticks(temp
);
916 if (gpmc_capability
& GPMC_HAS_WR_DATA_MUX_BUS
)
917 gpmc_t
->we_on
= gpmc_round_ps_to_ticks(dev_t
->t_weasu
);
919 gpmc_t
->we_on
= gpmc_t
->wr_data_mux_bus
;
922 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
923 gpmc_t
->wr_access
= gpmc_t
->access
;
926 temp
= gpmc_t
->we_on
+ dev_t
->t_wpl
;
927 temp
= max_t(u32
, temp
,
928 gpmc_t
->wr_access
+ gpmc_ticks_to_ps(1));
929 temp
= max_t(u32
, temp
,
930 gpmc_t
->we_on
+ gpmc_ticks_to_ps(dev_t
->cyc_wpl
));
931 gpmc_t
->we_off
= gpmc_round_ps_to_ticks(temp
);
933 gpmc_t
->cs_wr_off
= gpmc_round_ps_to_ticks(gpmc_t
->we_off
+
937 temp
= gpmc_round_ps_to_sync_clk(dev_t
->t_cez_w
, gpmc_t
->sync_clk
);
938 temp
+= gpmc_t
->wr_access
;
939 /* XXX: barter t_ce_rdyz with t_cez_w ? */
940 if (dev_t
->t_ce_rdyz
)
941 temp
= max_t(u32
, temp
,
942 gpmc_t
->cs_wr_off
+ dev_t
->t_ce_rdyz
);
943 gpmc_t
->wr_cycle
= gpmc_round_ps_to_ticks(temp
);
948 static int gpmc_calc_async_read_timings(struct gpmc_timings
*gpmc_t
,
949 struct gpmc_device_timings
*dev_t
,
955 temp
= dev_t
->t_avdp_r
;
957 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
958 gpmc_t
->adv_rd_off
= gpmc_round_ps_to_ticks(temp
);
961 temp
= dev_t
->t_oeasu
;
963 temp
= max_t(u32
, temp
,
964 gpmc_t
->adv_rd_off
+ dev_t
->t_aavdh
);
965 gpmc_t
->oe_on
= gpmc_round_ps_to_ticks(temp
);
968 temp
= max_t(u32
, dev_t
->t_iaa
, /* XXX: remove t_iaa in async ? */
969 gpmc_t
->oe_on
+ dev_t
->t_oe
);
970 temp
= max_t(u32
, temp
,
971 gpmc_t
->cs_on
+ dev_t
->t_ce
);
972 temp
= max_t(u32
, temp
,
973 gpmc_t
->adv_on
+ dev_t
->t_aa
);
974 gpmc_t
->access
= gpmc_round_ps_to_ticks(temp
);
976 gpmc_t
->oe_off
= gpmc_t
->access
+ gpmc_ticks_to_ps(1);
977 gpmc_t
->cs_rd_off
= gpmc_t
->oe_off
;
980 temp
= max_t(u32
, dev_t
->t_rd_cycle
,
981 gpmc_t
->cs_rd_off
+ dev_t
->t_cez_r
);
982 temp
= max_t(u32
, temp
, gpmc_t
->oe_off
+ dev_t
->t_oez
);
983 gpmc_t
->rd_cycle
= gpmc_round_ps_to_ticks(temp
);
988 static int gpmc_calc_async_write_timings(struct gpmc_timings
*gpmc_t
,
989 struct gpmc_device_timings
*dev_t
,
995 temp
= dev_t
->t_avdp_w
;
997 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
998 gpmc_t
->adv_wr_off
= gpmc_round_ps_to_ticks(temp
);
1000 /* wr_data_mux_bus */
1001 temp
= dev_t
->t_weasu
;
1003 temp
= max_t(u32
, temp
, gpmc_t
->adv_wr_off
+ dev_t
->t_aavdh
);
1004 temp
= max_t(u32
, temp
, gpmc_t
->adv_wr_off
+
1005 gpmc_ticks_to_ps(dev_t
->cyc_aavdh_we
));
1007 gpmc_t
->wr_data_mux_bus
= gpmc_round_ps_to_ticks(temp
);
1010 if (gpmc_capability
& GPMC_HAS_WR_DATA_MUX_BUS
)
1011 gpmc_t
->we_on
= gpmc_round_ps_to_ticks(dev_t
->t_weasu
);
1013 gpmc_t
->we_on
= gpmc_t
->wr_data_mux_bus
;
1016 temp
= gpmc_t
->we_on
+ dev_t
->t_wpl
;
1017 gpmc_t
->we_off
= gpmc_round_ps_to_ticks(temp
);
1019 gpmc_t
->cs_wr_off
= gpmc_round_ps_to_ticks(gpmc_t
->we_off
+
1023 temp
= max_t(u32
, dev_t
->t_wr_cycle
,
1024 gpmc_t
->cs_wr_off
+ dev_t
->t_cez_w
);
1025 gpmc_t
->wr_cycle
= gpmc_round_ps_to_ticks(temp
);
1030 static int gpmc_calc_sync_common_timings(struct gpmc_timings
*gpmc_t
,
1031 struct gpmc_device_timings
*dev_t
)
1035 gpmc_t
->sync_clk
= gpmc_calc_divider(dev_t
->clk
) *
1036 gpmc_get_fclk_period();
1038 gpmc_t
->page_burst_access
= gpmc_round_ps_to_sync_clk(
1042 temp
= max_t(u32
, dev_t
->t_ces
, dev_t
->t_avds
);
1043 gpmc_t
->clk_activation
= gpmc_round_ps_to_ticks(temp
);
1045 if (gpmc_calc_divider(gpmc_t
->sync_clk
) != 1)
1048 if (dev_t
->ce_xdelay
)
1049 gpmc_t
->bool_timings
.cs_extra_delay
= true;
1050 if (dev_t
->avd_xdelay
)
1051 gpmc_t
->bool_timings
.adv_extra_delay
= true;
1052 if (dev_t
->oe_xdelay
)
1053 gpmc_t
->bool_timings
.oe_extra_delay
= true;
1054 if (dev_t
->we_xdelay
)
1055 gpmc_t
->bool_timings
.we_extra_delay
= true;
1060 static int gpmc_calc_common_timings(struct gpmc_timings
*gpmc_t
,
1061 struct gpmc_device_timings
*dev_t
,
1067 gpmc_t
->cs_on
= gpmc_round_ps_to_ticks(dev_t
->t_ceasu
);
1070 temp
= dev_t
->t_avdasu
;
1071 if (dev_t
->t_ce_avd
)
1072 temp
= max_t(u32
, temp
,
1073 gpmc_t
->cs_on
+ dev_t
->t_ce_avd
);
1074 gpmc_t
->adv_on
= gpmc_round_ps_to_ticks(temp
);
1077 gpmc_calc_sync_common_timings(gpmc_t
, dev_t
);
1082 /* TODO: remove this function once all peripherals are confirmed to
1083 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1084 * has to be modified to handle timings in ps instead of ns
1086 static void gpmc_convert_ps_to_ns(struct gpmc_timings
*t
)
1089 t
->cs_rd_off
/= 1000;
1090 t
->cs_wr_off
/= 1000;
1092 t
->adv_rd_off
/= 1000;
1093 t
->adv_wr_off
/= 1000;
1098 t
->page_burst_access
/= 1000;
1100 t
->rd_cycle
/= 1000;
1101 t
->wr_cycle
/= 1000;
1102 t
->bus_turnaround
/= 1000;
1103 t
->cycle2cycle_delay
/= 1000;
1104 t
->wait_monitoring
/= 1000;
1105 t
->clk_activation
/= 1000;
1106 t
->wr_access
/= 1000;
1107 t
->wr_data_mux_bus
/= 1000;
1110 int gpmc_calc_timings(struct gpmc_timings
*gpmc_t
,
1111 struct gpmc_settings
*gpmc_s
,
1112 struct gpmc_device_timings
*dev_t
)
1114 bool mux
= false, sync
= false;
1117 mux
= gpmc_s
->mux_add_data
? true : false;
1118 sync
= (gpmc_s
->sync_read
|| gpmc_s
->sync_write
);
1121 memset(gpmc_t
, 0, sizeof(*gpmc_t
));
1123 gpmc_calc_common_timings(gpmc_t
, dev_t
, sync
);
1125 if (gpmc_s
&& gpmc_s
->sync_read
)
1126 gpmc_calc_sync_read_timings(gpmc_t
, dev_t
, mux
);
1128 gpmc_calc_async_read_timings(gpmc_t
, dev_t
, mux
);
1130 if (gpmc_s
&& gpmc_s
->sync_write
)
1131 gpmc_calc_sync_write_timings(gpmc_t
, dev_t
, mux
);
1133 gpmc_calc_async_write_timings(gpmc_t
, dev_t
, mux
);
1135 /* TODO: remove, see function definition */
1136 gpmc_convert_ps_to_ns(gpmc_t
);
1142 * gpmc_cs_program_settings - programs non-timing related settings
1143 * @cs: GPMC chip-select to program
1144 * @p: pointer to GPMC settings structure
1146 * Programs non-timing related settings for a GPMC chip-select, such as
1147 * bus-width, burst configuration, etc. Function should be called once
1148 * for each chip-select that is being used and must be called before
1149 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1150 * register will be initialised to zero by this function. Returns 0 on
1151 * success and appropriate negative error code on failure.
1153 int gpmc_cs_program_settings(int cs
, struct gpmc_settings
*p
)
1157 if ((!p
->device_width
) || (p
->device_width
> GPMC_DEVWIDTH_16BIT
)) {
1158 pr_err("%s: invalid width %d!", __func__
, p
->device_width
);
1162 /* Address-data multiplexing not supported for NAND devices */
1163 if (p
->device_nand
&& p
->mux_add_data
) {
1164 pr_err("%s: invalid configuration!\n", __func__
);
1168 if ((p
->mux_add_data
> GPMC_MUX_AD
) ||
1169 ((p
->mux_add_data
== GPMC_MUX_AAD
) &&
1170 !(gpmc_capability
& GPMC_HAS_MUX_AAD
))) {
1171 pr_err("%s: invalid multiplex configuration!\n", __func__
);
1175 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1176 if (p
->burst_read
|| p
->burst_write
) {
1177 switch (p
->burst_len
) {
1183 pr_err("%s: invalid page/burst-length (%d)\n",
1184 __func__
, p
->burst_len
);
1189 if ((p
->wait_on_read
|| p
->wait_on_write
) &&
1190 (p
->wait_pin
> gpmc_nr_waitpins
)) {
1191 pr_err("%s: invalid wait-pin (%d)\n", __func__
, p
->wait_pin
);
1195 config1
= GPMC_CONFIG1_DEVICESIZE((p
->device_width
- 1));
1198 config1
|= GPMC_CONFIG1_READTYPE_SYNC
;
1200 config1
|= GPMC_CONFIG1_WRITETYPE_SYNC
;
1201 if (p
->wait_on_read
)
1202 config1
|= GPMC_CONFIG1_WAIT_READ_MON
;
1203 if (p
->wait_on_write
)
1204 config1
|= GPMC_CONFIG1_WAIT_WRITE_MON
;
1205 if (p
->wait_on_read
|| p
->wait_on_write
)
1206 config1
|= GPMC_CONFIG1_WAIT_PIN_SEL(p
->wait_pin
);
1208 config1
|= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND
);
1209 if (p
->mux_add_data
)
1210 config1
|= GPMC_CONFIG1_MUXTYPE(p
->mux_add_data
);
1212 config1
|= GPMC_CONFIG1_READMULTIPLE_SUPP
;
1214 config1
|= GPMC_CONFIG1_WRITEMULTIPLE_SUPP
;
1215 if (p
->burst_read
|| p
->burst_write
) {
1216 config1
|= GPMC_CONFIG1_PAGE_LEN(p
->burst_len
>> 3);
1217 config1
|= p
->burst_wrap
? GPMC_CONFIG1_WRAPBURST_SUPP
: 0;
1220 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, config1
);
1226 static struct of_device_id gpmc_dt_ids
[] = {
1227 { .compatible
= "ti,omap2420-gpmc" },
1228 { .compatible
= "ti,omap2430-gpmc" },
1229 { .compatible
= "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1230 { .compatible
= "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1231 { .compatible
= "ti,am3352-gpmc" }, /* am335x devices */
1234 MODULE_DEVICE_TABLE(of
, gpmc_dt_ids
);
1237 * gpmc_read_settings_dt - read gpmc settings from device-tree
1238 * @np: pointer to device-tree node for a gpmc child device
1239 * @p: pointer to gpmc settings structure
1241 * Reads the GPMC settings for a GPMC child device from device-tree and
1242 * stores them in the GPMC settings structure passed. The GPMC settings
1243 * structure is initialised to zero by this function and so any
1244 * previously stored settings will be cleared.
1246 void gpmc_read_settings_dt(struct device_node
*np
, struct gpmc_settings
*p
)
1248 memset(p
, 0, sizeof(struct gpmc_settings
));
1250 p
->sync_read
= of_property_read_bool(np
, "gpmc,sync-read");
1251 p
->sync_write
= of_property_read_bool(np
, "gpmc,sync-write");
1252 of_property_read_u32(np
, "gpmc,device-width", &p
->device_width
);
1253 of_property_read_u32(np
, "gpmc,mux-add-data", &p
->mux_add_data
);
1255 if (!of_property_read_u32(np
, "gpmc,burst-length", &p
->burst_len
)) {
1256 p
->burst_wrap
= of_property_read_bool(np
, "gpmc,burst-wrap");
1257 p
->burst_read
= of_property_read_bool(np
, "gpmc,burst-read");
1258 p
->burst_write
= of_property_read_bool(np
, "gpmc,burst-write");
1259 if (!p
->burst_read
&& !p
->burst_write
)
1260 pr_warn("%s: page/burst-length set but not used!\n",
1264 if (!of_property_read_u32(np
, "gpmc,wait-pin", &p
->wait_pin
)) {
1265 p
->wait_on_read
= of_property_read_bool(np
,
1266 "gpmc,wait-on-read");
1267 p
->wait_on_write
= of_property_read_bool(np
,
1268 "gpmc,wait-on-write");
1269 if (!p
->wait_on_read
&& !p
->wait_on_write
)
1270 pr_warn("%s: read/write wait monitoring not enabled!\n",
1275 static void __maybe_unused
gpmc_read_timings_dt(struct device_node
*np
,
1276 struct gpmc_timings
*gpmc_t
)
1278 struct gpmc_bool_timings
*p
;
1283 memset(gpmc_t
, 0, sizeof(*gpmc_t
));
1285 /* minimum clock period for syncronous mode */
1286 of_property_read_u32(np
, "gpmc,sync-clk-ps", &gpmc_t
->sync_clk
);
1288 /* chip select timtings */
1289 of_property_read_u32(np
, "gpmc,cs-on-ns", &gpmc_t
->cs_on
);
1290 of_property_read_u32(np
, "gpmc,cs-rd-off-ns", &gpmc_t
->cs_rd_off
);
1291 of_property_read_u32(np
, "gpmc,cs-wr-off-ns", &gpmc_t
->cs_wr_off
);
1293 /* ADV signal timings */
1294 of_property_read_u32(np
, "gpmc,adv-on-ns", &gpmc_t
->adv_on
);
1295 of_property_read_u32(np
, "gpmc,adv-rd-off-ns", &gpmc_t
->adv_rd_off
);
1296 of_property_read_u32(np
, "gpmc,adv-wr-off-ns", &gpmc_t
->adv_wr_off
);
1298 /* WE signal timings */
1299 of_property_read_u32(np
, "gpmc,we-on-ns", &gpmc_t
->we_on
);
1300 of_property_read_u32(np
, "gpmc,we-off-ns", &gpmc_t
->we_off
);
1302 /* OE signal timings */
1303 of_property_read_u32(np
, "gpmc,oe-on-ns", &gpmc_t
->oe_on
);
1304 of_property_read_u32(np
, "gpmc,oe-off-ns", &gpmc_t
->oe_off
);
1306 /* access and cycle timings */
1307 of_property_read_u32(np
, "gpmc,page-burst-access-ns",
1308 &gpmc_t
->page_burst_access
);
1309 of_property_read_u32(np
, "gpmc,access-ns", &gpmc_t
->access
);
1310 of_property_read_u32(np
, "gpmc,rd-cycle-ns", &gpmc_t
->rd_cycle
);
1311 of_property_read_u32(np
, "gpmc,wr-cycle-ns", &gpmc_t
->wr_cycle
);
1312 of_property_read_u32(np
, "gpmc,bus-turnaround-ns",
1313 &gpmc_t
->bus_turnaround
);
1314 of_property_read_u32(np
, "gpmc,cycle2cycle-delay-ns",
1315 &gpmc_t
->cycle2cycle_delay
);
1316 of_property_read_u32(np
, "gpmc,wait-monitoring-ns",
1317 &gpmc_t
->wait_monitoring
);
1318 of_property_read_u32(np
, "gpmc,clk-activation-ns",
1319 &gpmc_t
->clk_activation
);
1321 /* only applicable to OMAP3+ */
1322 of_property_read_u32(np
, "gpmc,wr-access-ns", &gpmc_t
->wr_access
);
1323 of_property_read_u32(np
, "gpmc,wr-data-mux-bus-ns",
1324 &gpmc_t
->wr_data_mux_bus
);
1326 /* bool timing parameters */
1327 p
= &gpmc_t
->bool_timings
;
1329 p
->cycle2cyclediffcsen
=
1330 of_property_read_bool(np
, "gpmc,cycle2cycle-diffcsen");
1331 p
->cycle2cyclesamecsen
=
1332 of_property_read_bool(np
, "gpmc,cycle2cycle-samecsen");
1333 p
->we_extra_delay
= of_property_read_bool(np
, "gpmc,we-extra-delay");
1334 p
->oe_extra_delay
= of_property_read_bool(np
, "gpmc,oe-extra-delay");
1335 p
->adv_extra_delay
= of_property_read_bool(np
, "gpmc,adv-extra-delay");
1336 p
->cs_extra_delay
= of_property_read_bool(np
, "gpmc,cs-extra-delay");
1337 p
->time_para_granularity
=
1338 of_property_read_bool(np
, "gpmc,time-para-granularity");
1341 #ifdef CONFIG_MTD_NAND
1343 static const char * const nand_ecc_opts
[] = {
1344 [OMAP_ECC_HAMMING_CODE_DEFAULT
] = "sw",
1345 [OMAP_ECC_HAMMING_CODE_HW
] = "hw",
1346 [OMAP_ECC_HAMMING_CODE_HW_ROMCODE
] = "hw-romcode",
1347 [OMAP_ECC_BCH4_CODE_HW
] = "bch4",
1348 [OMAP_ECC_BCH8_CODE_HW
] = "bch8",
1351 static const char * const nand_xfer_types
[] = {
1352 [NAND_OMAP_PREFETCH_POLLED
] = "prefetch-polled",
1353 [NAND_OMAP_POLLED
] = "polled",
1354 [NAND_OMAP_PREFETCH_DMA
] = "prefetch-dma",
1355 [NAND_OMAP_PREFETCH_IRQ
] = "prefetch-irq",
1358 static int gpmc_probe_nand_child(struct platform_device
*pdev
,
1359 struct device_node
*child
)
1363 struct gpmc_timings gpmc_t
;
1364 struct omap_nand_platform_data
*gpmc_nand_data
;
1366 if (of_property_read_u32(child
, "reg", &val
) < 0) {
1367 dev_err(&pdev
->dev
, "%s has no 'reg' property\n",
1372 gpmc_nand_data
= devm_kzalloc(&pdev
->dev
, sizeof(*gpmc_nand_data
),
1374 if (!gpmc_nand_data
)
1377 gpmc_nand_data
->cs
= val
;
1378 gpmc_nand_data
->of_node
= child
;
1380 if (!of_property_read_string(child
, "ti,nand-ecc-opt", &s
))
1381 for (val
= 0; val
< ARRAY_SIZE(nand_ecc_opts
); val
++)
1382 if (!strcasecmp(s
, nand_ecc_opts
[val
])) {
1383 gpmc_nand_data
->ecc_opt
= val
;
1387 if (!of_property_read_string(child
, "ti,nand-xfer-type", &s
))
1388 for (val
= 0; val
< ARRAY_SIZE(nand_xfer_types
); val
++)
1389 if (!strcasecmp(s
, nand_xfer_types
[val
])) {
1390 gpmc_nand_data
->xfer_type
= val
;
1394 val
= of_get_nand_bus_width(child
);
1396 gpmc_nand_data
->devsize
= NAND_BUSWIDTH_16
;
1398 gpmc_read_timings_dt(child
, &gpmc_t
);
1399 gpmc_nand_init(gpmc_nand_data
, &gpmc_t
);
1404 static int gpmc_probe_nand_child(struct platform_device
*pdev
,
1405 struct device_node
*child
)
1411 #ifdef CONFIG_MTD_ONENAND
1412 static int gpmc_probe_onenand_child(struct platform_device
*pdev
,
1413 struct device_node
*child
)
1416 struct omap_onenand_platform_data
*gpmc_onenand_data
;
1418 if (of_property_read_u32(child
, "reg", &val
) < 0) {
1419 dev_err(&pdev
->dev
, "%s has no 'reg' property\n",
1424 gpmc_onenand_data
= devm_kzalloc(&pdev
->dev
, sizeof(*gpmc_onenand_data
),
1426 if (!gpmc_onenand_data
)
1429 gpmc_onenand_data
->cs
= val
;
1430 gpmc_onenand_data
->of_node
= child
;
1431 gpmc_onenand_data
->dma_channel
= -1;
1433 if (!of_property_read_u32(child
, "dma-channel", &val
))
1434 gpmc_onenand_data
->dma_channel
= val
;
1436 gpmc_onenand_init(gpmc_onenand_data
);
1441 static int gpmc_probe_onenand_child(struct platform_device
*pdev
,
1442 struct device_node
*child
)
1449 * gpmc_probe_generic_child - configures the gpmc for a child device
1450 * @pdev: pointer to gpmc platform device
1451 * @child: pointer to device-tree node for child device
1453 * Allocates and configures a GPMC chip-select for a child device.
1454 * Returns 0 on success and appropriate negative error code on failure.
1456 static int gpmc_probe_generic_child(struct platform_device
*pdev
,
1457 struct device_node
*child
)
1459 struct gpmc_settings gpmc_s
;
1460 struct gpmc_timings gpmc_t
;
1461 struct resource res
;
1465 if (of_property_read_u32(child
, "reg", &cs
) < 0) {
1466 dev_err(&pdev
->dev
, "%s has no 'reg' property\n",
1471 if (of_address_to_resource(child
, 0, &res
) < 0) {
1472 dev_err(&pdev
->dev
, "%s has malformed 'reg' property\n",
1477 ret
= gpmc_cs_request(cs
, resource_size(&res
), &base
);
1479 dev_err(&pdev
->dev
, "cannot request GPMC CS %d\n", cs
);
1484 * FIXME: gpmc_cs_request() will map the CS to an arbitary
1485 * location in the gpmc address space. When booting with
1486 * device-tree we want the NOR flash to be mapped to the
1487 * location specified in the device-tree blob. So remap the
1488 * CS to this location. Once DT migration is complete should
1489 * just make gpmc_cs_request() map a specific address.
1491 ret
= gpmc_cs_remap(cs
, res
.start
);
1493 dev_err(&pdev
->dev
, "cannot remap GPMC CS %d to 0x%x\n",
1498 gpmc_read_settings_dt(child
, &gpmc_s
);
1500 ret
= of_property_read_u32(child
, "bank-width", &gpmc_s
.device_width
);
1504 ret
= gpmc_cs_program_settings(cs
, &gpmc_s
);
1508 gpmc_read_timings_dt(child
, &gpmc_t
);
1509 gpmc_cs_set_timings(cs
, &gpmc_t
);
1511 if (of_platform_device_create(child
, NULL
, &pdev
->dev
))
1514 dev_err(&pdev
->dev
, "failed to create gpmc child %s\n", child
->name
);
1523 static int gpmc_probe_dt(struct platform_device
*pdev
)
1526 struct device_node
*child
;
1527 const struct of_device_id
*of_id
=
1528 of_match_device(gpmc_dt_ids
, &pdev
->dev
);
1533 ret
= of_property_read_u32(pdev
->dev
.of_node
, "gpmc,num-cs",
1536 pr_err("%s: number of chip-selects not defined\n", __func__
);
1538 } else if (gpmc_cs_num
< 1) {
1539 pr_err("%s: all chip-selects are disabled\n", __func__
);
1541 } else if (gpmc_cs_num
> GPMC_CS_NUM
) {
1542 pr_err("%s: number of supported chip-selects cannot be > %d\n",
1543 __func__
, GPMC_CS_NUM
);
1547 ret
= of_property_read_u32(pdev
->dev
.of_node
, "gpmc,num-waitpins",
1550 pr_err("%s: number of wait pins not found!\n", __func__
);
1554 for_each_child_of_node(pdev
->dev
.of_node
, child
) {
1559 if (of_node_cmp(child
->name
, "nand") == 0)
1560 ret
= gpmc_probe_nand_child(pdev
, child
);
1561 else if (of_node_cmp(child
->name
, "onenand") == 0)
1562 ret
= gpmc_probe_onenand_child(pdev
, child
);
1563 else if (of_node_cmp(child
->name
, "ethernet") == 0 ||
1564 of_node_cmp(child
->name
, "nor") == 0)
1565 ret
= gpmc_probe_generic_child(pdev
, child
);
1567 if (WARN(ret
< 0, "%s: probing gpmc child %s failed\n",
1568 __func__
, child
->full_name
))
1575 static int gpmc_probe_dt(struct platform_device
*pdev
)
1581 static int gpmc_probe(struct platform_device
*pdev
)
1585 struct resource
*res
;
1587 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1591 phys_base
= res
->start
;
1592 mem_size
= resource_size(res
);
1594 gpmc_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1595 if (IS_ERR(gpmc_base
))
1596 return PTR_ERR(gpmc_base
);
1598 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1600 dev_warn(&pdev
->dev
, "Failed to get resource: irq\n");
1602 gpmc_irq
= res
->start
;
1604 gpmc_l3_clk
= clk_get(&pdev
->dev
, "fck");
1605 if (IS_ERR(gpmc_l3_clk
)) {
1606 dev_err(&pdev
->dev
, "error: clk_get\n");
1608 return PTR_ERR(gpmc_l3_clk
);
1611 clk_prepare_enable(gpmc_l3_clk
);
1613 gpmc_dev
= &pdev
->dev
;
1615 l
= gpmc_read_reg(GPMC_REVISION
);
1618 * FIXME: Once device-tree migration is complete the below flags
1619 * should be populated based upon the device-tree compatible
1620 * string. For now just use the IP revision. OMAP3+ devices have
1621 * the wr_access and wr_data_mux_bus register fields. OMAP4+
1622 * devices support the addr-addr-data multiplex protocol.
1624 * GPMC IP revisions:
1627 * - OMAP44xx/54xx/AM335x = 6.0
1629 if (GPMC_REVISION_MAJOR(l
) > 0x4)
1630 gpmc_capability
= GPMC_HAS_WR_ACCESS
| GPMC_HAS_WR_DATA_MUX_BUS
;
1631 if (GPMC_REVISION_MAJOR(l
) > 0x5)
1632 gpmc_capability
|= GPMC_HAS_MUX_AAD
;
1633 dev_info(gpmc_dev
, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l
),
1634 GPMC_REVISION_MINOR(l
));
1638 if (gpmc_setup_irq() < 0)
1639 dev_warn(gpmc_dev
, "gpmc_setup_irq failed\n");
1641 /* Now the GPMC is initialised, unreserve the chip-selects */
1644 if (!pdev
->dev
.of_node
) {
1645 gpmc_cs_num
= GPMC_CS_NUM
;
1646 gpmc_nr_waitpins
= GPMC_NR_WAITPINS
;
1649 rc
= gpmc_probe_dt(pdev
);
1651 clk_disable_unprepare(gpmc_l3_clk
);
1652 clk_put(gpmc_l3_clk
);
1653 dev_err(gpmc_dev
, "failed to probe DT parameters\n");
1660 static int gpmc_remove(struct platform_device
*pdev
)
1668 static struct platform_driver gpmc_driver
= {
1669 .probe
= gpmc_probe
,
1670 .remove
= gpmc_remove
,
1672 .name
= DEVICE_NAME
,
1673 .owner
= THIS_MODULE
,
1674 .of_match_table
= of_match_ptr(gpmc_dt_ids
),
1678 static __init
int gpmc_init(void)
1680 return platform_driver_register(&gpmc_driver
);
1683 static __exit
void gpmc_exit(void)
1685 platform_driver_unregister(&gpmc_driver
);
1689 omap_postcore_initcall(gpmc_init
);
1690 module_exit(gpmc_exit
);
1692 static int __init
omap_gpmc_init(void)
1694 struct omap_hwmod
*oh
;
1695 struct platform_device
*pdev
;
1696 char *oh_name
= "gpmc";
1699 * if the board boots up with a populated DT, do not
1700 * manually add the device from this initcall
1702 if (of_have_populated_dt())
1705 oh
= omap_hwmod_lookup(oh_name
);
1707 pr_err("Could not look up %s\n", oh_name
);
1711 pdev
= omap_device_build(DEVICE_NAME
, -1, oh
, NULL
, 0);
1712 WARN(IS_ERR(pdev
), "could not build omap_device for %s\n", oh_name
);
1714 return IS_ERR(pdev
) ? PTR_ERR(pdev
) : 0;
1716 omap_postcore_initcall(omap_gpmc_init
);
1718 static irqreturn_t
gpmc_handle_irq(int irq
, void *dev
)
1723 regval
= gpmc_read_reg(GPMC_IRQSTATUS
);
1728 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
1729 if (regval
& gpmc_client_irq
[i
].bitmask
)
1730 generic_handle_irq(gpmc_client_irq
[i
].irq
);
1732 gpmc_write_reg(GPMC_IRQSTATUS
, regval
);
1737 #ifdef CONFIG_ARCH_OMAP3
1738 static struct omap3_gpmc_regs gpmc_context
;
1740 void omap3_gpmc_save_context(void)
1744 gpmc_context
.sysconfig
= gpmc_read_reg(GPMC_SYSCONFIG
);
1745 gpmc_context
.irqenable
= gpmc_read_reg(GPMC_IRQENABLE
);
1746 gpmc_context
.timeout_ctrl
= gpmc_read_reg(GPMC_TIMEOUT_CONTROL
);
1747 gpmc_context
.config
= gpmc_read_reg(GPMC_CONFIG
);
1748 gpmc_context
.prefetch_config1
= gpmc_read_reg(GPMC_PREFETCH_CONFIG1
);
1749 gpmc_context
.prefetch_config2
= gpmc_read_reg(GPMC_PREFETCH_CONFIG2
);
1750 gpmc_context
.prefetch_control
= gpmc_read_reg(GPMC_PREFETCH_CONTROL
);
1751 for (i
= 0; i
< gpmc_cs_num
; i
++) {
1752 gpmc_context
.cs_context
[i
].is_valid
= gpmc_cs_mem_enabled(i
);
1753 if (gpmc_context
.cs_context
[i
].is_valid
) {
1754 gpmc_context
.cs_context
[i
].config1
=
1755 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG1
);
1756 gpmc_context
.cs_context
[i
].config2
=
1757 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG2
);
1758 gpmc_context
.cs_context
[i
].config3
=
1759 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG3
);
1760 gpmc_context
.cs_context
[i
].config4
=
1761 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG4
);
1762 gpmc_context
.cs_context
[i
].config5
=
1763 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG5
);
1764 gpmc_context
.cs_context
[i
].config6
=
1765 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG6
);
1766 gpmc_context
.cs_context
[i
].config7
=
1767 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG7
);
1772 void omap3_gpmc_restore_context(void)
1776 gpmc_write_reg(GPMC_SYSCONFIG
, gpmc_context
.sysconfig
);
1777 gpmc_write_reg(GPMC_IRQENABLE
, gpmc_context
.irqenable
);
1778 gpmc_write_reg(GPMC_TIMEOUT_CONTROL
, gpmc_context
.timeout_ctrl
);
1779 gpmc_write_reg(GPMC_CONFIG
, gpmc_context
.config
);
1780 gpmc_write_reg(GPMC_PREFETCH_CONFIG1
, gpmc_context
.prefetch_config1
);
1781 gpmc_write_reg(GPMC_PREFETCH_CONFIG2
, gpmc_context
.prefetch_config2
);
1782 gpmc_write_reg(GPMC_PREFETCH_CONTROL
, gpmc_context
.prefetch_control
);
1783 for (i
= 0; i
< gpmc_cs_num
; i
++) {
1784 if (gpmc_context
.cs_context
[i
].is_valid
) {
1785 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG1
,
1786 gpmc_context
.cs_context
[i
].config1
);
1787 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG2
,
1788 gpmc_context
.cs_context
[i
].config2
);
1789 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG3
,
1790 gpmc_context
.cs_context
[i
].config3
);
1791 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG4
,
1792 gpmc_context
.cs_context
[i
].config4
);
1793 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG5
,
1794 gpmc_context
.cs_context
[i
].config5
);
1795 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG6
,
1796 gpmc_context
.cs_context
[i
].config6
);
1797 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG7
,
1798 gpmc_context
.cs_context
[i
].config7
);
1802 #endif /* CONFIG_ARCH_OMAP3 */